From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 41/43] aarch64: Sort fields alphanumerically
Date: Thu, 30 Mar 2023 11:23:57 +0100 [thread overview]
Message-ID: <20230330102359.3327695-42-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
This patch just sorts the field enum alphanumerically, which makes
it easier to see if a particular field has already been defined.
---
opcodes/aarch64-opc.c | 162 ++++++++++++++++++++---------------------
opcodes/aarch64-opc.h | 165 +++++++++++++++++++++---------------------
2 files changed, 164 insertions(+), 163 deletions(-)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index dc4df2ff20c..8a9e51faebd 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -202,74 +202,36 @@ aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
const aarch64_field fields[] =
{
{ 0, 0 }, /* NIL. */
- { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
- { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
- { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
- { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
- { 5, 19 }, /* imm19: e.g. in CBZ. */
- { 5, 19 }, /* immhi: e.g. in ADRP. */
- { 29, 2 }, /* immlo: e.g. in ADRP. */
- { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
- { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
- { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
- { 30, 1 }, /* Q: in most AdvSIMD instructions. */
- { 0, 5 }, /* Rt: in load/store instructions. */
- { 0, 5 }, /* Rd: in many integer instructions. */
- { 5, 5 }, /* Rn: in many integer instructions. */
- { 10, 5 }, /* Rt2: in load/store pair instructions. */
- { 10, 5 }, /* Ra: in fp instructions. */
- { 5, 3 }, /* op2: in the system instructions. */
{ 8, 4 }, /* CRm: in the system instructions. */
+ { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
{ 12, 4 }, /* CRn: in the system instructions. */
- { 16, 3 }, /* op1: in the system instructions. */
- { 19, 2 }, /* op0: in the system instructions. */
- { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
- { 12, 4 }, /* cond: condition flags as a source operand. */
- { 12, 4 }, /* opcode: in advsimd load/store instructions. */
- { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
- { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
- { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
- { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
- { 16, 5 }, /* Rs: in load/store exclusive instructions. */
- { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
- { 12, 1 }, /* S: in load/store reg offset instructions. */
- { 21, 2 }, /* hw: in move wide constant instructions. */
- { 22, 2 }, /* opc: in load/store reg offset instructions. */
- { 23, 1 }, /* opc1: in load/store reg offset instructions. */
- { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
- { 22, 2 }, /* type: floating point type field in fp data inst. */
- { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
- { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
- { 15, 6 }, /* imm6_15: in rmif instructions. */
- { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
- { 0, 4 }, /* imm4_0: in rmif instructions. */
- { 10, 4 }, /* imm4_10: in adddg/subg instructions. */
- { 5, 4 }, /* imm4_5: in SME instructions. */
- { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
- { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
- { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
- { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
- { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
- { 5, 14 }, /* imm14: in test bit and branch instructions. */
- { 5, 16 }, /* imm16_5: in exception instructions. */
- { 0, 16 }, /* imm16_0: in udf instruction. */
- { 0, 26 }, /* imm26: in unconditional branch instructions. */
- { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
- { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
- { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
- { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
- { 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
- { 22, 1 }, /* N: in logical (immediate) instructions. */
- { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
- { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
- { 31, 1 }, /* sf: in integer data processing instructions. */
- { 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
+ { 10, 8 }, /* CSSC_imm8. */
{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
- { 31, 1 }, /* b5: in the test bit and branch instructions. */
- { 19, 5 }, /* b40: in the test bit and branch instructions. */
- { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
+ { 22, 1 }, /* N: in logical (immediate) instructions. */
+ { 30, 1 }, /* Q: in most AdvSIMD instructions. */
+ { 10, 5 }, /* Ra: in fp instructions. */
+ { 0, 5 }, /* Rd: in many integer instructions. */
+ { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
+ { 5, 5 }, /* Rn: in many integer instructions. */
+ { 16, 5 }, /* Rs: in load/store exclusive instructions. */
+ { 0, 5 }, /* Rt: in load/store instructions. */
+ { 10, 5 }, /* Rt2: in load/store pair instructions. */
+ { 12, 1 }, /* S: in load/store reg offset instructions. */
+ { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
+ { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
+ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */
+ { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
+ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
+ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
+ { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
+ { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
+ { 23, 1 }, /* SME_i1: immediate field, bit 23. */
+ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
+ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
+ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
+ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
{ 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
{ 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
{ 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
@@ -295,10 +257,10 @@ const aarch64_field fields[] =
{ 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
+ { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
- { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
- { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
+ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
@@ -315,8 +277,8 @@ const aarch64_field fields[] =
{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
{ 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
- { 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
+ { 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 30, 1 }, /* SVE_sz2: 1-bit element size select. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
@@ -324,25 +286,63 @@ const aarch64_field fields[] =
{ 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
{ 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
{ 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
- { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
- { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
- { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
- { 16, 1 }, /* SME_Q: Q class bit, bit 16. */
- { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
- { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
- { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
- { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
- { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
- { 23, 1 }, /* SME_i1: immediate field, bit 23. */
- { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
- { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
+ { 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
+ { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
+ { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
+ { 19, 5 }, /* b40: in the test bit and branch instructions. */
+ { 31, 1 }, /* b5: in the test bit and branch instructions. */
+ { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
+ { 12, 4 }, /* cond: condition flags as a source operand. */
+ { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
+ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
+ { 21, 2 }, /* hw: in move wide constant instructions. */
+ { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
+ { 0, 4 }, /* imm4_0: in rmif instructions. */
+ { 5, 4 }, /* imm4_5: in SME instructions. */
+ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */
+ { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
+ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
+ { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
+ { 15, 6 }, /* imm6_15: in rmif instructions. */
+ { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
+ { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
+ { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
+ { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
+ { 5, 14 }, /* imm14: in test bit and branch instructions. */
+ { 0, 16 }, /* imm16_0: in udf instruction. */
+ { 5, 16 }, /* imm16_5: in exception instructions. */
+ { 5, 19 }, /* imm19: e.g. in CBZ. */
+ { 0, 26 }, /* imm26: in unconditional branch instructions. */
+ { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
+ { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
+ { 5, 19 }, /* immhi: e.g. in ADRP. */
+ { 29, 2 }, /* immlo: e.g. in ADRP. */
+ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
+ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
+ { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
+ { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
+ { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
+ { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
+ { 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
+ { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
+ { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
+ { 19, 2 }, /* op0: in the system instructions. */
+ { 16, 3 }, /* op1: in the system instructions. */
+ { 5, 3 }, /* op2: in the system instructions. */
+ { 22, 2 }, /* opc: in load/store reg offset instructions. */
+ { 23, 1 }, /* opc1: in load/store reg offset instructions. */
+ { 12, 4 }, /* opcode: in advsimd load/store instructions. */
+ { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
- { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
+ { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
+ { 31, 1 }, /* sf: in integer data processing instructions. */
+ { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
+ { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
{ 22, 1 }, /* sz: 1-bit element size select. */
- { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
- { 10, 8 }, /* CSSC_imm8. */
+ { 22, 2 }, /* type: floating point type field in fp data inst. */
+ { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
};
enum aarch64_operand_class
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index fc1f8087261..3ded6ab7958 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -25,78 +25,41 @@
#include "opcode/aarch64.h"
/* Instruction fields.
- Keep synced with fields. */
+ Keep this sorted alphanumerically and synced with the fields array
+ in aarch64-opc.c. */
enum aarch64_field_kind
{
FLD_NIL,
- FLD_cond2,
- FLD_nzcv,
- FLD_defgh,
- FLD_abc,
- FLD_imm19,
- FLD_immhi,
- FLD_immlo,
- FLD_size,
- FLD_vldst_size,
- FLD_op,
- FLD_Q,
- FLD_Rt,
- FLD_Rd,
- FLD_Rn,
- FLD_Rt2,
- FLD_Ra,
- FLD_op2,
FLD_CRm,
+ FLD_CRm_dsb_nxs,
FLD_CRn,
- FLD_op1,
- FLD_op0,
- FLD_imm3,
- FLD_cond,
- FLD_opcode,
- FLD_cmode,
- FLD_asisdlso_opcode,
- FLD_len,
- FLD_Rm,
- FLD_Rs,
- FLD_option,
- FLD_S,
- FLD_hw,
- FLD_opc,
- FLD_opc1,
- FLD_shift,
- FLD_type,
- FLD_ldst_size,
- FLD_imm6_10,
- FLD_imm6_15,
- FLD_imm4_11,
- FLD_imm4_0,
- FLD_imm4_10,
- FLD_imm4_5,
- FLD_imm5,
- FLD_imm7,
- FLD_imm8,
- FLD_imm9,
- FLD_imm12,
- FLD_imm14,
- FLD_imm16_5,
- FLD_imm16_0,
- FLD_imm26,
- FLD_imms,
- FLD_immr,
- FLD_immb,
- FLD_immh,
- FLD_S_imm10,
- FLD_N,
- FLD_index,
- FLD_index2,
- FLD_sf,
- FLD_lse_sz,
+ FLD_CSSC_imm8,
FLD_H,
FLD_L,
FLD_M,
- FLD_b5,
- FLD_b40,
- FLD_scale,
+ FLD_N,
+ FLD_Q,
+ FLD_Ra,
+ FLD_Rd,
+ FLD_Rm,
+ FLD_Rn,
+ FLD_Rs,
+ FLD_Rt,
+ FLD_Rt2,
+ FLD_S,
+ FLD_SM3_imm2,
+ FLD_SME_Pm,
+ FLD_SME_Q,
+ FLD_SME_Rm,
+ FLD_SME_Rv,
+ FLD_SME_V,
+ FLD_SME_ZAda_2b,
+ FLD_SME_ZAda_3b,
+ FLD_SME_i1,
+ FLD_SME_size_22,
+ FLD_SME_tszh,
+ FLD_SME_tszl,
+ FLD_SME_zero_mask,
FLD_SVE_M_4,
FLD_SVE_M_14,
FLD_SVE_M_16,
@@ -122,10 +85,10 @@ enum aarch64_field_kind
FLD_SVE_Zn,
FLD_SVE_Zt,
FLD_SVE_i1,
+ FLD_SVE_i2h,
FLD_SVE_i3h,
- FLD_SVE_i3l,
FLD_SVE_i3h2,
- FLD_SVE_i2h,
+ FLD_SVE_i3l,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
@@ -142,8 +105,8 @@ enum aarch64_field_kind
FLD_SVE_rot1,
FLD_SVE_rot2,
FLD_SVE_rot3,
- FLD_SVE_sz,
FLD_SVE_size,
+ FLD_SVE_sz,
FLD_SVE_sz2,
FLD_SVE_tsz,
FLD_SVE_tszh,
@@ -151,25 +114,63 @@ enum aarch64_field_kind
FLD_SVE_tszl_19,
FLD_SVE_xs_14,
FLD_SVE_xs_22,
- FLD_SME_ZAda_2b,
- FLD_SME_ZAda_3b,
- FLD_SME_size_22,
- FLD_SME_Q,
- FLD_SME_V,
- FLD_SME_Rv,
- FLD_SME_Pm,
- FLD_SME_zero_mask,
- FLD_SME_Rm,
- FLD_SME_i1,
- FLD_SME_tszh,
- FLD_SME_tszl,
+ FLD_S_imm10,
+ FLD_abc,
+ FLD_asisdlso_opcode,
+ FLD_b40,
+ FLD_b5,
+ FLD_cmode,
+ FLD_cond,
+ FLD_cond2,
+ FLD_defgh,
+ FLD_hw,
+ FLD_imm3,
+ FLD_imm4_0,
+ FLD_imm4_5,
+ FLD_imm4_10,
+ FLD_imm4_11,
+ FLD_imm5,
+ FLD_imm6_10,
+ FLD_imm6_15,
+ FLD_imm7,
+ FLD_imm8,
+ FLD_imm9,
+ FLD_imm12,
+ FLD_imm14,
+ FLD_imm16_0,
+ FLD_imm16_5,
+ FLD_imm19,
+ FLD_imm26,
+ FLD_immb,
+ FLD_immh,
+ FLD_immhi,
+ FLD_immlo,
+ FLD_immr,
+ FLD_imms,
+ FLD_index,
+ FLD_index2,
+ FLD_ldst_size,
+ FLD_len,
+ FLD_lse_sz,
+ FLD_nzcv,
+ FLD_op,
+ FLD_op0,
+ FLD_op1,
+ FLD_op2,
+ FLD_opc,
+ FLD_opc1,
+ FLD_opcode,
+ FLD_option,
FLD_rotate1,
FLD_rotate2,
FLD_rotate3,
- FLD_SM3_imm2,
+ FLD_scale,
+ FLD_sf,
+ FLD_shift,
+ FLD_size,
FLD_sz,
- FLD_CRm_dsb_nxs,
- FLD_CSSC_imm8
+ FLD_type,
+ FLD_vldst_size,
};
/* Field description. */
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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