From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes
Date: Thu, 30 Mar 2023 11:23:35 +0100 [thread overview]
Message-ID: <20230330102359.3327695-20-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
In SME, the vector select register had to be in the range
w12-w15, so it made sense to enforce that during parsing.
However, SME2 adds instructions for which the range is
w8-w11 instead.
This patch therefore moves the range check from the parsing
stage to the constraint-checking stage.
Also, the previous error used a capitalised range W12-W15,
whereas other register range errors used lowercase ranges
like p0-p7. A quick internal poll showed a preference for
the lowercase form, so the patch uses that.
The patch uses "selection register" rather than "vector
select register" so that the terminology extends more
naturally to PSEL.
---
gas/config/tc-aarch64.c | 15 ++++++-------
gas/testsuite/gas/aarch64/sme-2-illegal.l | 10 ++++-----
gas/testsuite/gas/aarch64/sme-5-illegal.l | 4 ++--
gas/testsuite/gas/aarch64/sme-6-illegal.l | 4 ++--
gas/testsuite/gas/aarch64/sme-7-illegal.l | 8 +++----
gas/testsuite/gas/aarch64/sme-9-illegal.l | 12 +++++++----
gas/testsuite/gas/aarch64/sme-9-illegal.s | 4 ++++
opcodes/aarch64-opc.c | 26 +++++++++++++++++------
8 files changed, 51 insertions(+), 32 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index dafd5bc296c..d938aa9eb83 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4372,11 +4372,10 @@ parse_sme_immediate (char **str, int64_t *imm)
return true;
}
-/* Parse index with vector select register and immediate:
+/* Parse index with selection register and immediate offset:
[<Wv>, <imm>]
[<Wv>, #<imm>]
- where <Wv> is in W12-W15 range and # is optional for immediate.
Return true on success, populating OPND with the parsed index. */
@@ -4391,12 +4390,11 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
return false;
}
- /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
+ /* The selection register, encoded in the 2-bit Rv field. */
reg = parse_reg (str);
- if (reg == NULL || reg->type != REG_TYPE_R_32
- || reg->number < 12 || reg->number > 15)
+ if (reg == NULL || reg->type != REG_TYPE_R_32)
{
- set_syntax_error (_("expected vector select register W12-W15"));
+ set_syntax_error (_("expected a 32-bit selection register"));
return false;
}
opnd->index.regno = reg->number;
@@ -4424,9 +4422,8 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
/* Parse a register of type REG_TYPE that might have an element type
qualifier and that is indexed by two values: a 32-bit register,
- followed by an immediate. The 32-bit register must be W12-W15.
- The range of the immediate varies by opcode and is checked in
- libopcodes.
+ followed by an immediate. The ranges of the register and the
+ immediate vary by opcode and are checked in libopcodes.
Return true on success, populating OPND with information about
the operand and setting QUALIFIER to the register qualifier.
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index eaf1b975a81..9d3495aebc0 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -11,12 +11,12 @@
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]'
[^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.h,p0/m,za0v\.h\[w12\. 0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0.q,p0/m,za0v\.q\[w12,\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12\.\]'
[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,abc\]'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index d706a169f3a..14d3cf456f3 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -1,6 +1,6 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index d2a3f3ca09e..b2527ead250 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -1,6 +1,6 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index cee93c85bac..cf4bca2cd20 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -1,22 +1,22 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w14,9\],\[x17,#9,mul#3\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w15,15\],\[sp,#15,mul#4\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w11,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `str za\[w11,0\],\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w14,9\],\[x17,#9,mul#3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
index b0554c5168f..1a33420dc35 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -15,10 +15,14 @@
[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w11\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p8,p11,p15.h\[w16\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p2,p7,p15.s\[w3\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p1,p15,p3.b\[w11,#0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p8,p11,p15.h\[w16,#0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p2,p7,p15.s\[w3,#0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p13,p3,p1.d\[w17,#0\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s
index 2351d711b64..f59582eeb8b 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s
@@ -8,6 +8,10 @@ psel p1, p15, p3.b[w11]
psel p8, p11, p15.h[w16]
psel p2, p7, p15.s[w3]
psel p13, p3, p1.d[w17]
+psel p1, p15, p3.b[w11, #0]
+psel p8, p11, p15.h[w16, #0]
+psel p2, p7, p15.s[w3, #0]
+psel p13, p3, p1.d[w17, #0]
psel p5, p12, p9.b[w15, #16]
psel p1, p8, p6.h[w14, #8]
psel p8, p4, p15.s[w13, #4]
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 746edde7516..24cca9e8193 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1438,14 +1438,28 @@ set_other_error (aarch64_operand_error *mismatch_detail, int idx,
set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
}
-/* Check that indexed ZA operand OPND has a vector select offset
- in the range [0, MAX_VALUE]. */
+/* Check that indexed ZA operand OPND has:
+
+ - a selection register in the range [MIN_WREG, MIN_WREG + 3]
+
+ - an immediate offset in the range [0, MAX_VALUE]. */
static bool
check_za_access (const aarch64_opnd_info *opnd,
aarch64_operand_error *mismatch_detail, int idx,
- int max_value)
+ int min_wreg, int max_value)
{
+ if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
+ {
+ if (min_wreg == 12)
+ set_other_error (mismatch_detail, idx,
+ _("expected a selection register in the"
+ " range w12-w15"));
+ else
+ abort ();
+ return false;
+ }
+
if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_value))
{
set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value);
@@ -1593,7 +1607,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_PnT_Wm_imm:
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
- if (!check_za_access (opnd, mismatch_detail, idx, max_value))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value))
return 0;
break;
@@ -1610,12 +1624,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
- if (!check_za_access (opnd, mismatch_detail, idx, max_value))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value))
return 0;
break;
case AARCH64_OPND_SME_ZA_array:
- if (!check_za_access (opnd, mismatch_detail, idx, 15))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, 15))
return 0;
break;
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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