From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*
Date: Thu, 30 Mar 2023 11:23:22 +0100 [thread overview]
Message-ID: <20230330102359.3327695-7-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
The ZA tile registers were called REG_TYPE_ZA, REG_TYPE_ZAH and
REG_TYPE_ZAV. However, a later patch wants to make plain "za"
a register type too, and REG_TYPE_ZA is the obvious name for that.
This patch therefore adds "T" (tile) to the existing names.
---
gas/config/tc-aarch64.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 4e75946c684..c8b4129202c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -283,9 +283,9 @@ struct reloc_entry
BASIC_REG_TYPE(VN) /* v[0-31] */ \
BASIC_REG_TYPE(ZN) /* z[0-31] */ \
BASIC_REG_TYPE(PN) /* p[0-15] */ \
- BASIC_REG_TYPE(ZA) /* za[0-15] */ \
- BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
- BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
+ BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
+ BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
+ BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
/* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
/* Typecheck: same, plus SVE registers. */ \
@@ -4297,7 +4297,7 @@ static int
parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier)
{
int regno;
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZA, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZAT, qualifier);
if (reg == NULL)
return PARSE_FAIL;
@@ -4448,12 +4448,12 @@ parse_sme_za_hv_tiles_operand (char **str,
const reg_entry *reg;
qh = qv = *str;
- if ((reg = parse_reg_with_qual (&qh, REG_TYPE_ZAH, qualifier)) != NULL)
+ if ((reg = parse_reg_with_qual (&qh, REG_TYPE_ZATH, qualifier)) != NULL)
{
*slice_indicator = HV_horizontal;
*str = qh;
}
- else if ((reg = parse_reg_with_qual (&qv, REG_TYPE_ZAV, qualifier)) != NULL)
+ else if ((reg = parse_reg_with_qual (&qv, REG_TYPE_ZATV, qualifier)) != NULL)
{
*slice_indicator = HV_vertical;
*str = qv;
@@ -4566,7 +4566,8 @@ parse_sme_zero_mask(char **str)
q = *str;
do
{
- const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA, &qualifier);
+ const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZAT,
+ &qualifier);
if (reg)
{
int regno = reg->number;
@@ -8266,13 +8267,13 @@ static const reg_entry reg_names[] = {
REGSET16 (p, PN), REGSET16 (P, PN),
/* SME ZA tile registers. */
- REGSET16 (za, ZA), REGSET16 (ZA, ZA),
+ REGSET16 (za, ZAT), REGSET16 (ZA, ZAT),
/* SME ZA tile registers (horizontal slice). */
- REGSET16S (za, h, ZAH), REGSET16S (ZA, H, ZAH),
+ REGSET16S (za, h, ZATH), REGSET16S (ZA, H, ZATH),
/* SME ZA tile registers (vertical slice). */
- REGSET16S (za, v, ZAV), REGSET16S (ZA, V, ZAV)
+ REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV)
};
#undef REGDEF
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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