From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros
Date: Thu, 30 Mar 2023 11:23:51 +0100 [thread overview]
Message-ID: <20230330102359.3327695-36-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
This patch renames the OP_SME_* macros in aarch64-tbl.h so that
they follow the same scheme as the OP_SVE_* ones. It also uses
OP_SVE_ as the prefix, since there is no real distinction between
the SVE and SME uses of qualifiers: a macro defined for one can
be useful for the other too.
---
opcodes/aarch64-tbl.h | 158 ++++++++++++++++++++----------------------
1 file changed, 77 insertions(+), 81 deletions(-)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 77890fd0f14..7fcc347c3b9 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1438,10 +1438,12 @@
- U: the operand is unqualified (NIL).
- - [BHSD]: the operand has a S_[BHSD] qualifier and the choice of
- qualifier is the same for all variants. This is used for both
- .[BHSD] suffixes on an SVE predicate or vector register and
- scalar FPRs of the form [BHSD]<number>.
+ - [BHSDQ]: the operand has a S_[BHSDQ] qualifier and the choice of
+ qualifier is the same for all variants. This is used for:
+
+ - .[BHSDQ] suffixes on an SVE vector or predicate
+ - .[BHSDQ] suffixes on an SME ZA operand
+ - vector registers and scalar FPRs of the form [BHSDQ]<number>
- [WX]: the operand has a [WX] qualifier and the choice of qualifier
is the same for all variants.
@@ -1450,7 +1452,8 @@
is the same for all variants.
- V: the operand has a S_[BHSD] qualifier and the choice of qualifier
- is not the same for all variants.
+ is not the same for all variants. This is used for the same kinds
+ of operand as [BHSDQ] above.
- R: the operand has a [WX] qualifier and the choice of qualifier is
not the same for all variants.
@@ -1532,6 +1535,18 @@
{ \
QLF3(S_D,S_D,S_D), \
}
+#define OP_SVE_DMMD \
+{ \
+ QLF4(S_D,P_M,P_M,S_D), \
+}
+#define OP_SVE_DMMDD \
+{ \
+ QLF5(S_D,P_M,P_M,S_D,S_D) \
+}
+#define OP_SVE_DMMHH \
+{ \
+ QLF5(S_D,P_M,P_M,S_H,S_H) \
+}
#define OP_SVE_QQQ \
{ \
QLF3(S_Q,S_Q,S_Q), \
@@ -1656,6 +1671,22 @@
{ \
QLF3(S_S,P_M,S_D), \
}
+#define OP_SVE_SMMBB \
+{ \
+ QLF5(S_S,P_M,P_M,S_B,S_B) \
+}
+#define OP_SVE_SMMHH \
+{ \
+ QLF5(S_S,P_M,P_M,S_H,S_H), \
+}
+#define OP_SVE_SMMS \
+{ \
+ QLF4(S_S,P_M,P_M,S_S), \
+}
+#define OP_SVE_SMMSS \
+{ \
+ QLF5(S_S,P_M,P_M,S_S,S_S) \
+}
#define OP_SVE_SSS \
{ \
QLF3(S_S,S_S,S_S), \
@@ -1787,6 +1818,14 @@
QLF3(S_S,P_M,S_S), \
QLF3(S_D,P_M,S_D), \
}
+#define OP_SVE_VMV_BHSDQ \
+{ \
+ QLF3(S_B,P_M,S_B), \
+ QLF3(S_H,P_M,S_H), \
+ QLF3(S_S,P_M,S_S), \
+ QLF3(S_D,P_M,S_D), \
+ QLF3(S_Q,P_M,S_Q) \
+}
#define OP_SVE_VMV_HSD \
{ \
QLF3(S_H,P_M,S_H), \
@@ -2196,49 +2235,6 @@
{ \
QLF3(X,X,NIL), \
}
-/* e.g. ADDVA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S */
-#define OP_SME_ZADA_PN_PM_ZN_S \
-{ \
- QLF4(S_S,P_M,P_M,S_S), \
-}
-/* e.g. ADDVA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D */
-#define OP_SME_ZADA_PN_PM_ZN_D \
-{ \
- QLF4(S_D,P_M,P_M,S_D), \
-}
-/* e.g. BFMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H */
-#define OP_SME_ZADA_PN_PM_ZN_ZM \
-{ \
- QLF5(S_S,P_M,P_M,S_H,S_H), \
-}
-#define OP_SME_ZADA_S_PM_PM_S_S \
-{ \
- QLF5(S_S,P_M,P_M,S_S,S_S) \
-}
-#define OP_SME_ZADA_D_PM_PM_D_D \
-{ \
- QLF5(S_D,P_M,P_M,S_D,S_D) \
-}
-#define OP_SME_ZADA_S_PM_PM_H_H \
-{ \
- QLF5(S_S,P_M,P_M,S_H,S_H) \
-}
-#define OP_SME_ZADA_S_PM_PM_B_B \
-{ \
- QLF5(S_S,P_M,P_M,S_B,S_B) \
-}
-#define OP_SME_ZADA_D_PM_PM_H_H \
-{ \
- QLF5(S_D,P_M,P_M,S_H,S_H) \
-}
-#define OP_SME_BHSDQ_PM_BHSDQ \
-{ \
- QLF3(S_B,P_M,S_B), \
- QLF3(S_H,P_M,S_H), \
- QLF3(S_S,P_M,S_S), \
- QLF3(S_D,P_M,S_D), \
- QLF3(S_Q,P_M,S_Q) \
-}
/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */
#define QL_V3DOT \
@@ -5206,42 +5202,42 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
/* SME instructions. */
- SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0),
- SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0),
+ SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0),
+ SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0),
SME_INSN ("addspl", 0x04605800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
SME_INSN ("addsvl", 0x04205800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
- SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0),
- SME_I16I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0),
- SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0),
- SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0),
- SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0),
- SME_F64F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0),
- SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0),
- SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0),
- SME_F64F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0),
- SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0),
+ SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0),
+ SME_I16I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0),
+ SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
+ SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
+ SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0),
+ SME_F64F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMDD, 0, 0),
+ SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
+ SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0),
+ SME_F64F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMDD, 0, 0),
+ SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
SME_INSN ("rdsvl", 0x04bf5800, 0xfffff800, sme_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0),
- SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
-
- SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+
+ SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0),
SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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