From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 17/43] aarch64: Consolidate ZA slice parsing
Date: Thu, 30 Mar 2023 11:23:33 +0100 [thread overview]
Message-ID: <20230330102359.3327695-18-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
Now that parse_typed_reg checks the range of tile register numbers
and libopcodes checks the range of vector select offsets, there's
very little difference between the parsing of ZA tile indices,
ZA array indices, and PSEL indices. The main one is that ZA
array indices don't currently allow "za" to be qualified,
but we need to remove that restriction for SME2.
This patch therefore consolidates all three parsers into a single
routine, parameterised by the type of register that they expect.
---
gas/config/tc-aarch64.c | 94 ++++++-----------------
gas/testsuite/gas/aarch64/sme-7-illegal.l | 17 ++++
gas/testsuite/gas/aarch64/sme-7-illegal.s | 8 ++
gas/testsuite/gas/aarch64/sme-9-illegal.l | 7 ++
gas/testsuite/gas/aarch64/sme-9-illegal.s | 1 +
5 files changed, 55 insertions(+), 72 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ba7f543e033..e5185353013 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4422,25 +4422,27 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
return true;
}
-/* Parse SME ZA horizontal or vertical vector access to tiles.
+/* Parse a register of type REG_TYPE that might have an element type
+ qualifier and that is indexed by two values: a 32-bit register,
+ followed by an immediate. The 32-bit register must be W12-W15.
+ The range of the immediate varies by opcode and is checked in
+ libopcodes.
+
Return true on success, populating OPND with information about
- the indexed tile and QUALIFIER with the qualifier that was applied
- to the tile name.
+ the operand and setting QUALIFIER to the register qualifier.
Field format examples:
- ZA0<HV>.B[<Wv>, #<imm>]
- <ZAn><HV>.H[<Wv>, #<imm>]
- <ZAn><HV>.S[<Wv>, #<imm>]
- <ZAn><HV>.D[<Wv>, #<imm>]
- <ZAn><HV>.Q[<Wv>, #<imm>]
+ <Pm>.<T>[<Wv>< #<imm>]
+ ZA[<Wv>, #<imm>]
+ <ZAn><HV>.<T>[<Wv>, #<imm>]
*/
static bool
-parse_sme_za_hv_tiles_operand (char **str,
- struct aarch64_indexed_za *opnd,
- aarch64_opnd_qualifier_t *qualifier)
+parse_dual_indexed_reg (char **str, aarch64_reg_type reg_type,
+ struct aarch64_indexed_za *opnd,
+ aarch64_opnd_qualifier_t *qualifier)
{
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier);
if (!reg)
return false;
@@ -4464,7 +4466,7 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
return false;
}
- if (!parse_sme_za_hv_tiles_operand (str, opnd, qualifier))
+ if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier))
return false;
if (!skip_past_char (str, '}'))
@@ -4585,33 +4587,6 @@ parse_sme_list_of_64bit_tiles (char **str)
return regno;
}
-/* Parse ZA array operand used in e.g. STR and LDR instruction.
- Operand format:
-
- ZA[<Wv>, <imm>]
- ZA[<Wv>, #<imm>]
-
- Return true on success, populating OPND with information about
- the operand. */
-
-static bool
-parse_sme_za_array (char **str, struct aarch64_indexed_za *opnd)
-{
- char *q;
-
- q = *str;
- const reg_entry *reg = parse_reg (&q);
- if (!reg || reg->type != REG_TYPE_ZA)
- {
- set_syntax_error (_("expected ZA array"));
- return false;
- }
- opnd->regno = -1;
-
- *str = q;
- return parse_sme_za_index (str, opnd);
-}
-
/* Parse streaming mode operand for SMSTART and SMSTOP.
{SM | ZA}
@@ -4638,32 +4613,6 @@ parse_sme_sm_za (char **str)
return TOLOWER (p[0]);
}
-/* Parse the name of the source scalable predicate register, the index base
- register W12-W15 and the element index. Function performs element index
- limit checks as well as qualifier type checks.
-
- <Pn>.<T>[<Wv>, <imm>]
- <Pn>.<T>[<Wv>, #<imm>]
-
- Return true on success, populating OPND with information about the index
- and setting QUALIFIER to <T>. */
-
-static bool
-parse_sme_pred_reg_with_index (char **str, struct aarch64_indexed_za *opnd,
- aarch64_opnd_qualifier_t *qualifier)
-{
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
- if (reg == NULL)
- return false;
-
- opnd->regno = reg->number;
-
- if (! parse_sme_za_index (str, opnd))
- return false;
-
- return true;
-}
-
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
@@ -7060,9 +7009,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_PnT_Wm_imm:
- /* <Pn>.<T>[<Wm>, #<imm>] */
- if (!parse_sme_pred_reg_with_index (&str, &info->indexed_za,
- &qualifier))
+ if (!parse_dual_indexed_reg (&str, REG_TYPE_PN,
+ &info->indexed_za, &qualifier))
goto failure;
info->qualifier = qualifier;
break;
@@ -7396,8 +7344,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
? !parse_sme_za_hv_tiles_operand_with_braces (&str,
&info->indexed_za,
&qualifier)
- : !parse_sme_za_hv_tiles_operand (&str, &info->indexed_za,
- &qualifier))
+ : !parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
+ &info->indexed_za, &qualifier))
goto failure;
info->qualifier = qualifier;
break;
@@ -7410,8 +7358,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_ZA_array:
- if (!parse_sme_za_array (&str, &info->indexed_za))
+ if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
+ &info->indexed_za, &qualifier))
goto failure;
+ info->qualifier = qualifier;
break;
case AARCH64_OPND_MOPS_ADDR_Rd:
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index 242c5ec75d3..cee93c85bac 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -31,3 +31,20 @@
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]'
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.b\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.h\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.s\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.d\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.q\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `ldr za/z\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `ldr za.2b\[w12,0\],\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s
index 0d92d843a4f..0669fe16dd4 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s
@@ -37,3 +37,11 @@ ldr za[w13, -1], [x17, #1, mul vl]
str za[w13, -1], [x17, #1, mul vl]
ldr za[w13, 1], [x17, #-1, mul vl]
str za[w13, 1], [x17, #-1, mul vl]
+
+ldr za.b[w12, 0], [x0]
+ldr za.h[w12, 0], [x0]
+ldr za.s[w12, 0], [x0]
+ldr za.d[w12, 0], [x0]
+ldr za.q[w12, 0], [x0]
+ldr za/z[w12, 0], [x0]
+ldr za.2b[w12, 0], [x0]
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
index 4d4520c55bd..b0554c5168f 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -8,6 +8,13 @@
[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `psel p1,p15,p3\[w15,#0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: psel p1, p15, p3.b\[w15, 0\]
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
+[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
+[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s
index 88d25fca10b..2351d711b64 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s
@@ -3,6 +3,7 @@
psel p1, p15, p3.b[w12]
psel p1, p15, p3.q[w15]
psel p1, p15, p3.q[w15, #0]
+psel p1, p15, p3[w15,#0]
psel p1, p15, p3.b[w11]
psel p8, p11, p15.h[w16]
psel p2, p7, p15.s[w3]
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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