From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 02/43] aarch64: Restrict range of PRFM opcodes
Date: Thu, 30 Mar 2023 11:23:18 +0100 [thread overview]
Message-ID: <20230330102359.3327695-3-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
In the register-index forms of PRFM, the unallocated prefetch opcodes
24-31 have been reused for the encoding of the new RPRFM instruction.
The PRFM opcode space is now capped at 23 for these forms. The other
forms of PRFM are unaffected.
---
gas/testsuite/gas/aarch64/illegal.l | 6 +++++-
gas/testsuite/gas/aarch64/illegal.s | 5 +++++
gas/testsuite/gas/aarch64/system.d | 18 ++----------------
gas/testsuite/gas/aarch64/system.s | 5 +++++
opcodes/aarch64-opc.c | 9 +++++++++
5 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 65bd38afd7a..ae9bb939728 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -879,4 +879,8 @@
[^:]*:593: Error: .*`st2 {v0\.16b-v1\.16b}\[1\],\[x0\]'
[^:]*:594: Error: .*`st3 {v0\.16b-v2\.16b}\[2\],\[x0\]'
[^:]*:595: Error: .*`st4 {v0\.8b-v3\.8b}\[4\],\[x0\]'
-[^:]*:597: Error: .*
+[^:]*:597: Error: the register-index form of PRFM does not accept opcodes in the range 24-31 at operand 1 -- `prfm #0x18,\[sp,x15,lsl#0\]'
+[^:]*:598: Error: the register-index form of PRFM does not accept opcodes in the range 24-31 at operand 1 -- `prfm #0x1f,\[sp,x15,lsl#0\]'
+[^:]*:599: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm #0x20,\[sp,x15,lsl#0\]'
+[^:]*:600: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm #0x20,FOO'
+[^:]*:602: Error: .*
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index 384b673e8fb..6fb637ab923 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -594,4 +594,9 @@ one_label:
st3 {v0.16b-v2.16b}[2],[x0]
st4 {v0.8b-v3.8b}[4],[x0]
+ prfm #0x18, [sp, x15, lsl #0]
+ prfm #0x1f, [sp, x15, lsl #0]
+ prfm #0x20, [sp, x15, lsl #0]
+ prfm #0x20, FOO
+
// End (for errors during literal pool generation)
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index 93c84a72982..7e4bafbf1ff 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -330,43 +330,27 @@ Disassembly of section \.text:
.*: f9800c77 prfm #0x17, \[x3, #24\]
.*: d8000018 prfm #0x18, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bf8 prfm #0x18, \[sp, x15\]
-.*: f8be58f8 prfm #0x18, \[x7, w30, uxtw #3\]
.*: f9800c78 prfm #0x18, \[x3, #24\]
.*: d8000019 prfm #0x19, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bf9 prfm #0x19, \[sp, x15\]
-.*: f8be58f9 prfm #0x19, \[x7, w30, uxtw #3\]
.*: f9800c79 prfm #0x19, \[x3, #24\]
.*: d800001a prfm #0x1a, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfa prfm #0x1a, \[sp, x15\]
-.*: f8be58fa prfm #0x1a, \[x7, w30, uxtw #3\]
.*: f9800c7a prfm #0x1a, \[x3, #24\]
.*: d800001b prfm #0x1b, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfb prfm #0x1b, \[sp, x15\]
-.*: f8be58fb prfm #0x1b, \[x7, w30, uxtw #3\]
.*: f9800c7b prfm #0x1b, \[x3, #24\]
.*: d800001c prfm #0x1c, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfc prfm #0x1c, \[sp, x15\]
-.*: f8be58fc prfm #0x1c, \[x7, w30, uxtw #3\]
.*: f9800c7c prfm #0x1c, \[x3, #24\]
.*: d800001d prfm #0x1d, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfd prfm #0x1d, \[sp, x15\]
-.*: f8be58fd prfm #0x1d, \[x7, w30, uxtw #3\]
.*: f9800c7d prfm #0x1d, \[x3, #24\]
.*: d800001e prfm #0x1e, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfe prfm #0x1e, \[sp, x15\]
-.*: f8be58fe prfm #0x1e, \[x7, w30, uxtw #3\]
.*: f9800c7e prfm #0x1e, \[x3, #24\]
.*: d800001f prfm #0x1f, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bff prfm #0x1f, \[sp, x15\]
-.*: f8be58ff prfm #0x1f, \[x7, w30, uxtw #3\]
.*: f9800c7f prfm #0x1f, \[x3, #24\]
.*: f9800c60 prfm pldl1keep, \[x3, #24\]
.*: f9800c61 prfm pldl1strm, \[x3, #24\]
@@ -386,3 +370,5 @@ Disassembly of section \.text:
.*: f9800c73 prfm pstl2strm, \[x3, #24\]
.*: f9800c74 prfm pstl3keep, \[x3, #24\]
.*: f9800c75 prfm pstl3strm, \[x3, #24\]
+.*: f8a04817 prfm #0x17, \[x0, w0, uxtw\]
+.*: f8a04818 \.inst 0xf8a04818 ; undefined
diff --git a/gas/testsuite/gas/aarch64/system.s b/gas/testsuite/gas/aarch64/system.s
index 4d24d9a7614..48e7bfeb103 100644
--- a/gas/testsuite/gas/aarch64/system.s
+++ b/gas/testsuite/gas/aarch64/system.s
@@ -70,8 +70,10 @@
.macro all_prefetchs op, from=0, to=31
\op \from, LABEL1
+ .if \from < 24
\op \from, [sp, x15, lsl #0]
\op \from, [x7, w30, uxtw #3]
+ .endif
\op \from, [x3, #24]
.if \to-\from
all_prefetchs \op, "(\from+1)", \to
@@ -91,3 +93,6 @@
.endr
.endr
.endr
+
+ .inst 0xf8a04817
+ .inst 0xf8a04818
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e271b0d5e8e..a0e6240592c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2599,6 +2599,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
}
break;
+ case AARCH64_OPND_PRFOP:
+ if (opcode->iclass == ldst_regoff && opnd->prfop->value >= 24)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("the register-index form of PRFM does"
+ " not accept opcodes in the range 24-31"));
+ return 0;
+ }
+ break;
default:
break;
}
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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