From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 00/27] sim: sim_cpu: invert sim_cpu storage
Date: Tue, 1 Nov 2022 20:56:31 +0545 [thread overview]
Message-ID: <20221101151158.24916-1-vapier@gentoo.org> (raw)
This is similar to the patch series for inverting sim_state storage:
https://sourceware.org/pipermail/gdb-patches/2021-May/178806.html
There's more patches here than that series because every arch defines
a custom sim_cpu with real content.
Basically we:
1) rename the per-arch "sim_cpu" type to "$arch_sim_cpu",
2) rename the common "sim_cpu_base" to "sim_cpu",
3) add a new "arch_data" to the new common "sim_cpu",
4) define $ARCH_SIM_CPU macro to turn common sim_cpu into the
$arch_sim_cpu data.
This is another required step along the way to creating a single sim
with multiple arch backends in it -- we can't have common data structs
(like "sim_cpu" which is used everywhere) having completely different
layouts & contents between archs.
Mike Frysinger (27):
sim: sim_cpu: invert sim_cpu storage
sim: bfin: invert sim_cpu storage
sim: ft32: invert sim_cpu storage
sim: msp430: invert sim_cpu storage
sim: moxie: invert sim_cpu storage
sim: avr: invert sim_cpu storage
sim: microblaze: invert sim_cpu storage
sim: aarch64: invert sim_cpu storage
sim: mcore: invert sim_cpu storage
sim: v850: invert sim_cpu storage
sim: mips: invert sim_cpu storage
sim: m68hc11: invert sim_cpu storage
sim: h8300: switch to cpu for state
sim: h8300: invert sim_cpu storage
sim: example-synacor: invert sim_cpu storage
sim: pru: invert sim_cpu storage
sim: riscv: invert sim_cpu storage
sim: cgen: prep for inverting sim_cpu storage
sim: bpf: invert sim_cpu storage
sim: cris: invert sim_cpu storage
sim: frv: invert sim_cpu storage
sim: iq2000: invert sim_cpu storage
sim: lm32: invert sim_cpu storage
sim: m32r: invert sim_cpu storage
sim: or1k: invert sim_cpu storage
sim: enable common sim_cpu usage everywhere
sim: fully merge sim_cpu_base into sim_cpu
sim/aarch64/cpustate.c | 242 +++++++-----
sim/aarch64/cpustate.h | 2 +-
sim/aarch64/interp.c | 3 +-
sim/aarch64/sim-main.h | 6 +-
sim/aarch64/simulator.c | 5 +-
sim/arm/sim-main.h | 5 -
sim/avr/interp.c | 201 +++++-----
sim/avr/sim-main.h | 6 +-
sim/bfin/interp.c | 5 +-
sim/bfin/sim-main.h | 8 +-
sim/bpf/cpu.h | 2 +-
sim/bpf/sim-main.h | 7 +-
sim/common/cgen-cpu.h | 5 +
sim/common/sim-cpu.c | 18 +-
sim/common/sim-cpu.h | 61 +--
sim/cr16/sim-main.h | 5 -
sim/cris/cpuv10.h | 2 +-
sim/cris/cpuv32.h | 2 +-
sim/cris/cris-tmpl.c | 19 +-
sim/cris/sim-if.c | 28 +-
sim/cris/sim-main.h | 15 +-
sim/cris/traps.c | 412 +++++++++----------
sim/d10v/sim-main.h | 5 -
sim/example-synacor/interp.c | 3 +-
sim/example-synacor/sim-main.c | 72 ++--
sim/example-synacor/sim-main.h | 7 +-
sim/frv/cpu.h | 2 +-
sim/frv/sim-main.h | 35 +-
sim/ft32/ft32-sim.h | 2 +
sim/ft32/interp.c | 181 +++++----
sim/ft32/sim-main.h | 9 -
sim/h8300/compile.c | 700 ++++++++++++++-------------------
sim/h8300/sim-main.h | 9 +-
sim/iq2000/cpu.h | 2 +-
sim/iq2000/sim-main.h | 11 +-
sim/lm32/cpu.h | 2 +-
sim/lm32/sim-main.h | 12 +-
sim/m32r/cpu.h | 2 +-
sim/m32r/cpu2.h | 2 +-
sim/m32r/cpux.h | 2 +-
sim/m32r/sim-main.h | 13 +-
sim/m68hc11/dv-m68hc11.c | 121 +++---
sim/m68hc11/dv-m68hc11eepr.c | 42 +-
sim/m68hc11/dv-m68hc11sio.c | 76 ++--
sim/m68hc11/dv-m68hc11spi.c | 45 ++-
sim/m68hc11/dv-m68hc11tim.c | 128 +++---
sim/m68hc11/emulos.c | 4 +-
sim/m68hc11/interp.c | 59 +--
sim/m68hc11/interrupts.c | 14 +-
sim/m68hc11/m68hc11_sim.c | 195 ++++-----
sim/m68hc11/sim-main.h | 114 +++---
sim/mcore/interp.c | 59 +--
sim/mcore/sim-main.h | 7 +-
sim/microblaze/interp.c | 7 +-
sim/microblaze/microblaze.h | 2 +-
sim/microblaze/sim-main.h | 5 +-
sim/mips/interp.c | 112 +++---
sim/mips/sim-main.h | 49 ++-
sim/mn10300/sim-main.h | 11 -
sim/moxie/interp.c | 9 +-
sim/moxie/sim-main.h | 16 +-
sim/msp430/msp430-sim.c | 212 +++++-----
sim/msp430/msp430-sim.h | 2 +-
sim/msp430/sim-main.h | 10 +-
sim/or1k/cpu.h | 2 +-
sim/or1k/or1k.c | 36 +-
sim/or1k/sim-main.h | 12 +-
sim/or1k/traps.c | 18 +-
sim/pru/interp.c | 28 +-
sim/pru/pru.h | 2 +-
sim/pru/sim-main.h | 5 +-
sim/riscv/sim-main.c | 439 ++++++++++++---------
sim/riscv/sim-main.h | 5 +-
sim/sh/sim-main.h | 5 -
sim/v850/interp.c | 15 +-
sim/v850/sim-main.h | 22 +-
sim/v850/v850.igen | 4 +-
77 files changed, 2068 insertions(+), 1954 deletions(-)
--
2.37.3
next reply other threads:[~2022-11-01 16:26 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 Mike Frysinger [this message]
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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