From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 14/27] sim: h8300: invert sim_cpu storage
Date: Tue, 1 Nov 2022 20:56:45 +0545 [thread overview]
Message-ID: <20221101151158.24916-15-vapier@gentoo.org> (raw)
In-Reply-To: <20221101151158.24916-1-vapier@gentoo.org>
---
sim/h8300/compile.c | 59 ++++++++++++++++++++++----------------------
sim/h8300/sim-main.h | 11 +++++----
2 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 45be27c5eedc..ad716c7c6b8a 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -57,13 +57,13 @@ static int memory_size;
static unsigned int
h8_get_reg (sim_cpu *cpu, int regnum)
{
- return cpu->regs[regnum];
+ return H8300_SIM_CPU (cpu)->regs[regnum];
}
static void
h8_set_reg (sim_cpu *cpu, int regnum, int val)
{
- cpu->regs[regnum] = val;
+ H8300_SIM_CPU (cpu)->regs[regnum] = val;
}
#define h8_get_ccr(cpu) h8_get_reg (cpu, CCR_REGNUM)
@@ -88,25 +88,25 @@ h8_set_reg (sim_cpu *cpu, int regnum, int val)
static int
h8_get_mask (sim_cpu *cpu)
{
- return cpu->mask;
+ return H8300_SIM_CPU (cpu)->mask;
}
static void
h8_set_mask (sim_cpu *cpu, int val)
{
- cpu->mask = val;
+ H8300_SIM_CPU (cpu)->mask = val;
}
#if 0
static int
h8_get_exception (sim_cpu *cpu)
{
- return cpu->exception;
+ return H8300_SIM_CPU (cpu)->exception;
}
static void
h8_set_exception (sim_cpu *cpu, int val)
{
- cpu->exception = val;
+ H8300_SIM_CPU (cpu)->exception = val;
}
static enum h8300_sim_state
@@ -125,7 +125,7 @@ h8_set_state (SIM_DESC sd, enum h8300_sim_state val)
static unsigned int *
h8_get_reg_buf (sim_cpu *cpu)
{
- return &cpu->regs[0];
+ return &H8300_SIM_CPU (cpu)->regs[0];
}
#ifdef ADEBUG
@@ -145,77 +145,77 @@ h8_increment_stats (SIM_DESC sd, int idx)
static unsigned char *
h8_get_memory_buf (sim_cpu *cpu)
{
- return cpu->memory;
+ return H8300_SIM_CPU (cpu)->memory;
}
static void
h8_set_memory_buf (sim_cpu *cpu, unsigned char *ptr)
{
- cpu->memory = ptr;
+ H8300_SIM_CPU (cpu)->memory = ptr;
}
static unsigned char
h8_get_memory (sim_cpu *cpu, int idx)
{
ASSERT (idx < memory_size);
- return cpu->memory[idx];
+ return H8300_SIM_CPU (cpu)->memory[idx];
}
static void
h8_set_memory (sim_cpu *cpu, int idx, unsigned int val)
{
ASSERT (idx < memory_size);
- cpu->memory[idx] = (unsigned char) val;
+ H8300_SIM_CPU (cpu)->memory[idx] = (unsigned char) val;
}
static unsigned int
h8_get_delayed_branch (sim_cpu *cpu)
{
- return cpu->delayed_branch;
+ return H8300_SIM_CPU (cpu)->delayed_branch;
}
static void
h8_set_delayed_branch (sim_cpu *cpu, unsigned int dest)
{
- cpu->delayed_branch = dest;
+ H8300_SIM_CPU (cpu)->delayed_branch = dest;
}
static char **
h8_get_command_line (sim_cpu *cpu)
{
- return cpu->command_line;
+ return H8300_SIM_CPU (cpu)->command_line;
}
static void
h8_set_command_line (sim_cpu *cpu, char ** val)
{
- cpu->command_line = val;
+ H8300_SIM_CPU (cpu)->command_line = val;
}
static char *
h8_get_cmdline_arg (sim_cpu *cpu, int index)
{
- return cpu->command_line[index];
+ return H8300_SIM_CPU (cpu)->command_line[index];
}
static void
h8_set_cmdline_arg (sim_cpu *cpu, int index, char * val)
{
- cpu->command_line[index] = val;
+ H8300_SIM_CPU (cpu)->command_line[index] = val;
}
/* MAC Saturation Mode */
static int
h8_get_macS (sim_cpu *cpu)
{
- return cpu->macS;
+ return H8300_SIM_CPU (cpu)->macS;
}
#if 0
static void
h8_set_macS (sim_cpu *cpu, int val)
{
- cpu->macS = (val != 0);
+ H8300_SIM_CPU (cpu)->macS = (val != 0);
}
#endif
@@ -223,39 +223,39 @@ h8_set_macS (sim_cpu *cpu, int val)
static int
h8_get_macZ (sim_cpu *cpu)
{
- return cpu->macZ;
+ return H8300_SIM_CPU (cpu)->macZ;
}
static void
h8_set_macZ (sim_cpu *cpu, int val)
{
- cpu->macZ = (val != 0);
+ H8300_SIM_CPU (cpu)->macZ = (val != 0);
}
/* MAC Negative Flag */
static int
h8_get_macN (sim_cpu *cpu)
{
- return cpu->macN;
+ return H8300_SIM_CPU (cpu)->macN;
}
static void
h8_set_macN (sim_cpu *cpu, int val)
{
- cpu->macN = (val != 0);
+ H8300_SIM_CPU (cpu)->macN = (val != 0);
}
/* MAC Overflow Flag */
static int
h8_get_macV (sim_cpu *cpu)
{
- return cpu->macV;
+ return H8300_SIM_CPU (cpu)->macV;
}
static void
h8_set_macV (sim_cpu *cpu, int val)
{
- cpu->macV = (val != 0);
+ H8300_SIM_CPU (cpu)->macV = (val != 0);
}
/* End CPU data object. */
@@ -1593,7 +1593,7 @@ init_pointers (SIM_DESC sd)
h8_set_mask (cpu, memory_size - 1);
- memset (h8_get_reg_buf (cpu), 0, sizeof (cpu->regs));
+ memset (h8_get_reg_buf (cpu), 0, sizeof (H8300_SIM_CPU (cpu)->regs));
for (i = 0; i < 8; i++)
{
@@ -4589,13 +4589,13 @@ static const OPTION h8300_options[] =
static sim_cia
h8300_pc_get (sim_cpu *cpu)
{
- return cpu->pc;
+ return H8300_SIM_CPU (cpu)->pc;
}
static void
h8300_pc_set (sim_cpu *cpu, sim_cia pc)
{
- cpu->pc = pc;
+ H8300_SIM_CPU (cpu)->pc = pc;
}
/* Cover function of sim_state_free to free the cpu buffers as well. */
@@ -4626,7 +4626,8 @@ sim_open (SIM_OPEN_KIND kind,
current_target_byte_order = BFD_ENDIAN_BIG;
/* The cpu data is kept in a separately allocated chunk of memory. */
- if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+ if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct h8300_sim_cpu))
+ != SIM_RC_OK)
{
free_state (sd);
return 0;
diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h
index f27ba6827381..d0a04f5fa46a 100644
--- a/sim/h8300/sim-main.h
+++ b/sim/h8300/sim-main.h
@@ -5,6 +5,8 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
+#define SIM_HAVE_COMMON_SIM_CPU
+
#define DEBUG
/* These define the size of main memory for the simulator.
@@ -114,7 +116,7 @@ typedef struct
#endif
} decoded_inst;
-struct _sim_cpu {
+struct h8300_sim_cpu {
unsigned int regs[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
unsigned int pc;
@@ -128,9 +130,8 @@ struct _sim_cpu {
unsigned char *memory;
int mask;
-
- sim_cpu_base base;
};
+#define H8300_SIM_CPU(sd) ((struct h8300_sim_cpu *) CPU_ARCH_DATA (sd))
struct h8300_sim_state {
unsigned long memory_size;
@@ -142,8 +143,8 @@ struct h8300_sim_state {
/* The current state of the processor; registers, memory, etc. */
-#define cpu_set_pc(CPU, VAL) (((CPU)->pc) = (VAL))
-#define cpu_get_pc(CPU) (((CPU)->pc))
+#define cpu_set_pc(cpu, val) (H8300_SIM_CPU (cpu)->pc = (val))
+#define cpu_get_pc(cpu) (H8300_SIM_CPU (cpu)->pc)
/* Magic numbers used to distinguish an exit from a breakpoint. */
#define LIBC_EXIT_MAGIC1 0xdead
--
2.37.3
next prev parent reply other threads:[~2022-11-01 16:26 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` Mike Frysinger [this message]
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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