From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 24/26] sim: or1k: invert sim_cpu storage
Date: Sat, 5 Nov 2022 20:32:56 +0700 [thread overview]
Message-ID: <20221105133258.23409-25-vapier@gentoo.org> (raw)
In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org>
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
---
sim/or1k/cpu.h | 2 +-
sim/or1k/or1k.c | 36 ++++++++++++++++++++++++------------
sim/or1k/sim-if.c | 3 ++-
sim/or1k/sim-main.h | 14 +++++---------
sim/or1k/traps.c | 18 +++++++++++-------
5 files changed, 43 insertions(+), 30 deletions(-)
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
index f0d37ea2ae27..fa378c4fd2f0 100644
--- a/sim/or1k/cpu.h
+++ b/sim/or1k/cpu.h
@@ -72,7 +72,7 @@ SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))),
#define GET_H_ROFF1() CPU (h_roff1)
#define SET_H_ROFF1(x) (CPU (h_roff1) = (x))
} hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+#define CPU_CGEN_HW(cpu) (& OR1K_SIM_CPU (cpu)->cpu_data.hardware)
} OR1K32BF_CPU_DATA;
/* Virtual regs. */
diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c
index 1d2d51fd9c6e..1386176e708d 100644
--- a/sim/or1k/or1k.c
+++ b/sim/or1k/or1k.c
@@ -104,32 +104,40 @@ USI
or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SIM_ASSERT (addr < NUM_SPR);
- return current_cpu->spr[addr];
+ return or1k_cpu->spr[addr];
}
void
or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SIM_ASSERT (addr < NUM_SPR);
- current_cpu->spr[addr] = val;
+ or1k_cpu->spr[addr] = val;
}
USI
or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SIM_ASSERT (addr < NUM_SPR);
- return LSEXTRACTED (current_cpu->spr[addr], msb, lsb);
+ return LSEXTRACTED (or1k_cpu->spr[addr], msb, lsb);
}
void
or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb,
USI val)
{
- current_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
- current_cpu->spr[addr] |= LSINSERTED (val, msb, lsb);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
+ or1k_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
+ or1k_cpu->spr[addr] |= LSINSERTED (val, msb, lsb);
}
/* Initialize a sim cpu object. */
@@ -137,6 +145,8 @@ void
or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
const USI or1k_upr, const USI or1k_cpucfgr)
{
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
/* Set the configuration registers passed from the user. */
SET_H_SYS_VR (or1k_vr);
SET_H_SYS_UPR (or1k_upr);
@@ -153,8 +163,8 @@ or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
} while (0)
/* Set flags indicating if we are in a delay slot or not. */
- current_cpu->next_delay_slot = 0;
- current_cpu->delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
+ or1k_cpu->delay_slot = 0;
/* Verify any user passed fields and warn on configurations we don't
support. */
@@ -202,11 +212,12 @@ void
or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
- current_cpu->delay_slot = current_cpu->next_delay_slot;
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->delay_slot = or1k_cpu->next_delay_slot;
+ or1k_cpu->next_delay_slot = 0;
- if (current_cpu->delay_slot &&
+ if (or1k_cpu->delay_slot &&
CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT))
{
@@ -226,6 +237,7 @@ void
or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
USI ppc;
#ifdef WITH_SCACHE
@@ -240,8 +252,8 @@ or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI))
{
- SIM_ASSERT (!current_cpu->delay_slot);
- current_cpu->next_delay_slot = 1;
+ SIM_ASSERT (!or1k_cpu->delay_slot);
+ or1k_cpu->next_delay_slot = 1;
}
}
diff --git a/sim/or1k/sim-if.c b/sim/or1k/sim-if.c
index 798a60ac7caf..a60c8815772b 100644
--- a/sim/or1k/sim-if.c
+++ b/sim/or1k/sim-if.c
@@ -168,7 +168,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
current_target_byte_order = BFD_ENDIAN_BIG;
/* The cpu data is kept in a separately allocated chunk of memory. */
- if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+ if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct or1k_sim_cpu))
+ != SIM_RC_OK)
{
free_state (sd);
return 0;
diff --git a/sim/or1k/sim-main.h b/sim/or1k/sim-main.h
index 4f7b1084b1b4..bf3558ddfef1 100644
--- a/sim/or1k/sim-main.h
+++ b/sim/or1k/sim-main.h
@@ -19,6 +19,8 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
+#define SIM_HAVE_COMMON_SIM_CPU
+
#define WITH_SCACHE_PBB 1
#include "ansidecl.h"
@@ -35,17 +37,10 @@
#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */
-/* The _sim_cpu struct. */
-struct _sim_cpu
+struct or1k_sim_cpu
{
- /* sim/common cpu base. */
- sim_cpu_base base;
-
- /* Static parts of cgen. */
- CGEN_CPU cgen_cpu;
-
OR1K_MISC_PROFILE or1k_misc_profile;
-#define CPU_OR1K_MISC_PROFILE(cpu) (& (cpu)->or1k_misc_profile)
+#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile)
/* CPU specific parts go here.
Note that in files that don't need to access these pieces WANT_CPU_FOO
@@ -65,5 +60,6 @@ struct _sim_cpu
OR1K32BF_CPU_DATA cpu_data;
#endif
};
+#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu))
#endif /* SIM_MAIN_H */
diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c
index d816810039d2..97e81f41e7da 100644
--- a/sim/or1k/traps.c
+++ b/sim/or1k/traps.c
@@ -123,6 +123,7 @@ void
or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
if (exnum == EXCEPT_TRAP)
{
@@ -142,14 +143,14 @@ or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
case EXCEPT_FPE:
case EXCEPT_SYSCALL:
- SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0));
+ SET_H_SYS_EPCR0 (pc + 4 - (or1k_cpu->delay_slot ? 4 : 0));
break;
case EXCEPT_BUSERR:
case EXCEPT_ALIGN:
case EXCEPT_ILLEGAL:
case EXCEPT_RANGE:
- SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0));
+ SET_H_SYS_EPCR0 (pc - (or1k_cpu->delay_slot ? 4 : 0));
break;
default:
@@ -162,9 +163,9 @@ or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
SET_H_SYS_ESR0 (GET_H_SYS_SR ());
/* Indicate in SR if the failed instruction is in delay slot or not. */
- SET_H_SYS_SR_DSX (current_cpu->delay_slot);
+ SET_H_SYS_SR_DSX (or1k_cpu->delay_slot);
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
/* Jump program counter into handler. */
handler_pc =
@@ -180,10 +181,12 @@ or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
void
or1k32bf_rfe (sim_cpu *current_cpu)
{
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SET_H_SYS_SR (GET_H_SYS_ESR0 ());
SET_H_SYS_SR_FO (1);
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
GET_H_SYS_EPCR0 ());
@@ -246,6 +249,7 @@ void
or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
{
@@ -275,9 +279,9 @@ or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
break;
case SPR_ADDR (SYS, NPC):
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
- sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, val);
+ sim_engine_restart (sd, current_cpu, NULL, val);
break;
case SPR_ADDR (TICK, TTMR):
--
2.38.1
next prev parent reply other threads:[~2022-11-05 13:33 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` Mike Frysinger [this message]
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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