From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 14/26] sim: example-synacor: invert sim_cpu storage
Date: Sat, 5 Nov 2022 20:32:46 +0700 [thread overview]
Message-ID: <20221105133258.23409-15-vapier@gentoo.org> (raw)
In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org>
---
sim/example-synacor/interp.c | 3 +-
sim/example-synacor/sim-main.c | 72 +++++++++++++++++++---------------
sim/example-synacor/sim-main.h | 9 +++--
3 files changed, 47 insertions(+), 37 deletions(-)
diff --git a/sim/example-synacor/interp.c b/sim/example-synacor/interp.c
index 57442b706d37..cbde166c9b32 100644
--- a/sim/example-synacor/interp.c
+++ b/sim/example-synacor/interp.c
@@ -88,7 +88,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
current_target_byte_order = BFD_ENDIAN_LITTLE;
/* The cpu data is kept in a separately allocated chunk of memory. */
- if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+ if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct example_sim_cpu))
+ != SIM_RC_OK)
{
free_state (sd);
return 0;
diff --git a/sim/example-synacor/sim-main.c b/sim/example-synacor/sim-main.c
index 75d5c6bc471c..0757d6925c8f 100644
--- a/sim/example-synacor/sim-main.c
+++ b/sim/example-synacor/sim-main.c
@@ -34,7 +34,7 @@ register_num (SIM_CPU *cpu, uint16_t num)
SIM_DESC sd = CPU_STATE (cpu);
if (num < 0x8000 || num >= 0x8008)
- sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, SIM_SIGILL);
return num & 0xf;
}
@@ -44,6 +44,7 @@ static uint16_t
interp_num (SIM_CPU *cpu, uint16_t num)
{
SIM_DESC sd = CPU_STATE (cpu);
+ struct example_sim_cpu *example_cpu = EXAMPLE_SIM_CPU (cpu);
if (num < 0x8000)
{
@@ -55,13 +56,13 @@ interp_num (SIM_CPU *cpu, uint16_t num)
{
/* Numbers 32768..32775 instead mean registers 0..7. */
TRACE_DECODE (cpu, "%#x is register R%i", num, num & 0xf);
- return cpu->regs[num & 0xf];
+ return example_cpu->regs[num & 0xf];
}
else
{
/* Numbers 32776..65535 are invalid. */
TRACE_DECODE (cpu, "%#x is an invalid number", num);
- sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ sim_engine_halt (sd, cpu, NULL, example_cpu->pc, sim_signalled, SIM_SIGILL);
}
}
\f
@@ -69,6 +70,7 @@ interp_num (SIM_CPU *cpu, uint16_t num)
void step_once (SIM_CPU *cpu)
{
SIM_DESC sd = CPU_STATE (cpu);
+ struct example_sim_cpu *example_cpu = EXAMPLE_SIM_CPU (cpu);
uint16_t iw1, num1;
sim_cia pc = sim_pc_get (cpu);
@@ -96,7 +98,7 @@ void step_once (SIM_CPU *cpu)
TRACE_INSN (cpu, "SET R%i %#x", num2, num3);
TRACE_REGISTER (cpu, "R%i = %#x", num2, num3);
- cpu->regs[num2] = num3;
+ example_cpu->regs[num2] = num3;
pc += 6;
}
@@ -110,9 +112,9 @@ void step_once (SIM_CPU *cpu)
TRACE_EXTRACT (cpu, "PUSH %#x", iw2);
TRACE_INSN (cpu, "PUSH %#x", num2);
- sim_core_write_aligned_2 (cpu, pc, write_map, cpu->sp, num2);
- cpu->sp -= 2;
- TRACE_REGISTER (cpu, "SP = %#x", cpu->sp);
+ sim_core_write_aligned_2 (cpu, pc, write_map, example_cpu->sp, num2);
+ example_cpu->sp -= 2;
+ TRACE_REGISTER (cpu, "SP = %#x", example_cpu->sp);
pc += 4;
}
@@ -126,12 +128,12 @@ void step_once (SIM_CPU *cpu)
num2 = register_num (cpu, iw2);
TRACE_EXTRACT (cpu, "POP %#x", iw2);
TRACE_INSN (cpu, "POP R%i", num2);
- cpu->sp += 2;
- TRACE_REGISTER (cpu, "SP = %#x", cpu->sp);
- result = sim_core_read_aligned_2 (cpu, pc, read_map, cpu->sp);
+ example_cpu->sp += 2;
+ TRACE_REGISTER (cpu, "SP = %#x", example_cpu->sp);
+ result = sim_core_read_aligned_2 (cpu, pc, read_map, example_cpu->sp);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 4;
}
@@ -153,7 +155,7 @@ void step_once (SIM_CPU *cpu)
TRACE_DECODE (cpu, "R%i = (%#x == %#x) = %i", num2, num3, num4, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -175,7 +177,7 @@ void step_once (SIM_CPU *cpu)
TRACE_DECODE (cpu, "R%i = (%#x > %#x) = %i", num2, num3, num4, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -258,7 +260,7 @@ void step_once (SIM_CPU *cpu)
32768, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -281,7 +283,7 @@ void step_once (SIM_CPU *cpu)
32768, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -302,7 +304,7 @@ void step_once (SIM_CPU *cpu)
TRACE_DECODE (cpu, "R%i = %#x %% %#x = %#x", num2, num3, num4, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -323,7 +325,7 @@ void step_once (SIM_CPU *cpu)
TRACE_DECODE (cpu, "R%i = %#x & %#x = %#x", num2, num3, num4, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -344,7 +346,7 @@ void step_once (SIM_CPU *cpu)
TRACE_DECODE (cpu, "R%i = %#x | %#x = %#x", num2, num3, num4, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 8;
}
@@ -363,7 +365,7 @@ void step_once (SIM_CPU *cpu)
TRACE_DECODE (cpu, "R%i = (~%#x) & 0x7fff = %#x", num2, num3, result);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 6;
}
@@ -385,7 +387,7 @@ void step_once (SIM_CPU *cpu)
result = sim_core_read_aligned_2 (cpu, pc, read_map, num3);
TRACE_REGISTER (cpu, "R%i = %#x", num2, result);
- cpu->regs[num2] = result;
+ example_cpu->regs[num2] = result;
pc += 6;
}
@@ -422,9 +424,9 @@ void step_once (SIM_CPU *cpu)
TRACE_INSN (cpu, "CALL %#x", num2);
TRACE_MEMORY (cpu, "pushing %#x onto stack", (pc + 4) >> 1);
- sim_core_write_aligned_2 (cpu, pc, write_map, cpu->sp, (pc + 4) >> 1);
- cpu->sp -= 2;
- TRACE_REGISTER (cpu, "SP = %#x", cpu->sp);
+ sim_core_write_aligned_2 (cpu, pc, write_map, example_cpu->sp, (pc + 4) >> 1);
+ example_cpu->sp -= 2;
+ TRACE_REGISTER (cpu, "SP = %#x", example_cpu->sp);
pc = num2;
TRACE_BRANCH (cpu, "CALL %#x", pc);
@@ -436,9 +438,9 @@ void step_once (SIM_CPU *cpu)
uint16_t result;
TRACE_INSN (cpu, "RET");
- cpu->sp += 2;
- TRACE_REGISTER (cpu, "SP = %#x", cpu->sp);
- result = sim_core_read_aligned_2 (cpu, pc, read_map, cpu->sp);
+ example_cpu->sp += 2;
+ TRACE_REGISTER (cpu, "SP = %#x", example_cpu->sp);
+ result = sim_core_read_aligned_2 (cpu, pc, read_map, example_cpu->sp);
TRACE_MEMORY (cpu, "popping %#x off of stack", result << 1);
pc = result << 1;
@@ -485,7 +487,7 @@ void step_once (SIM_CPU *cpu)
}
TRACE_REGISTER (cpu, "R%i = %#x", iw2 & 0xf, c);
- cpu->regs[iw2 & 0xf] = c;
+ example_cpu->regs[iw2 & 0xf] = c;
pc += 4;
}
@@ -507,14 +509,18 @@ void step_once (SIM_CPU *cpu)
static sim_cia
pc_get (sim_cpu *cpu)
{
- return cpu->pc;
+ struct example_sim_cpu *example_cpu = EXAMPLE_SIM_CPU (cpu);
+
+ return example_cpu->pc;
}
/* Set the program counter for this cpu to the new pc value. */
static void
pc_set (sim_cpu *cpu, sim_cia pc)
{
- cpu->pc = pc;
+ struct example_sim_cpu *example_cpu = EXAMPLE_SIM_CPU (cpu);
+
+ example_cpu->pc = pc;
}
/* Initialize the state for a single cpu. Usuaully this involves clearing all
@@ -522,10 +528,12 @@ pc_set (sim_cpu *cpu, sim_cia pc)
helper functions too. */
void initialize_cpu (SIM_DESC sd, SIM_CPU *cpu)
{
- memset (cpu->regs, 0, sizeof (cpu->regs));
- cpu->pc = 0;
+ struct example_sim_cpu *example_cpu = EXAMPLE_SIM_CPU (cpu);
+
+ memset (example_cpu->regs, 0, sizeof (example_cpu->regs));
+ example_cpu->pc = 0;
/* Make sure it's initialized outside of the 16-bit address space. */
- cpu->sp = 0x80000;
+ example_cpu->sp = 0x80000;
CPU_PC_FETCH (cpu) = pc_get;
CPU_PC_STORE (cpu) = pc_set;
diff --git a/sim/example-synacor/sim-main.h b/sim/example-synacor/sim-main.h
index e7e3ddc6d44d..11566d2c6b9f 100644
--- a/sim/example-synacor/sim-main.h
+++ b/sim/example-synacor/sim-main.h
@@ -21,21 +21,22 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
+#define SIM_HAVE_COMMON_SIM_CPU
+
#include "sim-basics.h"
#include "sim-base.h"
-struct _sim_cpu {
- /* ... simulator specific members ... */
+struct example_sim_cpu {
uint16_t regs[8];
sim_cia pc;
/* This isn't a real register, and the stack is not directly addressable,
so use memory outside of the 16-bit address space. */
uint32_t sp;
-
- sim_cpu_base base;
};
+#define EXAMPLE_SIM_CPU(cpu) ((struct example_sim_cpu *) CPU_ARCH_DATA (cpu))
+
extern void step_once (SIM_CPU *);
extern void initialize_cpu (SIM_DESC, SIM_CPU *);
--
2.38.1
next prev parent reply other threads:[~2022-11-05 13:33 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` Mike Frysinger [this message]
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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