From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 10/26] sim: v850: invert sim_cpu storage
Date: Sat, 5 Nov 2022 20:32:42 +0700 [thread overview]
Message-ID: <20221105133258.23409-11-vapier@gentoo.org> (raw)
In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org>
---
sim/v850/interp.c | 15 +++++++++------
sim/v850/sim-main.h | 24 ++++++++++++------------
sim/v850/v850.igen | 4 ++--
3 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index ab98571395bb..4fa900eef2b7 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -50,6 +50,8 @@ const char *interrupt_names[] =
static void
do_interrupt (SIM_DESC sd, void *data)
{
+ sim_cpu *cpu = STATE_CPU (sd, 0);
+ struct v850_sim_cpu *v850_cpu = V850_SIM_CPU (cpu);
const char **interrupt_name = (const char**)data;
enum interrupt_type inttype;
inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
@@ -74,9 +76,9 @@ do_interrupt (SIM_DESC sd, void *data)
ignores subsequent NMIs, so we don't need to count them.
Just keep re-scheduling a single NMI until it manages to
be delivered */
- if (STATE_CPU (sd, 0)->pending_nmi != NULL)
- sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
- STATE_CPU (sd, 0)->pending_nmi =
+ if (v850_cpu->pending_nmi != NULL)
+ sim_events_deschedule (sd, v850_cpu->pending_nmi);
+ v850_cpu->pending_nmi =
sim_events_schedule (sd, 1, do_interrupt, data);
return;
}
@@ -204,7 +206,8 @@ sim_open (SIM_OPEN_KIND kind,
cb->syscall_map = cb_v850_syscall_map;
/* The cpu data is kept in a separately allocated chunk of memory. */
- if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+ if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct v850_sim_cpu))
+ != SIM_RC_OK)
return 0;
/* for compatibility */
@@ -281,8 +284,8 @@ sim_open (SIM_OPEN_KIND kind,
case bfd_mach_v850e2:
case bfd_mach_v850e2v3:
case bfd_mach_v850e3v5:
- STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
- | PSW_CY | PSW_OV | PSW_S | PSW_Z);
+ V850_SIM_CPU (STATE_CPU (sd, 0))->psw_mask =
+ (PSW_NP | PSW_EP | PSW_ID | PSW_SAT | PSW_CY | PSW_OV | PSW_S | PSW_Z);
break;
}
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index ab7e47aa240a..970a1486ea12 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -1,6 +1,8 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
+#define SIM_HAVE_COMMON_SIM_CPU
+
/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
#define WITH_TARGET_WORD_MSB 31
@@ -32,16 +34,14 @@ typedef struct _v850_regs {
reg64_t vregs[32]; /* vector registers. */
} v850_regs;
-struct _sim_cpu
-{
- /* ... simulator specific members ... */
+struct v850_sim_cpu {
v850_regs reg;
reg_t psw_mask; /* only allow non-reserved bits to be set */
sim_event *pending_nmi;
- /* ... base type ... */
- sim_cpu_base base;
};
+#define V850_SIM_CPU(cpu) ((struct v850_sim_cpu *) CPU_ARCH_DATA (cpu))
+
/* For compatibility, until all functions converted to passing
SIM_DESC as an argument */
extern SIM_DESC simulator;
@@ -90,15 +90,15 @@ nia = PC
/* new */
-#define GR ((CPU)->reg.regs)
-#define SR ((CPU)->reg.sregs)
-#define VR ((CPU)->reg.vregs)
-#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
-#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
-#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
+#define GR (V850_SIM_CPU (CPU)->reg.regs)
+#define SR (V850_SIM_CPU (CPU)->reg.sregs)
+#define VR (V850_SIM_CPU (CPU)->reg.vregs)
+#define MPU0_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs)
+#define MPU1_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs)
+#define FPU_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs)
/* old */
-#define State (STATE_CPU (simulator, 0)->reg)
+#define State (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
#define PC (State.pc)
#define SP_REGNO 3
#define SP (State.regs[SP_REGNO])
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index eb32c0f5ec33..6bfabc08ea0a 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -370,7 +370,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
"ctret"
{
nia = (CTPC & ~1);
- PSW = (CTPSW & (CPU)->psw_mask);
+ PSW = (CTPSW & V850_SIM_CPU (CPU)->psw_mask);
TRACE_BRANCH1 (PSW);
}
@@ -954,7 +954,7 @@ regID,111111,RRRRR + selID,00000100000:IX:::ldsr
/* FIXME: For now we ignore the selID. */
if (idecode_issue == idecode_v850e3v5_issue && selID != 0)
{
- (CPU)->reg.selID_sregs[selID][regID] = sreg;
+ V850_SIM_CPU (CPU)->reg.selID_sregs[selID][regID] = sreg;
}
else if (( idecode_issue == idecode_v850e2_issue
|| idecode_issue == idecode_v850e3v5_issue
--
2.38.1
next prev parent reply other threads:[~2022-11-05 13:33 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` Mike Frysinger [this message]
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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