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From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 18/27] sim: cgen: prep for inverting sim_cpu storage
Date: Tue,  1 Nov 2022 20:56:49 +0545	[thread overview]
Message-ID: <20221101151158.24916-19-vapier@gentoo.org> (raw)
In-Reply-To: <20221101151158.24916-1-vapier@gentoo.org>

Some common cgen code changes to allow cgen ports to invert their
sim_cpu storage one-by-one.
---
 sim/common/cgen-cpu.h |  5 +++++
 sim/common/sim-cpu.h  | 10 ++++++++++
 2 files changed, 15 insertions(+)

diff --git a/sim/common/cgen-cpu.h b/sim/common/cgen-cpu.h
index 92161a84b875..d65e0dba0b20 100644
--- a/sim/common/cgen-cpu.h
+++ b/sim/common/cgen-cpu.h
@@ -20,6 +20,11 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 #ifndef CGEN_CPU_H
 #define CGEN_CPU_H
 
+#include "cgen-defs.h"
+#include "cgen-fpu.h"
+#include "cgen-par.h"
+#include "cgen-scache.h"
+
 /* Type of function that is ultimately called by sim_resume.  */
 typedef void (ENGINE_FN) (SIM_CPU *);
 
diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h
index 27dfde0bd09c..607b168a436a 100644
--- a/sim/common/sim-cpu.h
+++ b/sim/common/sim-cpu.h
@@ -28,6 +28,10 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 /* Type of function to return an insn name.  */
 typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int);
 
+#ifdef CGEN_ARCH
+# include "cgen-cpu.h"
+#endif
+
 /* Types for register access functions.
    These routines implement the sim_{fetch,store}_register interface.  */
 typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int);
@@ -127,6 +131,12 @@ struct _sim_cpu {
   /* All the common state.  */
   sim_cpu_base base;
 
+#ifdef CGEN_ARCH
+  /* Static parts of cgen.  */
+  CGEN_CPU cgen_cpu;
+#define CPU_CGEN_CPU(cpu) ((cpu)->cgen_cpu)
+#endif
+
   /* Pointer for sim target to store arbitrary cpu data.  Normally the
      target should define a struct and use it here.  */
   void *arch_data;
-- 
2.37.3


  parent reply	other threads:[~2022-11-01 16:27 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` Mike Frysinger [this message]
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32   ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32   ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32   ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32   ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32   ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger

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