From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 16/27] sim: pru: invert sim_cpu storage
Date: Tue, 1 Nov 2022 20:56:47 +0545 [thread overview]
Message-ID: <20221101151158.24916-17-vapier@gentoo.org> (raw)
In-Reply-To: <20221101151158.24916-1-vapier@gentoo.org>
---
sim/pru/interp.c | 28 ++++++++++++++++++++++++++--
sim/pru/pru.h | 2 +-
sim/pru/sim-main.h | 7 +++----
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/sim/pru/interp.c b/sim/pru/interp.c
index 4b7de4c79ce7..0a4579ac1689 100644
--- a/sim/pru/interp.c
+++ b/sim/pru/interp.c
@@ -130,6 +130,8 @@ write_regval (uint32_t val, uint32_t *reg, uint32_t regsel)
static uint32_t
imem_wordaddr_to_byteaddr (SIM_CPU *cpu, uint16_t wa)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
return (((uint32_t) wa << 2) & IMEM_ADDR_MASK) | PC_ADDR_SPACE_MARKER;
}
@@ -147,6 +149,7 @@ static inline void
pru_reg2dmem (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
int regn, int regb)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
/* GDB assumes unconditional access to all memories, so enable additional
checks only in standalone mode. */
bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
@@ -196,6 +199,7 @@ static inline void
pru_dmem2reg (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
int regn, int regb)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
/* GDB assumes unconditional access to all memories, so enable additional
checks only in standalone mode. */
bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
@@ -247,6 +251,7 @@ pru_dmem2reg (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
static void
set_initial_gprs (SIM_CPU *cpu)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
int i;
/* Set up machine just out of reset. */
@@ -325,6 +330,8 @@ static void
pru_sim_xin_mac (SIM_DESC sd, SIM_CPU *cpu, unsigned int rd_regn,
unsigned int rdb, unsigned int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
if (rd_regn < 25 || (rd_regn * 4 + rdb + length) > (27 + 1) * 4)
sim_io_error (sd, "XIN MAC: invalid transfer regn=%u.%u, length=%u\n",
rd_regn, rdb, length);
@@ -348,6 +355,8 @@ static void
pru_sim_xin (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
unsigned int rd_regn, unsigned int rdb, unsigned int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
if (wba == 0)
{
pru_sim_xin_mac (sd, cpu, rd_regn, rdb, length);
@@ -393,6 +402,7 @@ static void
pru_sim_xout_mac (SIM_DESC sd, SIM_CPU *cpu, unsigned int rd_regn,
unsigned int rdb, unsigned int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
const int modereg_accessed = (rd_regn == 25);
/* Multiple Accumulate. */
@@ -453,6 +463,8 @@ static void
pru_sim_xout (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
unsigned int rd_regn, unsigned int rdb, unsigned int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
if (wba == 0)
{
pru_sim_xout_mac (sd, cpu, rd_regn, rdb, length);
@@ -482,6 +494,8 @@ static void
pru_sim_xchg (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
unsigned int rd_regn, unsigned int rdb, unsigned int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
if (wba == XFRID_SCRATCH_BANK_0 || wba == XFRID_SCRATCH_BANK_1
|| wba == XFRID_SCRATCH_BANK_2 || wba == XFRID_SCRATCH_BANK_PEER)
{
@@ -508,6 +522,7 @@ pru_sim_xchg (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
static void
pru_sim_syscall (SIM_DESC sd, SIM_CPU *cpu)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
/* If someday TI confirms that the "reserved" HALT opcode fields
can be used for extra arguments, then maybe we can embed
the syscall number there. Until then, let's use R1. */
@@ -525,6 +540,7 @@ static void
sim_step_once (SIM_DESC sd)
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
const struct pru_opcode *op;
uint32_t inst;
uint32_t _RDVAL, OP2; /* intermediate values. */
@@ -635,16 +651,20 @@ sim_engine_run (SIM_DESC sd,
static sim_cia
pru_pc_get (sim_cpu *cpu)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
/* Present PC as byte address. */
- return imem_wordaddr_to_byteaddr (cpu, cpu->pru_cpu.pc);
+ return imem_wordaddr_to_byteaddr (cpu, pru_cpu->pc);
}
/* Implement callback for standard CPU_PC_STORE routine. */
static void
pru_pc_set (sim_cpu *cpu, sim_cia pc)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
/* PC given as byte address. */
- cpu->pru_cpu.pc = imem_byteaddr_to_wordaddr (cpu, pc);
+ pru_cpu->pc = imem_byteaddr_to_wordaddr (cpu, pc);
}
@@ -652,6 +672,8 @@ pru_pc_set (sim_cpu *cpu, sim_cia pc)
static int
pru_store_register (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
+
if (rn < NUM_REGS && rn >= 0)
{
if (length == 4)
@@ -675,6 +697,7 @@ pru_store_register (SIM_CPU *cpu, int rn, const unsigned char *memory, int lengt
static int
pru_fetch_register (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
long ival;
if (rn < NUM_REGS && rn >= 0)
@@ -831,6 +854,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd,
char * const *argv, char * const *env)
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
+ struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
host_callback *cb = STATE_CALLBACK (sd);
SIM_ADDR addr;
diff --git a/sim/pru/pru.h b/sim/pru/pru.h
index df61538491aa..f6b633b29bd0 100644
--- a/sim/pru/pru.h
+++ b/sim/pru/pru.h
@@ -41,7 +41,7 @@
#define XFRID_SCRATCH_BANK_PEER 14
#define XFRID_MAX 255
-#define CPU (cpu->pru_cpu)
+#define CPU (*pru_cpu)
#define PC (CPU.pc)
#define PC_byteaddr ((PC << 2) | PC_ADDR_SPACE_MARKER)
diff --git a/sim/pru/sim-main.h b/sim/pru/sim-main.h
index ce3453656380..a217eee576a1 100644
--- a/sim/pru/sim-main.h
+++ b/sim/pru/sim-main.h
@@ -19,6 +19,8 @@
#ifndef PRU_SIM_MAIN
#define PRU_SIM_MAIN
+#define SIM_HAVE_COMMON_SIM_CPU
+
#include <stdint.h>
#include <stddef.h>
#include "pru.h"
@@ -78,9 +80,6 @@ struct pru_regset
int insts;
};
-struct _sim_cpu {
- struct pru_regset pru_cpu;
- sim_cpu_base base;
-};
+#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
#endif /* PRU_SIM_MAIN */
--
2.37.3
next prev parent reply other threads:[~2022-11-01 16:26 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` Mike Frysinger [this message]
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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