From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu
Date: Tue, 1 Nov 2022 20:56:58 +0545 [thread overview]
Message-ID: <20221101151158.24916-28-vapier@gentoo.org> (raw)
In-Reply-To: <20221101151158.24916-1-vapier@gentoo.org>
Now that all ports have migrated to the new framework, drop support
for the old sim_cpu_base layout. There's a lot of noise here, so
it's been split into a dedicated commit.
---
sim/common/sim-cpu.h | 45 +++++++++++++++++++-------------------------
1 file changed, 19 insertions(+), 26 deletions(-)
diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h
index 51661996f6c6..7b22e8c33ca7 100644
--- a/sim/common/sim-cpu.h
+++ b/sim/common/sim-cpu.h
@@ -46,39 +46,38 @@ typedef void (PC_STORE_FN) (sim_cpu *, sim_cia);
/* Pseudo baseclass for each cpu. */
-typedef struct {
-
+struct _sim_cpu {
/* Backlink to main state struct. */
SIM_DESC state;
-#define CPU_STATE(cpu) ((cpu)->base.state)
+#define CPU_STATE(cpu) ((cpu)->state)
/* Processor index within the SD_DESC */
int index;
-#define CPU_INDEX(cpu) ((cpu)->base.index)
+#define CPU_INDEX(cpu) ((cpu)->index)
/* The name of the cpu. */
const char *name;
-#define CPU_NAME(cpu) ((cpu)->base.name)
+#define CPU_NAME(cpu) ((cpu)->name)
/* Options specific to this cpu. */
struct option_list *options;
-#define CPU_OPTIONS(cpu) ((cpu)->base.options)
+#define CPU_OPTIONS(cpu) ((cpu)->options)
/* Processor specific core data */
sim_cpu_core core;
-#define CPU_CORE(cpu) (& (cpu)->base.core)
+#define CPU_CORE(cpu) (& (cpu)->core)
/* Number of instructions (used to iterate over CPU_INSN_NAME). */
unsigned int max_insns;
-#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns)
+#define CPU_MAX_INSNS(cpu) ((cpu)->max_insns)
/* Function to return the name of an insn. */
CPU_INSN_NAME_FN *insn_name;
-#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name)
+#define CPU_INSN_NAME(cpu) ((cpu)->insn_name)
/* Trace data. See sim-trace.h. */
TRACE_DATA trace_data;
-#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
+#define CPU_TRACE_DATA(cpu) (& (cpu)->trace_data)
/* Maximum number of debuggable entities.
This debugging is not intended for normal use.
@@ -90,7 +89,7 @@ typedef struct {
/* Boolean array of specified debugging flags. */
char debug_flags[MAX_DEBUG_VALUES];
-#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
+#define CPU_DEBUG_FLAGS(cpu) ((cpu)->debug_flags)
/* Standard values. */
#define DEBUG_INSN_IDX 0
#define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
@@ -98,37 +97,31 @@ typedef struct {
/* Debugging output goes to this or stderr if NULL.
We can't store `stderr' here as stderr goes through a callback. */
FILE *debug_file;
-#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
+#define CPU_DEBUG_FILE(cpu) ((cpu)->debug_file)
/* Profile data. See sim-profile.h. */
PROFILE_DATA profile_data;
-#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
+#define CPU_PROFILE_DATA(cpu) (& (cpu)->profile_data)
/* Machine tables for this cpu. See sim-model.h. */
const SIM_MACH *mach;
-#define CPU_MACH(cpu) ((cpu)->base.mach)
+#define CPU_MACH(cpu) ((cpu)->mach)
/* The selected model. */
const SIM_MODEL *model;
-#define CPU_MODEL(cpu) ((cpu)->base.model)
+#define CPU_MODEL(cpu) ((cpu)->model)
/* Model data (profiling state, etc.). */
void *model_data;
-#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data)
+#define CPU_MODEL_DATA(cpu) ((cpu)->model_data)
/* Routines to fetch/store registers. */
CPUREG_FETCH_FN *reg_fetch;
-#define CPU_REG_FETCH(c) ((c)->base.reg_fetch)
+#define CPU_REG_FETCH(c) ((c)->reg_fetch)
CPUREG_STORE_FN *reg_store;
-#define CPU_REG_STORE(c) ((c)->base.reg_store)
+#define CPU_REG_STORE(c) ((c)->reg_store)
PC_FETCH_FN *pc_fetch;
-#define CPU_PC_FETCH(c) ((c)->base.pc_fetch)
+#define CPU_PC_FETCH(c) ((c)->pc_fetch)
PC_STORE_FN *pc_store;
-#define CPU_PC_STORE(c) ((c)->base.pc_store)
-
-} sim_cpu_base;
-
-struct _sim_cpu {
- /* All the common state. */
- sim_cpu_base base;
+#define CPU_PC_STORE(c) ((c)->pc_store)
#ifdef CGEN_ARCH
/* Static parts of cgen. */
--
2.37.3
next prev parent reply other threads:[~2022-11-01 16:27 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` Mike Frysinger [this message]
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32 ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32 ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32 ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32 ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 20/26] sim: frv: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32 ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32 ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
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