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From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 20/26] sim: frv: invert sim_cpu storage
Date: Sat,  5 Nov 2022 20:32:52 +0700	[thread overview]
Message-ID: <20221105133258.23409-21-vapier@gentoo.org> (raw)
In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org>

The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
---
 sim/frv/cpu.h      |  2 +-
 sim/frv/sim-if.c   |  2 +-
 sim/frv/sim-main.h | 37 ++++++++++++++++---------------------
 3 files changed, 18 insertions(+), 23 deletions(-)

diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h
index 902c6d4ae48d..d2409131b659 100644
--- a/sim/frv/cpu.h
+++ b/sim/frv/cpu.h
@@ -158,7 +158,7 @@ frvbf_h_spr_set_handler (current_cpu, (index), (x));\
 #define GET_H_CCCR(a1) CPU (h_cccr)[a1]
 #define SET_H_CCCR(a1, x) (CPU (h_cccr)[a1] = (x))
   } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+#define CPU_CGEN_HW(cpu) (& FRV_SIM_CPU (cpu)->cpu_data.hardware)
 } FRVBF_CPU_DATA;
 
 /* Virtual regs.  */
diff --git a/sim/frv/sim-if.c b/sim/frv/sim-if.c
index a7a3bb6a296b..f0487f5732ff 100644
--- a/sim/frv/sim-if.c
+++ b/sim/frv/sim-if.c
@@ -65,7 +65,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct frv_sim_cpu)) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/frv/sim-main.h b/sim/frv/sim-main.h
index 01ef0b680b90..3e40bd52ab38 100644
--- a/sim/frv/sim-main.h
+++ b/sim/frv/sim-main.h
@@ -22,6 +22,8 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 /* Main header for the frv.  */
 
+#define SIM_HAVE_COMMON_SIM_CPU
+
 /* This is a global setting.  Different cpu families can't mix-n-match -scache
    and -pbb.  However some cpu families may use -simple while others use
    one of -scache/-pbb. ???? */
@@ -51,15 +53,7 @@ void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
 extern void frv_sim_close (SIM_DESC sd, int quitting);
 #define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__)
 \f
-/* The _sim_cpu struct.  */
-
-struct _sim_cpu {
-  /* sim/common cpu base.  */
-  sim_cpu_base base;
-
-  /* Static parts of cgen.  */
-  CGEN_CPU cgen_cpu;
-
+struct frv_sim_cpu {
   /* CPU specific parts go here.
      Note that in files that don't need to access these pieces WANT_CPU_FOO
      won't be defined and thus these parts won't appear.  This is ok in the
@@ -72,40 +66,41 @@ struct _sim_cpu {
 
   /* Control information for registers */
   FRV_REGISTER_CONTROL register_control;
-#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
+#define CPU_REGISTER_CONTROL(cpu) (& FRV_SIM_CPU (cpu)->register_control)
 
   FRV_VLIW vliw;
-#define CPU_VLIW(cpu) (& (cpu)->vliw)
+#define CPU_VLIW(cpu) (& FRV_SIM_CPU (cpu)->vliw)
 
   FRV_CACHE insn_cache;
-#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
+#define CPU_INSN_CACHE(cpu) (& FRV_SIM_CPU (cpu)->insn_cache)
 
   FRV_CACHE data_cache;
-#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
+#define CPU_DATA_CACHE(cpu) (& FRV_SIM_CPU (cpu)->data_cache)
 
   FRV_PROFILE_STATE profile_state;
-#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
+#define CPU_PROFILE_STATE(cpu) (& FRV_SIM_CPU (cpu)->profile_state)
 
   int debug_state;
-#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
+#define CPU_DEBUG_STATE(cpu) (FRV_SIM_CPU (cpu)->debug_state)
 
   SI load_address;
-#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
+#define CPU_LOAD_ADDRESS(cpu) (FRV_SIM_CPU (cpu)->load_address)
 
   SI load_length;
-#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
+#define CPU_LOAD_LENGTH(cpu) (FRV_SIM_CPU (cpu)->load_length)
 
   SI load_flag;
-#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
-#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
+#define CPU_LOAD_SIGNED(cpu) (FRV_SIM_CPU (cpu)->load_flag)
+#define CPU_LOAD_LOCK(cpu) (FRV_SIM_CPU (cpu)->load_flag)
 
   SI store_flag;
-#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
+#define CPU_RSTR_INVALIDATE(cpu) (FRV_SIM_CPU (cpu)->store_flag)
 
   unsigned long elf_flags;
-#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
+#define CPU_ELF_FLAGS(cpu) (FRV_SIM_CPU (cpu)->elf_flags)
 #endif /* defined (WANT_CPU_FRVBF) */
 };
+#define FRV_SIM_CPU(cpu) ((struct frv_sim_cpu *) CPU_ARCH_DATA (cpu))
 \f
 /* Misc.  */
 
-- 
2.38.1


  parent reply	other threads:[~2022-11-05 13:33 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-01 15:11 [PATCH 00/27] sim: sim_cpu: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 01/27] " Mike Frysinger
2022-11-01 15:11 ` [PATCH 02/27] sim: bfin: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 03/27] sim: ft32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 04/27] sim: msp430: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 05/27] sim: moxie: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 06/27] sim: avr: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 07/27] sim: microblaze: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 08/27] sim: aarch64: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 09/27] sim: mcore: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 10/27] sim: v850: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 11/27] sim: mips: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 12/27] sim: m68hc11: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 13/27] sim: h8300: switch to cpu for state Mike Frysinger
2022-11-01 15:11 ` [PATCH 14/27] sim: h8300: invert sim_cpu storage Mike Frysinger
2022-11-01 15:11 ` [PATCH 15/27] sim: example-synacor: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 16/27] sim: pru: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 17/27] sim: riscv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 18/27] sim: cgen: prep for inverting " Mike Frysinger
2022-11-01 15:11 ` [PATCH 19/27] sim: bpf: invert " Mike Frysinger
2022-11-01 15:11 ` [PATCH 20/27] sim: cris: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 21/27] sim: frv: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 22/27] sim: iq2000: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 23/27] sim: lm32: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 24/27] sim: m32r: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 25/27] sim: or1k: " Mike Frysinger
2022-11-01 15:11 ` [PATCH 26/27] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-01 15:11 ` [PATCH 27/27] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger
2022-11-05 13:32 ` [PATCH v2 00/26] sim: sim_cpu: invert sim_cpu storage Mike Frysinger
2022-11-05 13:32   ` [PATCH 01/26] " Mike Frysinger
2022-11-05 13:32   ` [PATCH 02/26] sim: bfin: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 03/26] sim: ft32: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 04/26] sim: msp430: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 05/26] sim: moxie: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 06/26] sim: avr: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 07/26] sim: microblaze: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 08/26] sim: aarch64: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 09/26] sim: mcore: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 10/26] sim: v850: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 11/26] sim: mips: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 12/26] sim: m68hc11: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 13/26] sim: h8300: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 14/26] sim: example-synacor: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 15/26] sim: pru: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 16/26] sim: riscv: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 17/26] sim: cgen: prep for inverting " Mike Frysinger
2022-11-05 13:32   ` [PATCH 18/26] sim: bpf: invert " Mike Frysinger
2022-11-05 13:32   ` [PATCH 19/26] sim: cris: " Mike Frysinger
2022-11-05 13:32   ` Mike Frysinger [this message]
2022-11-05 13:32   ` [PATCH 21/26] sim: iq2000: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 22/26] sim: lm32: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 23/26] sim: m32r: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 24/26] sim: or1k: " Mike Frysinger
2022-11-05 13:32   ` [PATCH 25/26] sim: enable common sim_cpu usage everywhere Mike Frysinger
2022-11-05 13:32   ` [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Mike Frysinger

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