[PATCH 00/19] <sys/platform/x86.h>: Update CPUID features

[PATCH 00/19] <sys/platform/x86.h>: Update CPUID features

[H.J. Lu]

1. Rename x86_cpu_INDEX_7_ECX_1 to x86_cpu_INDEX_7_ECX_15 for the unused
bit 15 in ECX from CPUID with EAX == 0x7 and ECX == 0.
2. platform.texi: Move LAM after LAHF64_SAHF64 to sort x86 features.
3. Add more CPUID features documented in Intel Architecture Instruction
Set Extensions Programming Reference from:

https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html

H.J. Lu (19):
  <bits/platform/x86.h>: Rename to x86_cpu_INDEX_7_ECX_15
  platform.texi: Move LAM after LAHF64_SAHF64
  <sys/platform/x86.h>: Add LA57 support
  <sys/platform/x86.h>: Add BUS_LOCK_DETECT support
  <sys/platform/x86.h>: Add SGX-KEYS support
  <sys/platform/x86.h>: Add RTM_FORCE_ABORT support
  <sys/platform/x86.h>: Add LBR support
  <sys/platform/x86.h>: Add RAO-INT support
  <sys/platform/x86.h>: Add LASS support
  <sys/platform/x86.h>: Add CMPCCXADD support
  <sys/platform/x86.h>: Add ArchPerfmonExt support
  <sys/platform/x86.h>: Add WRMSRNS support
  <sys/platform/x86.h>: Add AMX-FP16 support
  <sys/platform/x86.h>: Add AVX-IFMA support
  <sys/platform/x86.h>: Add MSRLIST support
  <sys/platform/x86.h>: Add AVX-VNNI-INT8 support
  <sys/platform/x86.h>: Add AVX-NE-CONVERT support
  <sys/platform/x86.h>: Add AMX-COMPLEX support
  <sys/platform/x86.h>: Add PREFETCHI support

 manual/platform.texi               | 57 ++++++++++++++++++++++++++++--
 sysdeps/x86/bits/platform/x86.h    | 29 +++++++++++----
 sysdeps/x86/cpu-features.c         | 13 +++++++
 sysdeps/x86/include/cpu-features.h | 28 +++++++++++++++
 sysdeps/x86/tst-get-cpu-features.c | 25 +++++++++++++
 5 files changed, 144 insertions(+), 8 deletions(-)

-- 
2.39.2

[PATCH 01/19] <bits/platform/x86.h>: Rename to x86_cpu_INDEX_7_ECX_15

[H.J. Lu]

Rename x86_cpu_INDEX_7_ECX_1 to x86_cpu_INDEX_7_ECX_15 for the unused bit
15 in ECX from CPUID with EAX == 0x7 and ECX == 0.
---
 sysdeps/x86/bits/platform/x86.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 25a970b185..1ed24d7024 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -181,7 +181,7 @@ enum
   x86_cpu_AVX512_BITALG		= x86_cpu_index_7_ecx + 12,
   x86_cpu_INDEX_7_ECX_13	= x86_cpu_index_7_ecx + 13,
   x86_cpu_AVX512_VPOPCNTDQ	= x86_cpu_index_7_ecx + 14,
-  x86_cpu_INDEX_7_ECX_1		= x86_cpu_index_7_ecx + 15,
+  x86_cpu_INDEX_7_ECX_15	= x86_cpu_index_7_ecx + 15,
   x86_cpu_INDEX_7_ECX_16	= x86_cpu_index_7_ecx + 16,
 /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
    instructions in 64-bit mode.  */
-- 
2.39.2

[PATCH 02/19] platform.texi: Move LAM after LAHF64_SAHF64

[H.J. Lu]

Move LAM after LAHF64_SAHF64 to sort x86 features.
---
 manual/platform.texi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index d5fdc5bd05..c1cef570d2 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -391,15 +391,15 @@ the indirect branch predictor barrier (IBPB).
 @item
 @code{KL} -- AES Key Locker instructions.
 
-@item
-@code{LAM} -- Linear Address Masking.
-
 @item
 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
 
 @item
 @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
 
+@item
+@code{LAM} -- Linear Address Masking.
+
 @item
 @code{LM} -- Long mode.
 
-- 
2.39.2

[PATCH 03/19] <sys/platform/x86.h>: Add LA57 support

[H.J. Lu]

Add 57-bit linear addresses and five-level paging (LA57) support to
<sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 2 +-
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index c1cef570d2..9251b63e47 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB).
 @item
 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
 
+@item
+@code{LA57} -- 57-bit linear addresses and five-level paging.
+
 @item
 @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 1ed24d7024..c9189fa248 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -182,7 +182,7 @@ enum
   x86_cpu_INDEX_7_ECX_13	= x86_cpu_index_7_ecx + 13,
   x86_cpu_AVX512_VPOPCNTDQ	= x86_cpu_index_7_ecx + 14,
   x86_cpu_INDEX_7_ECX_15	= x86_cpu_index_7_ecx + 15,
-  x86_cpu_INDEX_7_ECX_16	= x86_cpu_index_7_ecx + 16,
+  x86_cpu_LA57			= x86_cpu_index_7_ecx + 16,
 /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
    instructions in 64-bit mode.  */
   x86_cpu_RDPID			= x86_cpu_index_7_ecx + 22,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 1954698df8..5f5cd3e448 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -144,6 +144,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI);
   CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG);
   CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ);
+  CHECK_CPU_FEATURE_PRESENT (LA57);
   CHECK_CPU_FEATURE_PRESENT (RDPID);
   CHECK_CPU_FEATURE_PRESENT (KL);
   CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
-- 
2.39.2

[PATCH 04/19] <sys/platform/x86.h>: Add BUS_LOCK_DETECT support

[H.J. Lu]

Add Bus lock debug exceptions (BUS_LOCK_DETECT) support to
<sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 2 +-
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index 9251b63e47..78ee39f650 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -276,6 +276,9 @@ extensions.
 @item
 @code{BMI2} -- BMI2 instructions.
 
+@item
+@code{BUS_LOCK_DETECT} -- Bus lock debug exceptions.
+
 @item
 @code{CLDEMOTE} -- CLDEMOTE instruction.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index c9189fa248..e25f1ac53c 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -187,7 +187,7 @@ enum
    instructions in 64-bit mode.  */
   x86_cpu_RDPID			= x86_cpu_index_7_ecx + 22,
   x86_cpu_KL			= x86_cpu_index_7_ecx + 23,
-  x86_cpu_INDEX_7_ECX_24	= x86_cpu_index_7_ecx + 24,
+  x86_cpu_BUS_LOCK_DETECT	= x86_cpu_index_7_ecx + 24,
   x86_cpu_CLDEMOTE		= x86_cpu_index_7_ecx + 25,
   x86_cpu_INDEX_7_ECX_26	= x86_cpu_index_7_ecx + 26,
   x86_cpu_MOVDIRI		= x86_cpu_index_7_ecx + 27,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 5f5cd3e448..dcb735ddd6 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -147,6 +147,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (LA57);
   CHECK_CPU_FEATURE_PRESENT (RDPID);
   CHECK_CPU_FEATURE_PRESENT (KL);
+  CHECK_CPU_FEATURE_PRESENT (BUS_LOCK_DETECT);
   CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
   CHECK_CPU_FEATURE_PRESENT (MOVDIRI);
   CHECK_CPU_FEATURE_PRESENT (MOVDIR64B);
-- 
2.39.2

[PATCH 05/19] <sys/platform/x86.h>: Add SGX-KEYS support

[H.J. Lu]

Add SGX-KEYS support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 2 +-
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index 78ee39f650..4453f6e1f4 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -551,6 +551,9 @@ capability.
 @item
 @code{SGX} -- Intel Software Guard Extensions.
 
+@item
+@code{SGX_KEYS} -- Attestation Services for SGX.
+
 @item
 @code{SGX_LC} -- SGX Launch Configuration.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index e25f1ac53c..ee5be8190f 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -201,7 +201,7 @@ enum
        + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
 
   x86_cpu_INDEX_7_EDX_0		= x86_cpu_index_7_edx,
-  x86_cpu_INDEX_7_EDX_1		= x86_cpu_index_7_edx + 1,
+  x86_cpu_SGX_KEYS		= x86_cpu_index_7_edx + 1,
   x86_cpu_AVX512_4VNNIW		= x86_cpu_index_7_edx + 2,
   x86_cpu_AVX512_4FMAPS		= x86_cpu_index_7_edx + 3,
   x86_cpu_FSRM			= x86_cpu_index_7_edx + 4,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index dcb735ddd6..1979da2174 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -154,6 +154,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (ENQCMD);
   CHECK_CPU_FEATURE_PRESENT (SGX_LC);
   CHECK_CPU_FEATURE_PRESENT (PKS);
+  CHECK_CPU_FEATURE_PRESENT (SGX_KEYS);
   CHECK_CPU_FEATURE_PRESENT (AVX512_4VNNIW);
   CHECK_CPU_FEATURE_PRESENT (AVX512_4FMAPS);
   CHECK_CPU_FEATURE_PRESENT (FSRM);
-- 
2.39.2

[PATCH 06/19] <sys/platform/x86.h>: Add RTM_FORCE_ABORT support

[H.J. Lu]

Add RTM_FORCE_ABORT support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 2 +-
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index 4453f6e1f4..2ab687cbba 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -539,6 +539,9 @@ capability.
 @item
 @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
 
+@item
+@code{RTM_FORCE_ABORT} -- TSX_FORCE_ABORT MSR.
+
 @item
 @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index ee5be8190f..6d9dd6dacf 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -213,7 +213,7 @@ enum
   x86_cpu_MD_CLEAR		= x86_cpu_index_7_edx + 10,
   x86_cpu_RTM_ALWAYS_ABORT	= x86_cpu_index_7_edx + 11,
   x86_cpu_INDEX_7_EDX_12	= x86_cpu_index_7_edx + 12,
-  x86_cpu_INDEX_7_EDX_13	= x86_cpu_index_7_edx + 13,
+  x86_cpu_RTM_FORCE_ABORT	= x86_cpu_index_7_edx + 13,
   x86_cpu_SERIALIZE		= x86_cpu_index_7_edx + 14,
   x86_cpu_HYBRID		= x86_cpu_index_7_edx + 15,
   x86_cpu_TSXLDTRK		= x86_cpu_index_7_edx + 16,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 1979da2174..8b7e70aee1 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -162,6 +162,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX512_VP2INTERSECT);
   CHECK_CPU_FEATURE_PRESENT (MD_CLEAR);
   CHECK_CPU_FEATURE_PRESENT (RTM_ALWAYS_ABORT);
+  CHECK_CPU_FEATURE_PRESENT (RTM_FORCE_ABORT);
   CHECK_CPU_FEATURE_PRESENT (SERIALIZE);
   CHECK_CPU_FEATURE_PRESENT (HYBRID);
   CHECK_CPU_FEATURE_PRESENT (TSXLDTRK);
-- 
2.39.2

[PATCH 07/19] <sys/platform/x86.h>: Add LBR support

[H.J. Lu]

Add architectural LBR support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 2 +-
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index 2ab687cbba..b72518ebd8 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -406,6 +406,9 @@ the indirect branch predictor barrier (IBPB).
 @item
 @code{LAM} -- Linear Address Masking.
 
+@item
+@code{LBR} -- Architectural LBR.
+
 @item
 @code{LM} -- Long mode.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 6d9dd6dacf..1040c2aed4 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -219,7 +219,7 @@ enum
   x86_cpu_TSXLDTRK		= x86_cpu_index_7_edx + 16,
   x86_cpu_INDEX_7_EDX_17	= x86_cpu_index_7_edx + 17,
   x86_cpu_PCONFIG		= x86_cpu_index_7_edx + 18,
-  x86_cpu_INDEX_7_EDX_19	= x86_cpu_index_7_edx + 19,
+  x86_cpu_LBR			= x86_cpu_index_7_edx + 19,
   x86_cpu_IBT			= x86_cpu_index_7_edx + 20,
   x86_cpu_INDEX_7_EDX_21	= x86_cpu_index_7_edx + 21,
   x86_cpu_AMX_BF16		= x86_cpu_index_7_edx + 22,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 8b7e70aee1..cfc8692392 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -166,6 +166,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (SERIALIZE);
   CHECK_CPU_FEATURE_PRESENT (HYBRID);
   CHECK_CPU_FEATURE_PRESENT (TSXLDTRK);
+  CHECK_CPU_FEATURE_PRESENT (LBR);
   CHECK_CPU_FEATURE_PRESENT (PCONFIG);
   CHECK_CPU_FEATURE_PRESENT (IBT);
   CHECK_CPU_FEATURE_PRESENT (AMX_BF16);
-- 
2.39.2

[PATCH 08/19] <sys/platform/x86.h>: Add RAO-INT support

[H.J. Lu]

Add RAO-INT support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 1 +
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 10 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index b72518ebd8..a6e33b1572 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -516,6 +516,9 @@ extended state management using XSAVE/XRSTOR.
 @item
 @code{PTWRITE} -- PTWRITE instruction.
 
+@item
+@code{RAO_INT} -- RAO-INT instructions.
+
 @item
 @code{RDPID} -- RDPID instruction.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 1040c2aed4..6fc3b69651 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -288,6 +288,7 @@ enum
     = (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
        + cpuid_register_index_eax * 8 * sizeof (unsigned int)),
 
+  x86_cpu_RAO_INT		= x86_cpu_index_7_ecx_1_eax + 3,
   x86_cpu_AVX_VNNI		= x86_cpu_index_7_ecx_1_eax + 4,
   x86_cpu_AVX512_BF16		= x86_cpu_index_7_ecx_1_eax + 5,
   x86_cpu_FZLRM			= x86_cpu_index_7_ecx_1_eax + 10,
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 95ad48b501..e591e55a88 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -99,6 +99,7 @@ update_active (struct cpu_features *cpu_features)
   CPU_FEATURE_SET_ACTIVE (cpu_features, TBM);
   CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP);
   CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD);
+  CPU_FEATURE_SET_ACTIVE (cpu_features, RAO_INT);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index fa91a23129..b946a88ad1 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -302,6 +302,7 @@ enum
 /* CPUID_INDEX_7_ECX_1.  */
 
 /* EAX.  */
+#define bit_cpu_RAO_INT		(1u << 3)
 #define bit_cpu_AVX_VNNI	(1u << 4)
 #define bit_cpu_AVX512_BF16	(1u << 5)
 #define bit_cpu_FZLRM		(1u << 10)
@@ -537,6 +538,7 @@ enum
 /* CPUID_INDEX_7_ECX_1.  */
 
 /* EAX.  */
+#define index_cpu_RAO_INT	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_VNNI	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX512_BF16	CPUID_INDEX_7_ECX_1
 #define index_cpu_FZLRM		CPUID_INDEX_7_ECX_1
@@ -772,6 +774,7 @@ enum
 /* CPUID_INDEX_7_ECX_1.  */
 
 /* EAX.  */
+#define reg_RAO_INT		eax
 #define reg_AVX_VNNI		eax
 #define reg_AVX512_BF16		eax
 #define reg_FZLRM		eax
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index cfc8692392..6a3f29db98 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -200,6 +200,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (XFD);
   CHECK_CPU_FEATURE_PRESENT (INVARIANT_TSC);
   CHECK_CPU_FEATURE_PRESENT (WBNOINVD);
+  CHECK_CPU_FEATURE_PRESENT (RAO_INT);
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
   CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
@@ -365,6 +366,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (XFD);
   CHECK_CPU_FEATURE_ACTIVE (INVARIANT_TSC);
   CHECK_CPU_FEATURE_ACTIVE (WBNOINVD);
+  CHECK_CPU_FEATURE_ACTIVE (RAO_INT);
   CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI);
   CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16);
   CHECK_CPU_FEATURE_ACTIVE (FZLRM);
-- 
2.39.2

[PATCH 09/19] <sys/platform/x86.h>: Add LASS support

[H.J. Lu]

Add Linear Address Space Separation (LASS) support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index a6e33b1572..be04194c88 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -406,6 +406,9 @@ the indirect branch predictor barrier (IBPB).
 @item
 @code{LAM} -- Linear Address Masking.
 
+@item
+@code{LASS} -- Linear Address Space Separation.
+
 @item
 @code{LBR} -- Architectural LBR.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 6fc3b69651..c9ee8fcf90 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -291,6 +291,7 @@ enum
   x86_cpu_RAO_INT		= x86_cpu_index_7_ecx_1_eax + 3,
   x86_cpu_AVX_VNNI		= x86_cpu_index_7_ecx_1_eax + 4,
   x86_cpu_AVX512_BF16		= x86_cpu_index_7_ecx_1_eax + 5,
+  x86_cpu_LASS			= x86_cpu_index_7_ecx_1_eax + 6,
   x86_cpu_FZLRM			= x86_cpu_index_7_ecx_1_eax + 10,
   x86_cpu_FSRS			= x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS			= x86_cpu_index_7_ecx_1_eax + 12,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 6a3f29db98..9da561a559 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -203,6 +203,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (RAO_INT);
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
   CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
+  CHECK_CPU_FEATURE_PRESENT (LASS);
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);
-- 
2.39.2

[PATCH 10/19] <sys/platform/x86.h>: Add CMPCCXADD support

[H.J. Lu]

Add CMPCCXADD support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 1 +
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 10 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index be04194c88..e4d2c00886 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -294,6 +294,9 @@ extensions.
 @item
 @code{CMOV} -- Conditional Move instructions.
 
+@item
+@code{CMPCCXADD} -- CMPccXADD instruction.
+
 @item
 @code{CMPXCHG16B} -- CMPXCHG16B instruction.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index c9ee8fcf90..0187964aba 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -292,6 +292,7 @@ enum
   x86_cpu_AVX_VNNI		= x86_cpu_index_7_ecx_1_eax + 4,
   x86_cpu_AVX512_BF16		= x86_cpu_index_7_ecx_1_eax + 5,
   x86_cpu_LASS			= x86_cpu_index_7_ecx_1_eax + 6,
+  x86_cpu_CMPCCXADD		= x86_cpu_index_7_ecx_1_eax + 7,
   x86_cpu_FZLRM			= x86_cpu_index_7_ecx_1_eax + 10,
   x86_cpu_FSRS			= x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS			= x86_cpu_index_7_ecx_1_eax + 12,
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index e591e55a88..da04ad0b00 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -100,6 +100,7 @@ update_active (struct cpu_features *cpu_features)
   CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP);
   CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD);
   CPU_FEATURE_SET_ACTIVE (cpu_features, RAO_INT);
+  CPU_FEATURE_SET_ACTIVE (cpu_features, CMPCCXADD);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index b946a88ad1..4e40fe0482 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -305,6 +305,7 @@ enum
 #define bit_cpu_RAO_INT		(1u << 3)
 #define bit_cpu_AVX_VNNI	(1u << 4)
 #define bit_cpu_AVX512_BF16	(1u << 5)
+#define bit_cpu_CMPCCXADD	(1u << 7)
 #define bit_cpu_FZLRM		(1u << 10)
 #define bit_cpu_FSRS		(1u << 11)
 #define bit_cpu_FSRCS		(1u << 12)
@@ -541,6 +542,7 @@ enum
 #define index_cpu_RAO_INT	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_VNNI	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX512_BF16	CPUID_INDEX_7_ECX_1
+#define index_cpu_CMPCCXADD	CPUID_INDEX_7_ECX_1
 #define index_cpu_FZLRM		CPUID_INDEX_7_ECX_1
 #define index_cpu_FSRS		CPUID_INDEX_7_ECX_1
 #define index_cpu_FSRCS		CPUID_INDEX_7_ECX_1
@@ -777,6 +779,7 @@ enum
 #define reg_RAO_INT		eax
 #define reg_AVX_VNNI		eax
 #define reg_AVX512_BF16		eax
+#define reg_CMPCCXADD		eax
 #define reg_FZLRM		eax
 #define reg_FSRS		eax
 #define reg_FSRCS		eax
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 9da561a559..d8bc92560f 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -204,6 +204,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
   CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
   CHECK_CPU_FEATURE_PRESENT (LASS);
+  CHECK_CPU_FEATURE_PRESENT (CMPCCXADD);
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);
@@ -370,6 +371,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (RAO_INT);
   CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI);
   CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16);
+  CHECK_CPU_FEATURE_ACTIVE (CMPCCXADD);
   CHECK_CPU_FEATURE_ACTIVE (FZLRM);
   CHECK_CPU_FEATURE_ACTIVE (FSRS);
   CHECK_CPU_FEATURE_ACTIVE (FSRCS);
-- 
2.39.2

[PATCH 11/19] <sys/platform/x86.h>: Add ArchPerfmonExt support

[H.J. Lu]

Add Architectural Performance Monitoring Extended Leaf (EAX = 23H)
support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 4 ++++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 6 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index e4d2c00886..ecee3a7b39 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -206,6 +206,10 @@ The supported processor features are:
 @item
 @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
 
+@item
+@code{ArchPerfmonExt} -- Architectural Performance Monitoring Extended
+Leaf (EAX = 23H).
+
 @item
 @code{AVX} -- The AVX instruction extensions.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 0187964aba..74b7f951e1 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -293,6 +293,7 @@ enum
   x86_cpu_AVX512_BF16		= x86_cpu_index_7_ecx_1_eax + 5,
   x86_cpu_LASS			= x86_cpu_index_7_ecx_1_eax + 6,
   x86_cpu_CMPCCXADD		= x86_cpu_index_7_ecx_1_eax + 7,
+  x86_cpu_ArchPerfmonExt	= x86_cpu_index_7_ecx_1_eax + 8,
   x86_cpu_FZLRM			= x86_cpu_index_7_ecx_1_eax + 10,
   x86_cpu_FSRS			= x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS			= x86_cpu_index_7_ecx_1_eax + 12,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index d8bc92560f..329d4aafb4 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -205,6 +205,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
   CHECK_CPU_FEATURE_PRESENT (LASS);
   CHECK_CPU_FEATURE_PRESENT (CMPCCXADD);
+  CHECK_CPU_FEATURE_PRESENT (ArchPerfmonExt);
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);
-- 
2.39.2

[PATCH 12/19] <sys/platform/x86.h>: Add WRMSRNS support

[H.J. Lu]

Add WRMSRNS support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 5 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index ecee3a7b39..af79f5eb4d 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -679,6 +679,9 @@ using a TSC deadline value.
 @item
 @code{WIDE_KL} -- AES wide Key Locker instructions.
 
+@item
+@code{WRMSRNS} -- WRMSRNS instruction.
+
 @item
 @code{X2APIC} -- x2APIC.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 74b7f951e1..2a15ad937a 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -297,6 +297,7 @@ enum
   x86_cpu_FZLRM			= x86_cpu_index_7_ecx_1_eax + 10,
   x86_cpu_FSRS			= x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS			= x86_cpu_index_7_ecx_1_eax + 12,
+  x86_cpu_WRMSRNS		= x86_cpu_index_7_ecx_1_eax + 19,
   x86_cpu_HRESET		= x86_cpu_index_7_ecx_1_eax + 22,
   x86_cpu_LAM			= x86_cpu_index_7_ecx_1_eax + 26,
 
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 329d4aafb4..9c436eaa64 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -209,6 +209,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);
+  CHECK_CPU_FEATURE_PRESENT (WRMSRNS);
   CHECK_CPU_FEATURE_PRESENT (HRESET);
   CHECK_CPU_FEATURE_PRESENT (LAM);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
-- 
2.39.2

[PATCH 13/19] <sys/platform/x86.h>: Add AMX-FP16 support

[H.J. Lu]

Add AMX-FP16 support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 2 ++
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 11 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index af79f5eb4d..7d4aa3d339 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -200,6 +200,9 @@ The supported processor features are:
 @item
 @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
 
+@item
+@code{AMX_FP16} -- Tile computational operations on FP16 numbers.
+
 @item
 @code{AMX_TILE} -- Tile architecture.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 2a15ad937a..2776c69b16 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -298,6 +298,7 @@ enum
   x86_cpu_FSRS			= x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS			= x86_cpu_index_7_ecx_1_eax + 12,
   x86_cpu_WRMSRNS		= x86_cpu_index_7_ecx_1_eax + 19,
+  x86_cpu_AMX_FP16		= x86_cpu_index_7_ecx_1_eax + 21,
   x86_cpu_HRESET		= x86_cpu_index_7_ecx_1_eax + 22,
   x86_cpu_LAM			= x86_cpu_index_7_ecx_1_eax + 26,
 
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index da04ad0b00..6c1b5efc5f 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -213,6 +213,8 @@ update_active (struct cpu_features *cpu_features)
 	  CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_TILE);
 	  /* Determine if AMX_INT8 is usable.  */
 	  CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_INT8);
+	  /* Determine if AMX_FP16 is usable.  */
+	  CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_FP16);
 	}
 
       /* These features are usable only when OSXSAVE is enabled.  */
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 4e40fe0482..07c841c1d4 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -309,6 +309,7 @@ enum
 #define bit_cpu_FZLRM		(1u << 10)
 #define bit_cpu_FSRS		(1u << 11)
 #define bit_cpu_FSRCS		(1u << 12)
+#define bit_cpu_AMX_FP16	(1u << 21)
 #define bit_cpu_HRESET		(1u << 22)
 #define bit_cpu_LAM		(1u << 26)
 
@@ -546,6 +547,7 @@ enum
 #define index_cpu_FZLRM		CPUID_INDEX_7_ECX_1
 #define index_cpu_FSRS		CPUID_INDEX_7_ECX_1
 #define index_cpu_FSRCS		CPUID_INDEX_7_ECX_1
+#define index_cpu_AMX_FP16	CPUID_INDEX_7_ECX_1
 #define index_cpu_HRESET	CPUID_INDEX_7_ECX_1
 #define index_cpu_LAM		CPUID_INDEX_7_ECX_1
 
@@ -783,6 +785,7 @@ enum
 #define reg_FZLRM		eax
 #define reg_FSRS		eax
 #define reg_FSRCS		eax
+#define reg_AMX_FP16		eax
 #define reg_HRESET		eax
 #define reg_LAM			eax
 
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 9c436eaa64..c0f222cb77 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -210,6 +210,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);
   CHECK_CPU_FEATURE_PRESENT (WRMSRNS);
+  CHECK_CPU_FEATURE_PRESENT (AMX_FP16);
   CHECK_CPU_FEATURE_PRESENT (HRESET);
   CHECK_CPU_FEATURE_PRESENT (LAM);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
@@ -377,6 +378,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (FZLRM);
   CHECK_CPU_FEATURE_ACTIVE (FSRS);
   CHECK_CPU_FEATURE_ACTIVE (FSRCS);
+  CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
-- 
2.39.2

[PATCH 14/19] <sys/platform/x86.h>: Add AVX-IFMA support

[H.J. Lu]

Add AVX-IFMA support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 2 ++
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 11 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index 7d4aa3d339..af75e5c413 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -219,6 +219,9 @@ Leaf (EAX = 23H).
 @item
 @code{AVX2} -- The AVX2 instruction extensions.
 
+@item
+@code{AVX_IFMA} -- The AVX-IFMA instruction extensions.
+
 @item
 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 2776c69b16..abc0116607 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -300,6 +300,7 @@ enum
   x86_cpu_WRMSRNS		= x86_cpu_index_7_ecx_1_eax + 19,
   x86_cpu_AMX_FP16		= x86_cpu_index_7_ecx_1_eax + 21,
   x86_cpu_HRESET		= x86_cpu_index_7_ecx_1_eax + 22,
+  x86_cpu_AVX_IFMA		= x86_cpu_index_7_ecx_1_eax + 23,
   x86_cpu_LAM			= x86_cpu_index_7_ecx_1_eax + 26,
 
   x86_cpu_index_19_ebx
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 6c1b5efc5f..06fae443a8 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -139,6 +139,8 @@ update_active (struct cpu_features *cpu_features)
 		  cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
 		    |= bit_arch_AVX_Fast_Unaligned_Load;
 		}
+	      /* Determine if AVX-IFMA is usable.  */
+	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_IFMA);
 	      /* Determine if AVX-VNNI is usable.  */
 	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI);
 	      /* Determine if FMA is usable.  */
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 07c841c1d4..1f4b6831f9 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -311,6 +311,7 @@ enum
 #define bit_cpu_FSRCS		(1u << 12)
 #define bit_cpu_AMX_FP16	(1u << 21)
 #define bit_cpu_HRESET		(1u << 22)
+#define bit_cpu_AVX_IFMA	(1u << 23)
 #define bit_cpu_LAM		(1u << 26)
 
 /* CPUID_INDEX_19.  */
@@ -549,6 +550,7 @@ enum
 #define index_cpu_FSRCS		CPUID_INDEX_7_ECX_1
 #define index_cpu_AMX_FP16	CPUID_INDEX_7_ECX_1
 #define index_cpu_HRESET	CPUID_INDEX_7_ECX_1
+#define index_cpu_AVX_IFMA	CPUID_INDEX_7_ECX_1
 #define index_cpu_LAM		CPUID_INDEX_7_ECX_1
 
 /* CPUID_INDEX_19.  */
@@ -787,6 +789,7 @@ enum
 #define reg_FSRCS		eax
 #define reg_AMX_FP16		eax
 #define reg_HRESET		eax
+#define reg_AVX_IFMA		eax
 #define reg_LAM			eax
 
 /* CPUID_INDEX_19.  */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index c0f222cb77..3a2d4671ec 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -212,6 +212,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (WRMSRNS);
   CHECK_CPU_FEATURE_PRESENT (AMX_FP16);
   CHECK_CPU_FEATURE_PRESENT (HRESET);
+  CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
   CHECK_CPU_FEATURE_PRESENT (LAM);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
@@ -379,6 +380,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (FSRS);
   CHECK_CPU_FEATURE_ACTIVE (FSRCS);
   CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
+  CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
-- 
2.39.2

[PATCH 15/19] <sys/platform/x86.h>: Add MSRLIST support

[H.J. Lu]

Add MSRLIST support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 4 ++++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 6 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index af75e5c413..bfccd024a5 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -464,6 +464,10 @@ the indirect branch predictor barrier (IBPB).
 @item
 @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
 
+@item
+@code{MSRLIST} -- RDMSRLIST/WRMSRLIST instructions and IA32_BARRIER
+MSR.
+
 @item
 @code{MTRR} -- Memory Type Range Registers.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index abc0116607..57973e9a6c 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -302,6 +302,7 @@ enum
   x86_cpu_HRESET		= x86_cpu_index_7_ecx_1_eax + 22,
   x86_cpu_AVX_IFMA		= x86_cpu_index_7_ecx_1_eax + 23,
   x86_cpu_LAM			= x86_cpu_index_7_ecx_1_eax + 26,
+  x86_cpu_MSRLIST		= x86_cpu_index_7_ecx_1_eax + 27,
 
   x86_cpu_index_19_ebx
     = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 3a2d4671ec..0c948c2b04 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -214,6 +214,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (HRESET);
   CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
   CHECK_CPU_FEATURE_PRESENT (LAM);
+  CHECK_CPU_FEATURE_PRESENT (MSRLIST);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
   CHECK_CPU_FEATURE_PRESENT (PTWRITE);
-- 
2.39.2

[PATCH 16/19] <sys/platform/x86.h>: Add AVX-VNNI-INT8 support

[H.J. Lu]

Add AVX-VNNI-INT8 support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 6 ++++++
 sysdeps/x86/cpu-features.c         | 2 ++
 sysdeps/x86/include/cpu-features.h | 7 +++++++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 20 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index bfccd024a5..873ea0a84a 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -225,6 +225,9 @@ Leaf (EAX = 23H).
 @item
 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
 
+@item
+@code{AVX_VNNI_INT8} -- The AVX-VNNI-INT8 instruction extensions.
+
 @item
 @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 57973e9a6c..7b239ef188 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -304,6 +304,12 @@ enum
   x86_cpu_LAM			= x86_cpu_index_7_ecx_1_eax + 26,
   x86_cpu_MSRLIST		= x86_cpu_index_7_ecx_1_eax + 27,
 
+  x86_cpu_index_7_ecx_1_edx
+    = (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
+       + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
+
+  x86_cpu_AVX_VNNI_INT8		= x86_cpu_index_7_ecx_1_edx + 4,
+
   x86_cpu_index_19_ebx
     = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
        + cpuid_register_index_ebx * 8 * sizeof (unsigned int)),
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 06fae443a8..f34f4884eb 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -143,6 +143,8 @@ update_active (struct cpu_features *cpu_features)
 	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_IFMA);
 	      /* Determine if AVX-VNNI is usable.  */
 	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI);
+	      /* Determine if AVX-VNNI-INT8 is usable.  */
+	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI_INT8);
 	      /* Determine if FMA is usable.  */
 	      CPU_FEATURE_SET_ACTIVE (cpu_features, FMA);
 	      /* Determine if VAES is usable.  */
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 1f4b6831f9..5e09c58d9c 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -314,6 +314,9 @@ enum
 #define bit_cpu_AVX_IFMA	(1u << 23)
 #define bit_cpu_LAM		(1u << 26)
 
+/* EDX.  */
+#define bit_cpu_AVX_VNNI_INT8	(1u << 4)
+
 /* CPUID_INDEX_19.  */
 
 /* EBX.  */
@@ -552,6 +555,7 @@ enum
 #define index_cpu_HRESET	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_IFMA	CPUID_INDEX_7_ECX_1
 #define index_cpu_LAM		CPUID_INDEX_7_ECX_1
+#define index_cpu_AVX_VNNI_INT8	CPUID_INDEX_7_ECX_1
 
 /* CPUID_INDEX_19.  */
 
@@ -792,6 +796,9 @@ enum
 #define reg_AVX_IFMA		eax
 #define reg_LAM			eax
 
+/* EDX.  */
+#define reg_AVX_VNNI_INT8	edx
+
 /* CPUID_INDEX_19.  */
 
 /* EBX.  */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 0c948c2b04..f0585cf330 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -215,6 +215,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
   CHECK_CPU_FEATURE_PRESENT (LAM);
   CHECK_CPU_FEATURE_PRESENT (MSRLIST);
+  CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
   CHECK_CPU_FEATURE_PRESENT (PTWRITE);
@@ -382,6 +383,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (FSRCS);
   CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
   CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
+  CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
-- 
2.39.2

[PATCH 17/19] <sys/platform/x86.h>: Add AVX-NE-CONVERT support

[H.J. Lu]

Add AVX-NE-CONVERT support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 2 ++
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 11 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index 873ea0a84a..1e120993d7 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -222,6 +222,9 @@ Leaf (EAX = 23H).
 @item
 @code{AVX_IFMA} -- The AVX-IFMA instruction extensions.
 
+@item
+@code{AVX_NE_CONVERT} -- The AVX-NE-CONVERT instruction extensions.
+
 @item
 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 7b239ef188..d8ba33bd42 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -309,6 +309,7 @@ enum
        + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
 
   x86_cpu_AVX_VNNI_INT8		= x86_cpu_index_7_ecx_1_edx + 4,
+  x86_cpu_AVX_NE_CONVERT	= x86_cpu_index_7_ecx_1_edx + 5,
 
   x86_cpu_index_19_ebx
     = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index f34f4884eb..dfd1b85dce 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -141,6 +141,8 @@ update_active (struct cpu_features *cpu_features)
 		}
 	      /* Determine if AVX-IFMA is usable.  */
 	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_IFMA);
+	      /* Determine if AVX-NE-CONVERT is usable.  */
+	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_NE_CONVERT);
 	      /* Determine if AVX-VNNI is usable.  */
 	      CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI);
 	      /* Determine if AVX-VNNI-INT8 is usable.  */
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 5e09c58d9c..673cf8ca92 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -316,6 +316,7 @@ enum
 
 /* EDX.  */
 #define bit_cpu_AVX_VNNI_INT8	(1u << 4)
+#define bit_cpu_AVX_NE_CONVERT	(1u << 5)
 
 /* CPUID_INDEX_19.  */
 
@@ -556,6 +557,7 @@ enum
 #define index_cpu_AVX_IFMA	CPUID_INDEX_7_ECX_1
 #define index_cpu_LAM		CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_VNNI_INT8	CPUID_INDEX_7_ECX_1
+#define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
 
 /* CPUID_INDEX_19.  */
 
@@ -798,6 +800,7 @@ enum
 
 /* EDX.  */
 #define reg_AVX_VNNI_INT8	edx
+#define reg_AVX_NE_CONVERT	edx
 
 /* CPUID_INDEX_19.  */
 
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index f0585cf330..bb1b67fd1c 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -216,6 +216,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (LAM);
   CHECK_CPU_FEATURE_PRESENT (MSRLIST);
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
+  CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
   CHECK_CPU_FEATURE_PRESENT (PTWRITE);
@@ -384,6 +385,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
   CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
   CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
+  CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
-- 
2.39.2

[PATCH 18/19] <sys/platform/x86.h>: Add AMX-COMPLEX support

[H.J. Lu]

Add AMX-COMPLEX support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 2 ++
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 11 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index 1e120993d7..e7448ffc1a 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -197,6 +197,9 @@ The supported processor features are:
 @item
 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
 
+@item
+@code{AMX_COMPLEX} -- Tile computational operations on complex FP16 numbers.
+
 @item
 @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index d8ba33bd42..96eb4c070d 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -310,6 +310,7 @@ enum
 
   x86_cpu_AVX_VNNI_INT8		= x86_cpu_index_7_ecx_1_edx + 4,
   x86_cpu_AVX_NE_CONVERT	= x86_cpu_index_7_ecx_1_edx + 5,
+  x86_cpu_AMX_COMPLEX		= x86_cpu_index_7_ecx_1_edx + 8,
 
   x86_cpu_index_19_ebx
     = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index dfd1b85dce..c2bea6a32d 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -221,6 +221,8 @@ update_active (struct cpu_features *cpu_features)
 	  CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_INT8);
 	  /* Determine if AMX_FP16 is usable.  */
 	  CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_FP16);
+	  /* Determine if AMX_COMPLEX is usable.  */
+	  CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_COMPLEX);
 	}
 
       /* These features are usable only when OSXSAVE is enabled.  */
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 673cf8ca92..f14c1078d5 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -317,6 +317,7 @@ enum
 /* EDX.  */
 #define bit_cpu_AVX_VNNI_INT8	(1u << 4)
 #define bit_cpu_AVX_NE_CONVERT	(1u << 5)
+#define bit_cpu_AMX_COMPLEX	(1u << 8)
 
 /* CPUID_INDEX_19.  */
 
@@ -558,6 +559,7 @@ enum
 #define index_cpu_LAM		CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_VNNI_INT8	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
+#define index_cpu_AMX_COMPLEX	CPUID_INDEX_7_ECX_1
 
 /* CPUID_INDEX_19.  */
 
@@ -801,6 +803,7 @@ enum
 /* EDX.  */
 #define reg_AVX_VNNI_INT8	edx
 #define reg_AVX_NE_CONVERT	edx
+#define reg_AMX_COMPLEX		edx
 
 /* CPUID_INDEX_19.  */
 
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index bb1b67fd1c..87fe27340f 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -217,6 +217,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (MSRLIST);
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
   CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
+  CHECK_CPU_FEATURE_PRESENT (AMX_COMPLEX);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
   CHECK_CPU_FEATURE_PRESENT (PTWRITE);
@@ -386,6 +387,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
   CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
   CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
+  CHECK_CPU_FEATURE_ACTIVE (AMX_COMPLEX);
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
-- 
2.39.2

[PATCH 19/19] <sys/platform/x86.h>: Add PREFETCHI support

[H.J. Lu]

Add PREFETCHI support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/bits/platform/x86.h    | 1 +
 sysdeps/x86/cpu-features.c         | 1 +
 sysdeps/x86/include/cpu-features.h | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 2 ++
 5 files changed, 10 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index e7448ffc1a..c6ed73cb97 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -533,6 +533,9 @@ extended state management using XSAVE/XRSTOR.
 @item
 @code{PREFETCHWT1} -- PREFETCHWT1 instruction.
 
+@item
+@code{PREFETCHI} -- PREFETCHIT0/1 instructions.
+
 @item
 @code{PSE} -- Page Size Extension.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 96eb4c070d..6555f9b91d 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -311,6 +311,7 @@ enum
   x86_cpu_AVX_VNNI_INT8		= x86_cpu_index_7_ecx_1_edx + 4,
   x86_cpu_AVX_NE_CONVERT	= x86_cpu_index_7_ecx_1_edx + 5,
   x86_cpu_AMX_COMPLEX		= x86_cpu_index_7_ecx_1_edx + 8,
+  x86_cpu_PREFETCHI		= x86_cpu_index_7_ecx_1_edx + 14,
 
   x86_cpu_index_19_ebx
     = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index c2bea6a32d..5bff8ec0b4 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -104,6 +104,7 @@ update_active (struct cpu_features *cpu_features)
   CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
+  CPU_FEATURE_SET_ACTIVE (cpu_features, PREFETCHI);
   CPU_FEATURE_SET_ACTIVE (cpu_features, PTWRITE);
 
   if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index f14c1078d5..40b8129d6a 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -318,6 +318,7 @@ enum
 #define bit_cpu_AVX_VNNI_INT8	(1u << 4)
 #define bit_cpu_AVX_NE_CONVERT	(1u << 5)
 #define bit_cpu_AMX_COMPLEX	(1u << 8)
+#define bit_cpu_PREFETCHI	(1u << 14)
 
 /* CPUID_INDEX_19.  */
 
@@ -560,6 +561,7 @@ enum
 #define index_cpu_AVX_VNNI_INT8	CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
 #define index_cpu_AMX_COMPLEX	CPUID_INDEX_7_ECX_1
+#define index_cpu_PREFETCHI	CPUID_INDEX_7_ECX_1
 
 /* CPUID_INDEX_19.  */
 
@@ -804,6 +806,7 @@ enum
 #define reg_AVX_VNNI_INT8	edx
 #define reg_AVX_NE_CONVERT	edx
 #define reg_AMX_COMPLEX		edx
+#define reg_PREFETCHI		edx
 
 /* CPUID_INDEX_19.  */
 
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 87fe27340f..1bd7e0be53 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -218,6 +218,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
   CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
   CHECK_CPU_FEATURE_PRESENT (AMX_COMPLEX);
+  CHECK_CPU_FEATURE_PRESENT (PREFETCHI);
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
   CHECK_CPU_FEATURE_PRESENT (PTWRITE);
@@ -388,6 +389,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
   CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
   CHECK_CPU_FEATURE_ACTIVE (AMX_COMPLEX);
+  CHECK_CPU_FEATURE_ACTIVE (PREFETCHI);
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
-- 
2.39.2

Re: [PATCH 03/19] <sys/platform/x86.h>: Add LA57 support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add 57-bit linear addresses and five-level paging (LA57) support to
> <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 2 +-
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index c1cef570d2..9251b63e47 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB).
>  @item
>  @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
>
> +@item
> +@code{LA57} -- 57-bit linear addresses and five-level paging.
> +
>  @item
>  @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 1ed24d7024..c9189fa248 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -182,7 +182,7 @@ enum
>    x86_cpu_INDEX_7_ECX_13       = x86_cpu_index_7_ecx + 13,
>    x86_cpu_AVX512_VPOPCNTDQ     = x86_cpu_index_7_ecx + 14,
>    x86_cpu_INDEX_7_ECX_15       = x86_cpu_index_7_ecx + 15,
> -  x86_cpu_INDEX_7_ECX_16       = x86_cpu_index_7_ecx + 16,
> +  x86_cpu_LA57                 = x86_cpu_index_7_ecx + 16,
>  /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
>     instructions in 64-bit mode.  */
>    x86_cpu_RDPID                        = x86_cpu_index_7_ecx + 22,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 1954698df8..5f5cd3e448 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -144,6 +144,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ);
> +  CHECK_CPU_FEATURE_PRESENT (LA57);
>    CHECK_CPU_FEATURE_PRESENT (RDPID);
>    CHECK_CPU_FEATURE_PRESENT (KL);
>    CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
> --
> 2.39.2
>
Rename:
`#define bit_cpu_INDEX_7_ECX_16`
in cpu-features.h?

Re: [PATCH 04/19] <sys/platform/x86.h>: Add BUS_LOCK_DETECT support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add Bus lock debug exceptions (BUS_LOCK_DETECT) support to
> <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 2 +-
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 9251b63e47..78ee39f650 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -276,6 +276,9 @@ extensions.
>  @item
>  @code{BMI2} -- BMI2 instructions.
>
> +@item
> +@code{BUS_LOCK_DETECT} -- Bus lock debug exceptions.
> +
>  @item
>  @code{CLDEMOTE} -- CLDEMOTE instruction.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index c9189fa248..e25f1ac53c 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -187,7 +187,7 @@ enum
>     instructions in 64-bit mode.  */
>    x86_cpu_RDPID                        = x86_cpu_index_7_ecx + 22,
>    x86_cpu_KL                   = x86_cpu_index_7_ecx + 23,
> -  x86_cpu_INDEX_7_ECX_24       = x86_cpu_index_7_ecx + 24,
> +  x86_cpu_BUS_LOCK_DETECT      = x86_cpu_index_7_ecx + 24,
>    x86_cpu_CLDEMOTE             = x86_cpu_index_7_ecx + 25,
>    x86_cpu_INDEX_7_ECX_26       = x86_cpu_index_7_ecx + 26,
>    x86_cpu_MOVDIRI              = x86_cpu_index_7_ecx + 27,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 5f5cd3e448..dcb735ddd6 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -147,6 +147,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (LA57);
>    CHECK_CPU_FEATURE_PRESENT (RDPID);
>    CHECK_CPU_FEATURE_PRESENT (KL);
> +  CHECK_CPU_FEATURE_PRESENT (BUS_LOCK_DETECT);
>    CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
>    CHECK_CPU_FEATURE_PRESENT (MOVDIRI);
>    CHECK_CPU_FEATURE_PRESENT (MOVDIR64B);
> --
> 2.39.2
>
Rename 'bit_cpu_INDEX_7_ECX_24' in cpu-features.h?

Re: [PATCH 05/19] <sys/platform/x86.h>: Add SGX-KEYS support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:25 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add SGX-KEYS support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 2 +-
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 78ee39f650..4453f6e1f4 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -551,6 +551,9 @@ capability.
>  @item
>  @code{SGX} -- Intel Software Guard Extensions.
>
> +@item
> +@code{SGX_KEYS} -- Attestation Services for SGX.
> +
>  @item
>  @code{SGX_LC} -- SGX Launch Configuration.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index e25f1ac53c..ee5be8190f 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -201,7 +201,7 @@ enum
>         + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
>
>    x86_cpu_INDEX_7_EDX_0                = x86_cpu_index_7_edx,
> -  x86_cpu_INDEX_7_EDX_1                = x86_cpu_index_7_edx + 1,
> +  x86_cpu_SGX_KEYS             = x86_cpu_index_7_edx + 1,
>    x86_cpu_AVX512_4VNNIW                = x86_cpu_index_7_edx + 2,
>    x86_cpu_AVX512_4FMAPS                = x86_cpu_index_7_edx + 3,
>    x86_cpu_FSRM                 = x86_cpu_index_7_edx + 4,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index dcb735ddd6..1979da2174 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -154,6 +154,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (ENQCMD);
>    CHECK_CPU_FEATURE_PRESENT (SGX_LC);
>    CHECK_CPU_FEATURE_PRESENT (PKS);
> +  CHECK_CPU_FEATURE_PRESENT (SGX_KEYS);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_4VNNIW);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_4FMAPS);
>    CHECK_CPU_FEATURE_PRESENT (FSRM);
> --
> 2.39.2
>

Rename 'bit_cpu_INDEX_7_EDX_1' in cpu-features.h?
Likewise for all other patches that don't rename the new index.

Re: [PATCH 03/19] <sys/platform/x86.h>: Add LA57 support

[H.J. Lu]

On Wed, Apr 5, 2023 at 11:20 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha
> <libc-alpha@sourceware.org> wrote:
> >
> > Add 57-bit linear addresses and five-level paging (LA57) support to
> > <sys/platform/x86.h>.
> > ---
> >  manual/platform.texi               | 3 +++
> >  sysdeps/x86/bits/platform/x86.h    | 2 +-
> >  sysdeps/x86/tst-get-cpu-features.c | 1 +
> >  3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/manual/platform.texi b/manual/platform.texi
> > index c1cef570d2..9251b63e47 100644
> > --- a/manual/platform.texi
> > +++ b/manual/platform.texi
> > @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB).
> >  @item
> >  @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
> >
> > +@item
> > +@code{LA57} -- 57-bit linear addresses and five-level paging.
> > +
> >  @item
> >  @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
> >
> > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> > index 1ed24d7024..c9189fa248 100644
> > --- a/sysdeps/x86/bits/platform/x86.h
> > +++ b/sysdeps/x86/bits/platform/x86.h
> > @@ -182,7 +182,7 @@ enum
> >    x86_cpu_INDEX_7_ECX_13       = x86_cpu_index_7_ecx + 13,
> >    x86_cpu_AVX512_VPOPCNTDQ     = x86_cpu_index_7_ecx + 14,
> >    x86_cpu_INDEX_7_ECX_15       = x86_cpu_index_7_ecx + 15,
> > -  x86_cpu_INDEX_7_ECX_16       = x86_cpu_index_7_ecx + 16,
> > +  x86_cpu_LA57                 = x86_cpu_index_7_ecx + 16,
> >  /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
> >     instructions in 64-bit mode.  */
> >    x86_cpu_RDPID                        = x86_cpu_index_7_ecx + 22,
> > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> > index 1954698df8..5f5cd3e448 100644
> > --- a/sysdeps/x86/tst-get-cpu-features.c
> > +++ b/sysdeps/x86/tst-get-cpu-features.c
> > @@ -144,6 +144,7 @@ do_test (void)
> >    CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI);
> >    CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG);
> >    CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ);
> > +  CHECK_CPU_FEATURE_PRESENT (LA57);
> >    CHECK_CPU_FEATURE_PRESENT (RDPID);
> >    CHECK_CPU_FEATURE_PRESENT (KL);
> >    CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
> > --
> > 2.39.2
> >
> Rename:
> `#define bit_cpu_INDEX_7_ECX_16`
> in cpu-features.h?

cpu-features.h is used internally in glibc.   Changes in
cpu-features.h are needed only if we need to use
CPU_FEATURE_SET_ACTIVE to mark a feature active.

-- 
H.J.

Re: [PATCH 05/19] <sys/platform/x86.h>: Add SGX-KEYS support

[H.J. Lu]

On Wed, Apr 5, 2023 at 11:21 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Wed, Apr 5, 2023 at 11:25 AM H.J. Lu via Libc-alpha
> <libc-alpha@sourceware.org> wrote:
> >
> > Add SGX-KEYS support to <sys/platform/x86.h>.
> > ---
> >  manual/platform.texi               | 3 +++
> >  sysdeps/x86/bits/platform/x86.h    | 2 +-
> >  sysdeps/x86/tst-get-cpu-features.c | 1 +
> >  3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/manual/platform.texi b/manual/platform.texi
> > index 78ee39f650..4453f6e1f4 100644
> > --- a/manual/platform.texi
> > +++ b/manual/platform.texi
> > @@ -551,6 +551,9 @@ capability.
> >  @item
> >  @code{SGX} -- Intel Software Guard Extensions.
> >
> > +@item
> > +@code{SGX_KEYS} -- Attestation Services for SGX.
> > +
> >  @item
> >  @code{SGX_LC} -- SGX Launch Configuration.
> >
> > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> > index e25f1ac53c..ee5be8190f 100644
> > --- a/sysdeps/x86/bits/platform/x86.h
> > +++ b/sysdeps/x86/bits/platform/x86.h
> > @@ -201,7 +201,7 @@ enum
> >         + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
> >
> >    x86_cpu_INDEX_7_EDX_0                = x86_cpu_index_7_edx,
> > -  x86_cpu_INDEX_7_EDX_1                = x86_cpu_index_7_edx + 1,
> > +  x86_cpu_SGX_KEYS             = x86_cpu_index_7_edx + 1,
> >    x86_cpu_AVX512_4VNNIW                = x86_cpu_index_7_edx + 2,
> >    x86_cpu_AVX512_4FMAPS                = x86_cpu_index_7_edx + 3,
> >    x86_cpu_FSRM                 = x86_cpu_index_7_edx + 4,
> > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> > index dcb735ddd6..1979da2174 100644
> > --- a/sysdeps/x86/tst-get-cpu-features.c
> > +++ b/sysdeps/x86/tst-get-cpu-features.c
> > @@ -154,6 +154,7 @@ do_test (void)
> >    CHECK_CPU_FEATURE_PRESENT (ENQCMD);
> >    CHECK_CPU_FEATURE_PRESENT (SGX_LC);
> >    CHECK_CPU_FEATURE_PRESENT (PKS);
> > +  CHECK_CPU_FEATURE_PRESENT (SGX_KEYS);
> >    CHECK_CPU_FEATURE_PRESENT (AVX512_4VNNIW);
> >    CHECK_CPU_FEATURE_PRESENT (AVX512_4FMAPS);
> >    CHECK_CPU_FEATURE_PRESENT (FSRM);
> > --
> > 2.39.2
> >
>
> Rename 'bit_cpu_INDEX_7_EDX_1' in cpu-features.h?
> Likewise for all other patches that don't rename the new index.

They can't be removed since they aren't used by
CPU_FEATURE_SET_ACTIVE.


-- 
H.J.

Re: [PATCH 01/19] <bits/platform/x86.h>: Rename to x86_cpu_INDEX_7_ECX_15

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:23 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Rename x86_cpu_INDEX_7_ECX_1 to x86_cpu_INDEX_7_ECX_15 for the unused bit
> 15 in ECX from CPUID with EAX == 0x7 and ECX == 0.
> ---
>  sysdeps/x86/bits/platform/x86.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 25a970b185..1ed24d7024 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -181,7 +181,7 @@ enum
>    x86_cpu_AVX512_BITALG                = x86_cpu_index_7_ecx + 12,
>    x86_cpu_INDEX_7_ECX_13       = x86_cpu_index_7_ecx + 13,
>    x86_cpu_AVX512_VPOPCNTDQ     = x86_cpu_index_7_ecx + 14,
> -  x86_cpu_INDEX_7_ECX_1                = x86_cpu_index_7_ecx + 15,
> +  x86_cpu_INDEX_7_ECX_15       = x86_cpu_index_7_ecx + 15,
>    x86_cpu_INDEX_7_ECX_16       = x86_cpu_index_7_ecx + 16,
>  /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
>     instructions in 64-bit mode.  */
> --
> 2.39.2
>
LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 02/19] platform.texi: Move LAM after LAHF64_SAHF64

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:21 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Move LAM after LAHF64_SAHF64 to sort x86 features.
> ---
>  manual/platform.texi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index d5fdc5bd05..c1cef570d2 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -391,15 +391,15 @@ the indirect branch predictor barrier (IBPB).
>  @item
>  @code{KL} -- AES Key Locker instructions.
>
> -@item
> -@code{LAM} -- Linear Address Masking.
> -
>  @item
>  @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
>
>  @item
>  @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
>
> +@item
> +@code{LAM} -- Linear Address Masking.
> +
>  @item
>  @code{LM} -- Long mode.
>
> --
> 2.39.2
>
LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 03/19] <sys/platform/x86.h>: Add LA57 support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 1:39 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Apr 5, 2023 at 11:20 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha
> > <libc-alpha@sourceware.org> wrote:
> > >
> > > Add 57-bit linear addresses and five-level paging (LA57) support to
> > > <sys/platform/x86.h>.
> > > ---
> > >  manual/platform.texi               | 3 +++
> > >  sysdeps/x86/bits/platform/x86.h    | 2 +-
> > >  sysdeps/x86/tst-get-cpu-features.c | 1 +
> > >  3 files changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/manual/platform.texi b/manual/platform.texi
> > > index c1cef570d2..9251b63e47 100644
> > > --- a/manual/platform.texi
> > > +++ b/manual/platform.texi
> > > @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB).
> > >  @item
> > >  @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
> > >
> > > +@item
> > > +@code{LA57} -- 57-bit linear addresses and five-level paging.
> > > +
> > >  @item
> > >  @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
> > >
> > > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> > > index 1ed24d7024..c9189fa248 100644
> > > --- a/sysdeps/x86/bits/platform/x86.h
> > > +++ b/sysdeps/x86/bits/platform/x86.h
> > > @@ -182,7 +182,7 @@ enum
> > >    x86_cpu_INDEX_7_ECX_13       = x86_cpu_index_7_ecx + 13,
> > >    x86_cpu_AVX512_VPOPCNTDQ     = x86_cpu_index_7_ecx + 14,
> > >    x86_cpu_INDEX_7_ECX_15       = x86_cpu_index_7_ecx + 15,
> > > -  x86_cpu_INDEX_7_ECX_16       = x86_cpu_index_7_ecx + 16,
> > > +  x86_cpu_LA57                 = x86_cpu_index_7_ecx + 16,
> > >  /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
> > >     instructions in 64-bit mode.  */
> > >    x86_cpu_RDPID                        = x86_cpu_index_7_ecx + 22,
> > > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> > > index 1954698df8..5f5cd3e448 100644
> > > --- a/sysdeps/x86/tst-get-cpu-features.c
> > > +++ b/sysdeps/x86/tst-get-cpu-features.c
> > > @@ -144,6 +144,7 @@ do_test (void)
> > >    CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI);
> > >    CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG);
> > >    CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ);
> > > +  CHECK_CPU_FEATURE_PRESENT (LA57);
> > >    CHECK_CPU_FEATURE_PRESENT (RDPID);
> > >    CHECK_CPU_FEATURE_PRESENT (KL);
> > >    CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
> > > --
> > > 2.39.2
> > >
> > Rename:
> > `#define bit_cpu_INDEX_7_ECX_16`
> > in cpu-features.h?
>
> cpu-features.h is used internally in glibc.   Changes in
> cpu-features.h are needed only if we need to use
> CPU_FEATURE_SET_ACTIVE to mark a feature active.
>
> --
> H.J.

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 04/19] <sys/platform/x86.h>: Add BUS_LOCK_DETECT support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 1:20 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha
> <libc-alpha@sourceware.org> wrote:
> >
> > Add Bus lock debug exceptions (BUS_LOCK_DETECT) support to
> > <sys/platform/x86.h>.
> > ---
> >  manual/platform.texi               | 3 +++
> >  sysdeps/x86/bits/platform/x86.h    | 2 +-
> >  sysdeps/x86/tst-get-cpu-features.c | 1 +
> >  3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/manual/platform.texi b/manual/platform.texi
> > index 9251b63e47..78ee39f650 100644
> > --- a/manual/platform.texi
> > +++ b/manual/platform.texi
> > @@ -276,6 +276,9 @@ extensions.
> >  @item
> >  @code{BMI2} -- BMI2 instructions.
> >
> > +@item
> > +@code{BUS_LOCK_DETECT} -- Bus lock debug exceptions.
> > +
> >  @item
> >  @code{CLDEMOTE} -- CLDEMOTE instruction.
> >
> > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> > index c9189fa248..e25f1ac53c 100644
> > --- a/sysdeps/x86/bits/platform/x86.h
> > +++ b/sysdeps/x86/bits/platform/x86.h
> > @@ -187,7 +187,7 @@ enum
> >     instructions in 64-bit mode.  */
> >    x86_cpu_RDPID                        = x86_cpu_index_7_ecx + 22,
> >    x86_cpu_KL                   = x86_cpu_index_7_ecx + 23,
> > -  x86_cpu_INDEX_7_ECX_24       = x86_cpu_index_7_ecx + 24,
> > +  x86_cpu_BUS_LOCK_DETECT      = x86_cpu_index_7_ecx + 24,
> >    x86_cpu_CLDEMOTE             = x86_cpu_index_7_ecx + 25,
> >    x86_cpu_INDEX_7_ECX_26       = x86_cpu_index_7_ecx + 26,
> >    x86_cpu_MOVDIRI              = x86_cpu_index_7_ecx + 27,
> > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> > index 5f5cd3e448..dcb735ddd6 100644
> > --- a/sysdeps/x86/tst-get-cpu-features.c
> > +++ b/sysdeps/x86/tst-get-cpu-features.c
> > @@ -147,6 +147,7 @@ do_test (void)
> >    CHECK_CPU_FEATURE_PRESENT (LA57);
> >    CHECK_CPU_FEATURE_PRESENT (RDPID);
> >    CHECK_CPU_FEATURE_PRESENT (KL);
> > +  CHECK_CPU_FEATURE_PRESENT (BUS_LOCK_DETECT);
> >    CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);
> >    CHECK_CPU_FEATURE_PRESENT (MOVDIRI);
> >    CHECK_CPU_FEATURE_PRESENT (MOVDIR64B);
> > --
> > 2.39.2
> >
> Rename 'bit_cpu_INDEX_7_ECX_24' in cpu-features.h?

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 05/19] <sys/platform/x86.h>: Add SGX-KEYS support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 1:40 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Apr 5, 2023 at 11:21 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > On Wed, Apr 5, 2023 at 11:25 AM H.J. Lu via Libc-alpha
> > <libc-alpha@sourceware.org> wrote:
> > >
> > > Add SGX-KEYS support to <sys/platform/x86.h>.
> > > ---
> > >  manual/platform.texi               | 3 +++
> > >  sysdeps/x86/bits/platform/x86.h    | 2 +-
> > >  sysdeps/x86/tst-get-cpu-features.c | 1 +
> > >  3 files changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/manual/platform.texi b/manual/platform.texi
> > > index 78ee39f650..4453f6e1f4 100644
> > > --- a/manual/platform.texi
> > > +++ b/manual/platform.texi
> > > @@ -551,6 +551,9 @@ capability.
> > >  @item
> > >  @code{SGX} -- Intel Software Guard Extensions.
> > >
> > > +@item
> > > +@code{SGX_KEYS} -- Attestation Services for SGX.
> > > +
> > >  @item
> > >  @code{SGX_LC} -- SGX Launch Configuration.
> > >
> > > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> > > index e25f1ac53c..ee5be8190f 100644
> > > --- a/sysdeps/x86/bits/platform/x86.h
> > > +++ b/sysdeps/x86/bits/platform/x86.h
> > > @@ -201,7 +201,7 @@ enum
> > >         + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
> > >
> > >    x86_cpu_INDEX_7_EDX_0                = x86_cpu_index_7_edx,
> > > -  x86_cpu_INDEX_7_EDX_1                = x86_cpu_index_7_edx + 1,
> > > +  x86_cpu_SGX_KEYS             = x86_cpu_index_7_edx + 1,
> > >    x86_cpu_AVX512_4VNNIW                = x86_cpu_index_7_edx + 2,
> > >    x86_cpu_AVX512_4FMAPS                = x86_cpu_index_7_edx + 3,
> > >    x86_cpu_FSRM                 = x86_cpu_index_7_edx + 4,
> > > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> > > index dcb735ddd6..1979da2174 100644
> > > --- a/sysdeps/x86/tst-get-cpu-features.c
> > > +++ b/sysdeps/x86/tst-get-cpu-features.c
> > > @@ -154,6 +154,7 @@ do_test (void)
> > >    CHECK_CPU_FEATURE_PRESENT (ENQCMD);
> > >    CHECK_CPU_FEATURE_PRESENT (SGX_LC);
> > >    CHECK_CPU_FEATURE_PRESENT (PKS);
> > > +  CHECK_CPU_FEATURE_PRESENT (SGX_KEYS);
> > >    CHECK_CPU_FEATURE_PRESENT (AVX512_4VNNIW);
> > >    CHECK_CPU_FEATURE_PRESENT (AVX512_4FMAPS);
> > >    CHECK_CPU_FEATURE_PRESENT (FSRM);
> > > --
> > > 2.39.2
> > >
> >
> > Rename 'bit_cpu_INDEX_7_EDX_1' in cpu-features.h?
> > Likewise for all other patches that don't rename the new index.
>
> They can't be removed since they aren't used by
> CPU_FEATURE_SET_ACTIVE.
>
>
> --
> H.J.

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 06/19] <sys/platform/x86.h>: Add RTM_FORCE_ABORT support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:23 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add RTM_FORCE_ABORT support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 2 +-
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 4453f6e1f4..2ab687cbba 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -539,6 +539,9 @@ capability.
>  @item
>  @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
>
> +@item
> +@code{RTM_FORCE_ABORT} -- TSX_FORCE_ABORT MSR.
> +
>  @item
>  @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index ee5be8190f..6d9dd6dacf 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -213,7 +213,7 @@ enum
>    x86_cpu_MD_CLEAR             = x86_cpu_index_7_edx + 10,
>    x86_cpu_RTM_ALWAYS_ABORT     = x86_cpu_index_7_edx + 11,
>    x86_cpu_INDEX_7_EDX_12       = x86_cpu_index_7_edx + 12,
> -  x86_cpu_INDEX_7_EDX_13       = x86_cpu_index_7_edx + 13,
> +  x86_cpu_RTM_FORCE_ABORT      = x86_cpu_index_7_edx + 13,
>    x86_cpu_SERIALIZE            = x86_cpu_index_7_edx + 14,
>    x86_cpu_HYBRID               = x86_cpu_index_7_edx + 15,
>    x86_cpu_TSXLDTRK             = x86_cpu_index_7_edx + 16,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 1979da2174..8b7e70aee1 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -162,6 +162,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AVX512_VP2INTERSECT);
>    CHECK_CPU_FEATURE_PRESENT (MD_CLEAR);
>    CHECK_CPU_FEATURE_PRESENT (RTM_ALWAYS_ABORT);
> +  CHECK_CPU_FEATURE_PRESENT (RTM_FORCE_ABORT);
>    CHECK_CPU_FEATURE_PRESENT (SERIALIZE);
>    CHECK_CPU_FEATURE_PRESENT (HYBRID);
>    CHECK_CPU_FEATURE_PRESENT (TSXLDTRK);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 07/19] <sys/platform/x86.h>: Add LBR support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:23 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add architectural LBR support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 2 +-
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 2ab687cbba..b72518ebd8 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -406,6 +406,9 @@ the indirect branch predictor barrier (IBPB).
>  @item
>  @code{LAM} -- Linear Address Masking.
>
> +@item
> +@code{LBR} -- Architectural LBR.
> +
>  @item
>  @code{LM} -- Long mode.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 6d9dd6dacf..1040c2aed4 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -219,7 +219,7 @@ enum
>    x86_cpu_TSXLDTRK             = x86_cpu_index_7_edx + 16,
>    x86_cpu_INDEX_7_EDX_17       = x86_cpu_index_7_edx + 17,
>    x86_cpu_PCONFIG              = x86_cpu_index_7_edx + 18,
> -  x86_cpu_INDEX_7_EDX_19       = x86_cpu_index_7_edx + 19,
> +  x86_cpu_LBR                  = x86_cpu_index_7_edx + 19,
>    x86_cpu_IBT                  = x86_cpu_index_7_edx + 20,
>    x86_cpu_INDEX_7_EDX_21       = x86_cpu_index_7_edx + 21,
>    x86_cpu_AMX_BF16             = x86_cpu_index_7_edx + 22,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 8b7e70aee1..cfc8692392 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -166,6 +166,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (SERIALIZE);
>    CHECK_CPU_FEATURE_PRESENT (HYBRID);
>    CHECK_CPU_FEATURE_PRESENT (TSXLDTRK);
> +  CHECK_CPU_FEATURE_PRESENT (LBR);
>    CHECK_CPU_FEATURE_PRESENT (PCONFIG);
>    CHECK_CPU_FEATURE_PRESENT (IBT);
>    CHECK_CPU_FEATURE_PRESENT (AMX_BF16);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 08/19] <sys/platform/x86.h>: Add RAO-INT support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:25 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add RAO-INT support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 1 +
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 10 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index b72518ebd8..a6e33b1572 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -516,6 +516,9 @@ extended state management using XSAVE/XRSTOR.
>  @item
>  @code{PTWRITE} -- PTWRITE instruction.
>
> +@item
> +@code{RAO_INT} -- RAO-INT instructions.
> +
>  @item
>  @code{RDPID} -- RDPID instruction.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 1040c2aed4..6fc3b69651 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -288,6 +288,7 @@ enum
>      = (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
>         + cpuid_register_index_eax * 8 * sizeof (unsigned int)),
>
> +  x86_cpu_RAO_INT              = x86_cpu_index_7_ecx_1_eax + 3,
>    x86_cpu_AVX_VNNI             = x86_cpu_index_7_ecx_1_eax + 4,
>    x86_cpu_AVX512_BF16          = x86_cpu_index_7_ecx_1_eax + 5,
>    x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index 95ad48b501..e591e55a88 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -99,6 +99,7 @@ update_active (struct cpu_features *cpu_features)
>    CPU_FEATURE_SET_ACTIVE (cpu_features, TBM);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD);
> +  CPU_FEATURE_SET_ACTIVE (cpu_features, RAO_INT);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index fa91a23129..b946a88ad1 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -302,6 +302,7 @@ enum
>  /* CPUID_INDEX_7_ECX_1.  */
>
>  /* EAX.  */
> +#define bit_cpu_RAO_INT                (1u << 3)
>  #define bit_cpu_AVX_VNNI       (1u << 4)
>  #define bit_cpu_AVX512_BF16    (1u << 5)
>  #define bit_cpu_FZLRM          (1u << 10)
> @@ -537,6 +538,7 @@ enum
>  /* CPUID_INDEX_7_ECX_1.  */
>
>  /* EAX.  */
> +#define index_cpu_RAO_INT      CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_VNNI     CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX512_BF16  CPUID_INDEX_7_ECX_1
>  #define index_cpu_FZLRM                CPUID_INDEX_7_ECX_1
> @@ -772,6 +774,7 @@ enum
>  /* CPUID_INDEX_7_ECX_1.  */
>
>  /* EAX.  */
> +#define reg_RAO_INT            eax
>  #define reg_AVX_VNNI           eax
>  #define reg_AVX512_BF16                eax
>  #define reg_FZLRM              eax
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index cfc8692392..6a3f29db98 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -200,6 +200,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (XFD);
>    CHECK_CPU_FEATURE_PRESENT (INVARIANT_TSC);
>    CHECK_CPU_FEATURE_PRESENT (WBNOINVD);
> +  CHECK_CPU_FEATURE_PRESENT (RAO_INT);
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
>    CHECK_CPU_FEATURE_PRESENT (FZLRM);
> @@ -365,6 +366,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (XFD);
>    CHECK_CPU_FEATURE_ACTIVE (INVARIANT_TSC);
>    CHECK_CPU_FEATURE_ACTIVE (WBNOINVD);
> +  CHECK_CPU_FEATURE_ACTIVE (RAO_INT);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI);
>    CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16);
>    CHECK_CPU_FEATURE_ACTIVE (FZLRM);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 09/19] <sys/platform/x86.h>: Add LASS support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:26 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add Linear Address Space Separation (LASS) support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index a6e33b1572..be04194c88 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -406,6 +406,9 @@ the indirect branch predictor barrier (IBPB).
>  @item
>  @code{LAM} -- Linear Address Masking.
>
> +@item
> +@code{LASS} -- Linear Address Space Separation.
> +
>  @item
>  @code{LBR} -- Architectural LBR.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 6fc3b69651..c9ee8fcf90 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -291,6 +291,7 @@ enum
>    x86_cpu_RAO_INT              = x86_cpu_index_7_ecx_1_eax + 3,
>    x86_cpu_AVX_VNNI             = x86_cpu_index_7_ecx_1_eax + 4,
>    x86_cpu_AVX512_BF16          = x86_cpu_index_7_ecx_1_eax + 5,
> +  x86_cpu_LASS                 = x86_cpu_index_7_ecx_1_eax + 6,
>    x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
>    x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
>    x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 6a3f29db98..9da561a559 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -203,6 +203,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (RAO_INT);
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
> +  CHECK_CPU_FEATURE_PRESENT (LASS);
>    CHECK_CPU_FEATURE_PRESENT (FZLRM);
>    CHECK_CPU_FEATURE_PRESENT (FSRS);
>    CHECK_CPU_FEATURE_PRESENT (FSRCS);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 10/19] <sys/platform/x86.h>: Add CMPCCXADD support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:25 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add CMPCCXADD support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 1 +
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 10 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index be04194c88..e4d2c00886 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -294,6 +294,9 @@ extensions.
>  @item
>  @code{CMOV} -- Conditional Move instructions.
>
> +@item
> +@code{CMPCCXADD} -- CMPccXADD instruction.
> +
>  @item
>  @code{CMPXCHG16B} -- CMPXCHG16B instruction.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index c9ee8fcf90..0187964aba 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -292,6 +292,7 @@ enum
>    x86_cpu_AVX_VNNI             = x86_cpu_index_7_ecx_1_eax + 4,
>    x86_cpu_AVX512_BF16          = x86_cpu_index_7_ecx_1_eax + 5,
>    x86_cpu_LASS                 = x86_cpu_index_7_ecx_1_eax + 6,
> +  x86_cpu_CMPCCXADD            = x86_cpu_index_7_ecx_1_eax + 7,
>    x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
>    x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
>    x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index e591e55a88..da04ad0b00 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -100,6 +100,7 @@ update_active (struct cpu_features *cpu_features)
>    CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, RAO_INT);
> +  CPU_FEATURE_SET_ACTIVE (cpu_features, CMPCCXADD);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index b946a88ad1..4e40fe0482 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -305,6 +305,7 @@ enum
>  #define bit_cpu_RAO_INT                (1u << 3)
>  #define bit_cpu_AVX_VNNI       (1u << 4)
>  #define bit_cpu_AVX512_BF16    (1u << 5)
> +#define bit_cpu_CMPCCXADD      (1u << 7)
>  #define bit_cpu_FZLRM          (1u << 10)
>  #define bit_cpu_FSRS           (1u << 11)
>  #define bit_cpu_FSRCS          (1u << 12)
> @@ -541,6 +542,7 @@ enum
>  #define index_cpu_RAO_INT      CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_VNNI     CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX512_BF16  CPUID_INDEX_7_ECX_1
> +#define index_cpu_CMPCCXADD    CPUID_INDEX_7_ECX_1
>  #define index_cpu_FZLRM                CPUID_INDEX_7_ECX_1
>  #define index_cpu_FSRS         CPUID_INDEX_7_ECX_1
>  #define index_cpu_FSRCS                CPUID_INDEX_7_ECX_1
> @@ -777,6 +779,7 @@ enum
>  #define reg_RAO_INT            eax
>  #define reg_AVX_VNNI           eax
>  #define reg_AVX512_BF16                eax
> +#define reg_CMPCCXADD          eax
>  #define reg_FZLRM              eax
>  #define reg_FSRS               eax
>  #define reg_FSRCS              eax
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 9da561a559..d8bc92560f 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -204,6 +204,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
>    CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
>    CHECK_CPU_FEATURE_PRESENT (LASS);
> +  CHECK_CPU_FEATURE_PRESENT (CMPCCXADD);
>    CHECK_CPU_FEATURE_PRESENT (FZLRM);
>    CHECK_CPU_FEATURE_PRESENT (FSRS);
>    CHECK_CPU_FEATURE_PRESENT (FSRCS);
> @@ -370,6 +371,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (RAO_INT);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI);
>    CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16);
> +  CHECK_CPU_FEATURE_ACTIVE (CMPCCXADD);
>    CHECK_CPU_FEATURE_ACTIVE (FZLRM);
>    CHECK_CPU_FEATURE_ACTIVE (FSRS);
>    CHECK_CPU_FEATURE_ACTIVE (FSRCS);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 11/19] <sys/platform/x86.h>: Add ArchPerfmonExt support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:26 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add Architectural Performance Monitoring Extended Leaf (EAX = 23H)
> support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 4 ++++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 6 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index e4d2c00886..ecee3a7b39 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -206,6 +206,10 @@ The supported processor features are:
>  @item
>  @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
>
> +@item
> +@code{ArchPerfmonExt} -- Architectural Performance Monitoring Extended
> +Leaf (EAX = 23H).
> +
>  @item
>  @code{AVX} -- The AVX instruction extensions.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 0187964aba..74b7f951e1 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -293,6 +293,7 @@ enum
>    x86_cpu_AVX512_BF16          = x86_cpu_index_7_ecx_1_eax + 5,
>    x86_cpu_LASS                 = x86_cpu_index_7_ecx_1_eax + 6,
>    x86_cpu_CMPCCXADD            = x86_cpu_index_7_ecx_1_eax + 7,
> +  x86_cpu_ArchPerfmonExt       = x86_cpu_index_7_ecx_1_eax + 8,
>    x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
>    x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
>    x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index d8bc92560f..329d4aafb4 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -205,6 +205,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
>    CHECK_CPU_FEATURE_PRESENT (LASS);
>    CHECK_CPU_FEATURE_PRESENT (CMPCCXADD);
> +  CHECK_CPU_FEATURE_PRESENT (ArchPerfmonExt);
>    CHECK_CPU_FEATURE_PRESENT (FZLRM);
>    CHECK_CPU_FEATURE_PRESENT (FSRS);
>    CHECK_CPU_FEATURE_PRESENT (FSRCS);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 12/19] <sys/platform/x86.h>: Add WRMSRNS support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:23 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add WRMSRNS support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 5 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index ecee3a7b39..af79f5eb4d 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -679,6 +679,9 @@ using a TSC deadline value.
>  @item
>  @code{WIDE_KL} -- AES wide Key Locker instructions.
>
> +@item
> +@code{WRMSRNS} -- WRMSRNS instruction.
> +
>  @item
>  @code{X2APIC} -- x2APIC.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 74b7f951e1..2a15ad937a 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -297,6 +297,7 @@ enum
>    x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
>    x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
>    x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
> +  x86_cpu_WRMSRNS              = x86_cpu_index_7_ecx_1_eax + 19,
>    x86_cpu_HRESET               = x86_cpu_index_7_ecx_1_eax + 22,
>    x86_cpu_LAM                  = x86_cpu_index_7_ecx_1_eax + 26,
>
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 329d4aafb4..9c436eaa64 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -209,6 +209,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (FZLRM);
>    CHECK_CPU_FEATURE_PRESENT (FSRS);
>    CHECK_CPU_FEATURE_PRESENT (FSRCS);
> +  CHECK_CPU_FEATURE_PRESENT (WRMSRNS);
>    CHECK_CPU_FEATURE_PRESENT (HRESET);
>    CHECK_CPU_FEATURE_PRESENT (LAM);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 13/19] <sys/platform/x86.h>: Add AMX-FP16 support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:28 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add AMX-FP16 support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 2 ++
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 11 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index af79f5eb4d..7d4aa3d339 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -200,6 +200,9 @@ The supported processor features are:
>  @item
>  @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
>
> +@item
> +@code{AMX_FP16} -- Tile computational operations on FP16 numbers.
> +
>  @item
>  @code{AMX_TILE} -- Tile architecture.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 2a15ad937a..2776c69b16 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -298,6 +298,7 @@ enum
>    x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
>    x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
>    x86_cpu_WRMSRNS              = x86_cpu_index_7_ecx_1_eax + 19,
> +  x86_cpu_AMX_FP16             = x86_cpu_index_7_ecx_1_eax + 21,
>    x86_cpu_HRESET               = x86_cpu_index_7_ecx_1_eax + 22,
>    x86_cpu_LAM                  = x86_cpu_index_7_ecx_1_eax + 26,
>
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index da04ad0b00..6c1b5efc5f 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -213,6 +213,8 @@ update_active (struct cpu_features *cpu_features)
>           CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_TILE);
>           /* Determine if AMX_INT8 is usable.  */
>           CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_INT8);
> +         /* Determine if AMX_FP16 is usable.  */
> +         CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_FP16);
>         }
>
>        /* These features are usable only when OSXSAVE is enabled.  */
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index 4e40fe0482..07c841c1d4 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -309,6 +309,7 @@ enum
>  #define bit_cpu_FZLRM          (1u << 10)
>  #define bit_cpu_FSRS           (1u << 11)
>  #define bit_cpu_FSRCS          (1u << 12)
> +#define bit_cpu_AMX_FP16       (1u << 21)
>  #define bit_cpu_HRESET         (1u << 22)
>  #define bit_cpu_LAM            (1u << 26)
>
> @@ -546,6 +547,7 @@ enum
>  #define index_cpu_FZLRM                CPUID_INDEX_7_ECX_1
>  #define index_cpu_FSRS         CPUID_INDEX_7_ECX_1
>  #define index_cpu_FSRCS                CPUID_INDEX_7_ECX_1
> +#define index_cpu_AMX_FP16     CPUID_INDEX_7_ECX_1
>  #define index_cpu_HRESET       CPUID_INDEX_7_ECX_1
>  #define index_cpu_LAM          CPUID_INDEX_7_ECX_1
>
> @@ -783,6 +785,7 @@ enum
>  #define reg_FZLRM              eax
>  #define reg_FSRS               eax
>  #define reg_FSRCS              eax
> +#define reg_AMX_FP16           eax
>  #define reg_HRESET             eax
>  #define reg_LAM                        eax
>
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 9c436eaa64..c0f222cb77 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -210,6 +210,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (FSRS);
>    CHECK_CPU_FEATURE_PRESENT (FSRCS);
>    CHECK_CPU_FEATURE_PRESENT (WRMSRNS);
> +  CHECK_CPU_FEATURE_PRESENT (AMX_FP16);
>    CHECK_CPU_FEATURE_PRESENT (HRESET);
>    CHECK_CPU_FEATURE_PRESENT (LAM);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
> @@ -377,6 +378,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (FZLRM);
>    CHECK_CPU_FEATURE_ACTIVE (FSRS);
>    CHECK_CPU_FEATURE_ACTIVE (FSRCS);
> +  CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 14/19] <sys/platform/x86.h>: Add AVX-IFMA support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:27 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add AVX-IFMA support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 2 ++
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 11 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 7d4aa3d339..af75e5c413 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -219,6 +219,9 @@ Leaf (EAX = 23H).
>  @item
>  @code{AVX2} -- The AVX2 instruction extensions.
>
> +@item
> +@code{AVX_IFMA} -- The AVX-IFMA instruction extensions.
> +
>  @item
>  @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 2776c69b16..abc0116607 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -300,6 +300,7 @@ enum
>    x86_cpu_WRMSRNS              = x86_cpu_index_7_ecx_1_eax + 19,
>    x86_cpu_AMX_FP16             = x86_cpu_index_7_ecx_1_eax + 21,
>    x86_cpu_HRESET               = x86_cpu_index_7_ecx_1_eax + 22,
> +  x86_cpu_AVX_IFMA             = x86_cpu_index_7_ecx_1_eax + 23,
>    x86_cpu_LAM                  = x86_cpu_index_7_ecx_1_eax + 26,
>
>    x86_cpu_index_19_ebx
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index 6c1b5efc5f..06fae443a8 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -139,6 +139,8 @@ update_active (struct cpu_features *cpu_features)
>                   cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
>                     |= bit_arch_AVX_Fast_Unaligned_Load;
>                 }
> +             /* Determine if AVX-IFMA is usable.  */
> +             CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_IFMA);
>               /* Determine if AVX-VNNI is usable.  */
>               CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI);
>               /* Determine if FMA is usable.  */
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index 07c841c1d4..1f4b6831f9 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -311,6 +311,7 @@ enum
>  #define bit_cpu_FSRCS          (1u << 12)
>  #define bit_cpu_AMX_FP16       (1u << 21)
>  #define bit_cpu_HRESET         (1u << 22)
> +#define bit_cpu_AVX_IFMA       (1u << 23)
>  #define bit_cpu_LAM            (1u << 26)
>
>  /* CPUID_INDEX_19.  */
> @@ -549,6 +550,7 @@ enum
>  #define index_cpu_FSRCS                CPUID_INDEX_7_ECX_1
>  #define index_cpu_AMX_FP16     CPUID_INDEX_7_ECX_1
>  #define index_cpu_HRESET       CPUID_INDEX_7_ECX_1
> +#define index_cpu_AVX_IFMA     CPUID_INDEX_7_ECX_1
>  #define index_cpu_LAM          CPUID_INDEX_7_ECX_1
>
>  /* CPUID_INDEX_19.  */
> @@ -787,6 +789,7 @@ enum
>  #define reg_FSRCS              eax
>  #define reg_AMX_FP16           eax
>  #define reg_HRESET             eax
> +#define reg_AVX_IFMA           eax
>  #define reg_LAM                        eax
>
>  /* CPUID_INDEX_19.  */
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index c0f222cb77..3a2d4671ec 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -212,6 +212,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (WRMSRNS);
>    CHECK_CPU_FEATURE_PRESENT (AMX_FP16);
>    CHECK_CPU_FEATURE_PRESENT (HRESET);
> +  CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
>    CHECK_CPU_FEATURE_PRESENT (LAM);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
> @@ -379,6 +380,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (FSRS);
>    CHECK_CPU_FEATURE_ACTIVE (FSRCS);
>    CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
> +  CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 15/19] <sys/platform/x86.h>: Add MSRLIST support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:26 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add MSRLIST support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 4 ++++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/tst-get-cpu-features.c | 1 +
>  3 files changed, 6 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index af75e5c413..bfccd024a5 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -464,6 +464,10 @@ the indirect branch predictor barrier (IBPB).
>  @item
>  @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
>
> +@item
> +@code{MSRLIST} -- RDMSRLIST/WRMSRLIST instructions and IA32_BARRIER
> +MSR.
> +
>  @item
>  @code{MTRR} -- Memory Type Range Registers.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index abc0116607..57973e9a6c 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -302,6 +302,7 @@ enum
>    x86_cpu_HRESET               = x86_cpu_index_7_ecx_1_eax + 22,
>    x86_cpu_AVX_IFMA             = x86_cpu_index_7_ecx_1_eax + 23,
>    x86_cpu_LAM                  = x86_cpu_index_7_ecx_1_eax + 26,
> +  x86_cpu_MSRLIST              = x86_cpu_index_7_ecx_1_eax + 27,
>
>    x86_cpu_index_19_ebx
>      = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 3a2d4671ec..0c948c2b04 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -214,6 +214,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (HRESET);
>    CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
>    CHECK_CPU_FEATURE_PRESENT (LAM);
> +  CHECK_CPU_FEATURE_PRESENT (MSRLIST);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
>    CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 16/19] <sys/platform/x86.h>: Add AVX-VNNI-INT8 support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:28 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add AVX-VNNI-INT8 support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 6 ++++++
>  sysdeps/x86/cpu-features.c         | 2 ++
>  sysdeps/x86/include/cpu-features.h | 7 +++++++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 20 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index bfccd024a5..873ea0a84a 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -225,6 +225,9 @@ Leaf (EAX = 23H).
>  @item
>  @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
>
> +@item
> +@code{AVX_VNNI_INT8} -- The AVX-VNNI-INT8 instruction extensions.
> +
>  @item
>  @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 57973e9a6c..7b239ef188 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -304,6 +304,12 @@ enum
>    x86_cpu_LAM                  = x86_cpu_index_7_ecx_1_eax + 26,
>    x86_cpu_MSRLIST              = x86_cpu_index_7_ecx_1_eax + 27,
>
> +  x86_cpu_index_7_ecx_1_edx
> +    = (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int)
> +       + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
> +
> +  x86_cpu_AVX_VNNI_INT8                = x86_cpu_index_7_ecx_1_edx + 4,
> +
>    x86_cpu_index_19_ebx
>      = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
>         + cpuid_register_index_ebx * 8 * sizeof (unsigned int)),
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index 06fae443a8..f34f4884eb 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -143,6 +143,8 @@ update_active (struct cpu_features *cpu_features)
>               CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_IFMA);
>               /* Determine if AVX-VNNI is usable.  */
>               CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI);
> +             /* Determine if AVX-VNNI-INT8 is usable.  */
> +             CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI_INT8);
>               /* Determine if FMA is usable.  */
>               CPU_FEATURE_SET_ACTIVE (cpu_features, FMA);
>               /* Determine if VAES is usable.  */
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index 1f4b6831f9..5e09c58d9c 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -314,6 +314,9 @@ enum
>  #define bit_cpu_AVX_IFMA       (1u << 23)
>  #define bit_cpu_LAM            (1u << 26)
>
> +/* EDX.  */
> +#define bit_cpu_AVX_VNNI_INT8  (1u << 4)
> +
>  /* CPUID_INDEX_19.  */
>
>  /* EBX.  */
> @@ -552,6 +555,7 @@ enum
>  #define index_cpu_HRESET       CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_IFMA     CPUID_INDEX_7_ECX_1
>  #define index_cpu_LAM          CPUID_INDEX_7_ECX_1
> +#define index_cpu_AVX_VNNI_INT8        CPUID_INDEX_7_ECX_1
>
>  /* CPUID_INDEX_19.  */
>
> @@ -792,6 +796,9 @@ enum
>  #define reg_AVX_IFMA           eax
>  #define reg_LAM                        eax
>
> +/* EDX.  */
> +#define reg_AVX_VNNI_INT8      edx
> +
>  /* CPUID_INDEX_19.  */
>
>  /* EBX.  */
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 0c948c2b04..f0585cf330 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -215,6 +215,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AVX_IFMA);
>    CHECK_CPU_FEATURE_PRESENT (LAM);
>    CHECK_CPU_FEATURE_PRESENT (MSRLIST);
> +  CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
>    CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> @@ -382,6 +383,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (FSRCS);
>    CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
> +  CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 17/19] <sys/platform/x86.h>: Add AVX-NE-CONVERT support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:27 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add AVX-NE-CONVERT support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 2 ++
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 11 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 873ea0a84a..1e120993d7 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -222,6 +222,9 @@ Leaf (EAX = 23H).
>  @item
>  @code{AVX_IFMA} -- The AVX-IFMA instruction extensions.
>
> +@item
> +@code{AVX_NE_CONVERT} -- The AVX-NE-CONVERT instruction extensions.
> +
>  @item
>  @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 7b239ef188..d8ba33bd42 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -309,6 +309,7 @@ enum
>         + cpuid_register_index_edx * 8 * sizeof (unsigned int)),
>
>    x86_cpu_AVX_VNNI_INT8                = x86_cpu_index_7_ecx_1_edx + 4,
> +  x86_cpu_AVX_NE_CONVERT       = x86_cpu_index_7_ecx_1_edx + 5,
>
>    x86_cpu_index_19_ebx
>      = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index f34f4884eb..dfd1b85dce 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -141,6 +141,8 @@ update_active (struct cpu_features *cpu_features)
>                 }
>               /* Determine if AVX-IFMA is usable.  */
>               CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_IFMA);
> +             /* Determine if AVX-NE-CONVERT is usable.  */
> +             CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_NE_CONVERT);
>               /* Determine if AVX-VNNI is usable.  */
>               CPU_FEATURE_SET_ACTIVE (cpu_features, AVX_VNNI);
>               /* Determine if AVX-VNNI-INT8 is usable.  */
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index 5e09c58d9c..673cf8ca92 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -316,6 +316,7 @@ enum
>
>  /* EDX.  */
>  #define bit_cpu_AVX_VNNI_INT8  (1u << 4)
> +#define bit_cpu_AVX_NE_CONVERT (1u << 5)
>
>  /* CPUID_INDEX_19.  */
>
> @@ -556,6 +557,7 @@ enum
>  #define index_cpu_AVX_IFMA     CPUID_INDEX_7_ECX_1
>  #define index_cpu_LAM          CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_VNNI_INT8        CPUID_INDEX_7_ECX_1
> +#define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
>
>  /* CPUID_INDEX_19.  */
>
> @@ -798,6 +800,7 @@ enum
>
>  /* EDX.  */
>  #define reg_AVX_VNNI_INT8      edx
> +#define reg_AVX_NE_CONVERT     edx
>
>  /* CPUID_INDEX_19.  */
>
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index f0585cf330..bb1b67fd1c 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -216,6 +216,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (LAM);
>    CHECK_CPU_FEATURE_PRESENT (MSRLIST);
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
> +  CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
>    CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> @@ -384,6 +385,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (AMX_FP16);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
> +  CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 18/19] <sys/platform/x86.h>: Add AMX-COMPLEX support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:27 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add AMX-COMPLEX support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 2 ++
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 11 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 1e120993d7..e7448ffc1a 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -197,6 +197,9 @@ The supported processor features are:
>  @item
>  @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
>
> +@item
> +@code{AMX_COMPLEX} -- Tile computational operations on complex FP16 numbers.
> +
>  @item
>  @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index d8ba33bd42..96eb4c070d 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -310,6 +310,7 @@ enum
>
>    x86_cpu_AVX_VNNI_INT8                = x86_cpu_index_7_ecx_1_edx + 4,
>    x86_cpu_AVX_NE_CONVERT       = x86_cpu_index_7_ecx_1_edx + 5,
> +  x86_cpu_AMX_COMPLEX          = x86_cpu_index_7_ecx_1_edx + 8,
>
>    x86_cpu_index_19_ebx
>      = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index dfd1b85dce..c2bea6a32d 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -221,6 +221,8 @@ update_active (struct cpu_features *cpu_features)
>           CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_INT8);
>           /* Determine if AMX_FP16 is usable.  */
>           CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_FP16);
> +         /* Determine if AMX_COMPLEX is usable.  */
> +         CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_COMPLEX);
>         }
>
>        /* These features are usable only when OSXSAVE is enabled.  */
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index 673cf8ca92..f14c1078d5 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -317,6 +317,7 @@ enum
>  /* EDX.  */
>  #define bit_cpu_AVX_VNNI_INT8  (1u << 4)
>  #define bit_cpu_AVX_NE_CONVERT (1u << 5)
> +#define bit_cpu_AMX_COMPLEX    (1u << 8)
>
>  /* CPUID_INDEX_19.  */
>
> @@ -558,6 +559,7 @@ enum
>  #define index_cpu_LAM          CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_VNNI_INT8        CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
> +#define index_cpu_AMX_COMPLEX  CPUID_INDEX_7_ECX_1
>
>  /* CPUID_INDEX_19.  */
>
> @@ -801,6 +803,7 @@ enum
>  /* EDX.  */
>  #define reg_AVX_VNNI_INT8      edx
>  #define reg_AVX_NE_CONVERT     edx
> +#define reg_AMX_COMPLEX                edx
>
>  /* CPUID_INDEX_19.  */
>
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index bb1b67fd1c..87fe27340f 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -217,6 +217,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (MSRLIST);
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
>    CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
> +  CHECK_CPU_FEATURE_PRESENT (AMX_COMPLEX);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
>    CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> @@ -386,6 +387,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (AVX_IFMA);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
> +  CHECK_CPU_FEATURE_ACTIVE (AMX_COMPLEX);
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>

Re: [PATCH 19/19] <sys/platform/x86.h>: Add PREFETCHI support

[Noah Goldstein]

On Wed, Apr 5, 2023 at 11:29 AM H.J. Lu via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Add PREFETCHI support to <sys/platform/x86.h>.
> ---
>  manual/platform.texi               | 3 +++
>  sysdeps/x86/bits/platform/x86.h    | 1 +
>  sysdeps/x86/cpu-features.c         | 1 +
>  sysdeps/x86/include/cpu-features.h | 3 +++
>  sysdeps/x86/tst-get-cpu-features.c | 2 ++
>  5 files changed, 10 insertions(+)
>
> diff --git a/manual/platform.texi b/manual/platform.texi
> index e7448ffc1a..c6ed73cb97 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -533,6 +533,9 @@ extended state management using XSAVE/XRSTOR.
>  @item
>  @code{PREFETCHWT1} -- PREFETCHWT1 instruction.
>
> +@item
> +@code{PREFETCHI} -- PREFETCHIT0/1 instructions.
> +
>  @item
>  @code{PSE} -- Page Size Extension.
>
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index 96eb4c070d..6555f9b91d 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -311,6 +311,7 @@ enum
>    x86_cpu_AVX_VNNI_INT8                = x86_cpu_index_7_ecx_1_edx + 4,
>    x86_cpu_AVX_NE_CONVERT       = x86_cpu_index_7_ecx_1_edx + 5,
>    x86_cpu_AMX_COMPLEX          = x86_cpu_index_7_ecx_1_edx + 8,
> +  x86_cpu_PREFETCHI            = x86_cpu_index_7_ecx_1_edx + 14,
>
>    x86_cpu_index_19_ebx
>      = (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index c2bea6a32d..5bff8ec0b4 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -104,6 +104,7 @@ update_active (struct cpu_features *cpu_features)
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
> +  CPU_FEATURE_SET_ACTIVE (cpu_features, PREFETCHI);
>    CPU_FEATURE_SET_ACTIVE (cpu_features, PTWRITE);
>
>    if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index f14c1078d5..40b8129d6a 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -318,6 +318,7 @@ enum
>  #define bit_cpu_AVX_VNNI_INT8  (1u << 4)
>  #define bit_cpu_AVX_NE_CONVERT (1u << 5)
>  #define bit_cpu_AMX_COMPLEX    (1u << 8)
> +#define bit_cpu_PREFETCHI      (1u << 14)
>
>  /* CPUID_INDEX_19.  */
>
> @@ -560,6 +561,7 @@ enum
>  #define index_cpu_AVX_VNNI_INT8        CPUID_INDEX_7_ECX_1
>  #define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
>  #define index_cpu_AMX_COMPLEX  CPUID_INDEX_7_ECX_1
> +#define index_cpu_PREFETCHI    CPUID_INDEX_7_ECX_1
>
>  /* CPUID_INDEX_19.  */
>
> @@ -804,6 +806,7 @@ enum
>  #define reg_AVX_VNNI_INT8      edx
>  #define reg_AVX_NE_CONVERT     edx
>  #define reg_AMX_COMPLEX                edx
> +#define reg_PREFETCHI          edx
>
>  /* CPUID_INDEX_19.  */
>
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index 87fe27340f..1bd7e0be53 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -218,6 +218,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AVX_VNNI_INT8);
>    CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
>    CHECK_CPU_FEATURE_PRESENT (AMX_COMPLEX);
> +  CHECK_CPU_FEATURE_PRESENT (PREFETCHI);
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
>    CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> @@ -388,6 +389,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI_INT8);
>    CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
>    CHECK_CPU_FEATURE_ACTIVE (AMX_COMPLEX);
> +  CHECK_CPU_FEATURE_ACTIVE (PREFETCHI);
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> --
> 2.39.2
>

LGTM
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>