[PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1)

[PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1)

[Tsukasa OI]

Hi all,

In my environment (Ubuntu 22.04.1 LTS + LLVM Clang 15.0.0/15.0.3), I have
finally managed to build almost default configuration of all-arch Binutils +
GDB ("--enable-targets=all") with Clang and -Werror enabled (by default).

This patchset is what I originally intended to split to multiple parts (in
fact, I submitted several patchsets that are originally a part of this) but
shared here (without splitting) to discuss and share information who wants
to build Binutils + GDB with Clang.

Related components (for review):
-   3 : cpu (Binutils)
    -   PATCH 04/40 (CRIS)
    -   PATCH 05/40 (CRIS)
    -   PATCH 11/40 (FR-V)
-   1 : gdb (GDB)
    -   PATCH 01/40 (same patch as below):
        <https://sourceware.org/pipermail/gdb-patches/2022-October/192802.html>
-  36 : sim (GDB)

Each resolves relatively small issue and/or non-issue (which Clang thinks
it is a problem).


[Credit]

PATCH 16/40 is entirely authored by Andrew Burgess (exactly the same as):
<https://sourceware.org/pipermail/gdb-patches/2022-October/192841.html>


[Limitation]

I only tested this on Linux (x86_64) and with almost default configuration.
My initial submission of gdb patch above confirmed broken on Mac due to
different C++ standard library (fixed though) but I cannot guarantee whether
this patchset is all we need.
So, non-default components and non-default configurations may still have
problems building with Clang (e.g. assemblers except x86).


[Shared Technique: Explicit cast to CGEN_INSN_TYPE]

-   PATCH 07/40: CRIS (in the process of regenerating all files)
-   PATCH 14/40: FR-V
-   PATCH 17/40: LatticeMicro32
-   PATCH 23/40: M32R
-   PATCH 38/40: BPF
-   PATCH 39/40: IQ2000
-   PATCH 40/40: OpenRISC 1000

In CGEN-generated instruction decoder, instruction type has CGEN_INSN_TYPE
values but some contain CGEN_INSN_VIRTUAL_TYPE values.  On such cases,
CGEN_INSN_VIRTUAL_TYPE values must be explicitly converted to CGEN_INSN_TYPE
to prevent build failure caused by Clang warnings ("-Wenum-conversion").

I'm going to upstream this change to CGEN but due to known regressions,
I did not regenerate those files using CGEN (except CRIS (PATCH 07/40),
which I used a WIP version of CGEN).


[Related Patches]

-   PATCH 02/40 is a prerequisite of PATCH 26/40.
    We don't want to declare getrusage ourself (as possible).
    If we have a known declaration of getrusage with known prototype,
    we no longer need to declare getrusage with indeterminate arguments
    (without prototype).  This is similar to getopt in Binutils.


Thanks,
Tsukasa




Andrew Burgess (1):
  sim/lm32: fix some missing function declaration warnings

Tsukasa OI (39):
  gdb/unittests: PR28413, suppress warnings generated by Gnulib
  sim: Check known getrusage declaration existence
  sim/aarch64: Remove unused functions
  cpu/cris: Initialize some variables on CRIS CPU
  cpu/cris: Add u-stall virtual unit to CRIS v32
  sim/cris: Move declarations of f_specific_init
  sim/cris: Regenerate with CGEN
  sim/erc32: Insert void parameter
  sim/erc32: Use int32_t as event callback argument
  sim/erc32: Use int32_t as IRQ callback argument
  cpu/frv: Initialize some variables
  sim/frv: Initialize nesr variable
  sim/frv: Initialize some variables
  sim/frv: Add explicit casts
  sim/h8300: Add "+ 0x0" to avoid self-assignments
  sim/lm32: Add explicit casts
  sim/m32c: Stop using middle dot
  sim/m32r: Initialize "list" variable
  sim/m32r: Prepare required functions
  sim/m32r: Declare all required functions
  sim/m32r: Fixes to Linux emulator
  sim/m32r: Add explicit casts
  sim/mips: Fix enum type-related issues on cp1.c
  sim/mn10300: Add an explicit cast
  sim/ppc: Remove getrusage declarations if possible
  sim/ppc: Add extra parenthesis to avoid ambiguity
  sim/ppc: Initialize stat type buffer
  sim/ppc: Fix indentation on generated code
  sim/ppc: Use TRACE with initialized entry_point
  sim/ppc: Initialize help variables
  sim/ppc: Add an explicit cast
  sim/ppc: Initialize reg and control_nr
  sim/rx: Mark unused function
  sim/sh: Initialize some variables
  sim/sh: Use fabs instead of abs
  sim/sh: Remove redundant function declaration
  sim/bpf: Add explicit casts
  sim/iq2000: Add explicit casts
  sim/or1k: Add explicit casts

 cpu/cris.cpu                          |  4 ++++
 cpu/frv.cpu                           |  3 +++
 gdb/unittests/string_view-selftests.c |  7 ++++++
 sim/aarch64/simulator.c               | 16 --------------
 sim/bpf/decode-be.c                   | 14 ++++++------
 sim/bpf/decode-le.c                   | 14 ++++++------
 sim/config.h.in                       |  4 ++++
 sim/configure                         | 32 +++++++++++++++++++++++++++
 sim/configure.ac                      | 10 +++++++++
 sim/cris/arch.c                       |  5 +++--
 sim/cris/arch.h                       | 21 +++++++++++++-----
 sim/cris/cpuall.h                     |  5 +++--
 sim/cris/cpuv10.c                     |  6 +++--
 sim/cris/cpuv10.h                     |  5 +++--
 sim/cris/cpuv32.c                     |  6 +++--
 sim/cris/cpuv32.h                     |  5 +++--
 sim/cris/cris-tmpl.c                  |  2 ++
 sim/cris/decodev10.c                  | 21 +++++++++---------
 sim/cris/decodev10.h                  |  6 ++---
 sim/cris/decodev32.c                  | 21 +++++++++---------
 sim/cris/decodev32.h                  |  8 +++----
 sim/cris/modelv10.c                   |  5 +++--
 sim/cris/modelv32.c                   |  5 +++--
 sim/cris/semcrisv10f-switch.c         | 20 +++++++++++------
 sim/cris/semcrisv32f-switch.c         | 20 +++++++++++------
 sim/erc32/erc32.c                     | 28 +++++++++++------------
 sim/erc32/func.c                      | 14 ++++++------
 sim/erc32/sis.h                       |  8 +++----
 sim/frv/decode.c                      | 14 ++++++------
 sim/frv/sem.c                         |  4 ++++
 sim/frv/traps.c                       |  2 +-
 sim/h8300/compile.c                   |  4 ++--
 sim/iq2000/decode.c                   | 14 ++++++------
 sim/lm32/Makefile.in                  |  3 ---
 sim/lm32/cpu.h                        | 11 +++++++++
 sim/lm32/decode.c                     | 14 ++++++------
 sim/lm32/dv-lm32cpu.c                 |  3 +++
 sim/lm32/user.c                       |  3 +++
 sim/m32c/mem.c                        |  2 +-
 sim/m32r/decode.c                     | 14 ++++++------
 sim/m32r/decode2.c                    | 14 ++++++------
 sim/m32r/decodex.c                    | 14 ++++++------
 sim/m32r/m32r-sim.h                   | 24 +++++++++++++++-----
 sim/m32r/m32r2.c                      |  5 +++++
 sim/m32r/m32rx.c                      |  5 +++++
 sim/m32r/sim-if.c                     |  4 ++++
 sim/m32r/traps.c                      | 28 +++++++++++++++++++++--
 sim/mips/cp1.c                        |  8 +++----
 sim/mn10300/op_utils.c                |  5 +++--
 sim/or1k/decode.c                     | 14 ++++++------
 sim/ppc/altivec.igen                  |  2 +-
 sim/ppc/emul_netbsd.c                 |  4 +++-
 sim/ppc/emul_unix.c                   |  2 ++
 sim/ppc/hw_ide.c                      |  8 +++----
 sim/ppc/hw_phb.c                      |  2 +-
 sim/ppc/hw_sem.c                      |  4 ++--
 sim/ppc/igen.c                        |  2 +-
 sim/ppc/mon.c                         |  2 ++
 sim/ppc/sim_calls.c                   |  4 ++--
 sim/rx/rx.c                           |  2 +-
 sim/sh/gencode.c                      |  4 ++--
 sim/sh/interp.c                       |  4 +---
 62 files changed, 358 insertions(+), 206 deletions(-)


base-commit: 837e225ba1992f9745e5bbbd5e8443243a7f475f
-- 
2.34.1

[PATCH 01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib

[Tsukasa OI]

Gnulib generates a warning if the system version of certain functions
are used (to redirect the developer to use Gnulib version).  It caused a
compiler error when...

-   Compiled with Clang
-   -Werror is specified (by default)
-   C++ standard used by Clang is before C++17 (by default as of 15.0.0)
    when this unit test is activated.

This issue is raised as PR28413.

However, previous proposal to fix this issue (a "fix" to Gnulib):
<https://lists.gnu.org/archive/html/bug-gnulib/2021-10/msg00003.html>
was rejected because it ruins the intent of Gnulib warnings.

So, we need a Binutils/GDB-side solution.

This commit tries to address this issue on the GDB side.  We have
"include/diagnostics.h" to disable certain warnings only when necessary.

This commit suppresses the Gnulib warnings by surrounding entire #include
block with DIAGNOSTIC_IGNORE_USER_DEFINED_WARNINGS to disable Gnulib-
generated warnings on all standard C++ header files.
---
 gdb/unittests/string_view-selftests.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/gdb/unittests/string_view-selftests.c b/gdb/unittests/string_view-selftests.c
index 2d7261d18d3..441d533b54e 100644
--- a/gdb/unittests/string_view-selftests.c
+++ b/gdb/unittests/string_view-selftests.c
@@ -23,6 +23,11 @@
 
 #define GNULIB_NAMESPACE gnulib
 
+#include "diagnostics.h"
+
+DIAGNOSTIC_PUSH
+DIAGNOSTIC_IGNORE_USER_DEFINED_WARNINGS
+
 #include "defs.h"
 #include "gdbsupport/selftest.h"
 #include "gdbsupport/gdb_string_view.h"
@@ -34,6 +39,8 @@
 #include <fstream>
 #include <iostream>
 
+DIAGNOSTIC_POP
+
 /* libstdc++'s testsuite uses VERIFY.  */
 #define VERIFY SELF_CHECK
 
-- 
2.34.1

[PATCH 02/40] sim: Check known getrusage declaration existence

[Tsukasa OI]

Clang generates a warning if there is a function declaration/definition
with zero arguments. Such declarations/definitions without a prototype (an
argument list) are deprecated forms of indefinite arguments
("-Wdeprecated-non-prototype"). On the default configuration, it causes a
build failure (unless "--disable-werror" is specified).

Such getrusage function declarations are placed in three files under sim/ppc
and to avoid defining those on the modern environments, this commit will
make the configuration script to find the known declaration of getrusage
and defines HAVE_DECL_GETRUSAGE if it finds one.

If we find one (and we *will* in most modern environments), we don't need
to rely on the deprecated declarations.
---
 sim/config.h.in  |  4 ++++
 sim/configure    | 32 ++++++++++++++++++++++++++++++++
 sim/configure.ac | 10 ++++++++++
 3 files changed, 46 insertions(+)

diff --git a/sim/config.h.in b/sim/config.h.in
index 9a94b289e46..bc7ec588ec6 100644
--- a/sim/config.h.in
+++ b/sim/config.h.in
@@ -44,6 +44,10 @@
 /* Is the prototype for getopt in <unistd.h> in the expected format? */
 #undef HAVE_DECL_GETOPT
 
+/* Is the prototype for getrusage in <sys/resource.h> in the expected format?
+   */
+#undef HAVE_DECL_GETRUSAGE
+
 /* Define to 1 if you have the declaration of `tzname', and to 0 if you don't.
    */
 #undef HAVE_DECL_TZNAME
diff --git a/sim/configure b/sim/configure
index dac7f085be1..fbdd256d374 100755
--- a/sim/configure
+++ b/sim/configure
@@ -16460,6 +16460,38 @@ $as_echo "#define HAVE_DECL_GETOPT 1" >>confdefs.h
 
 fi
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a known getrusage prototype in sys/resource.h" >&5
+$as_echo_n "checking for a known getrusage prototype in sys/resource.h... " >&6; }
+if ${sim_cv_decl_getrusage_sys_resource_h+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#include <sys/resource.h>
+int
+main ()
+{
+extern int getrusage (int, struct rusage *);
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  sim_cv_decl_getrusage_sys_resource_h=yes
+else
+  sim_cv_decl_getrusage_sys_resource_h=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $sim_cv_decl_getrusage_sys_resource_h" >&5
+$as_echo "$sim_cv_decl_getrusage_sys_resource_h" >&6; }
+if test $sim_cv_decl_getrusage_sys_resource_h = yes; then
+
+$as_echo "#define HAVE_DECL_GETRUSAGE 1" >>confdefs.h
+
+fi
+
 
 
 
diff --git a/sim/configure.ac b/sim/configure.ac
index be0cfdbea32..9411fc10f9d 100644
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -187,6 +187,16 @@ if test $sim_cv_decl_getopt_unistd_h = yes; then
 	    [Is the prototype for getopt in <unistd.h> in the expected format?])
 fi
 
+AC_MSG_CHECKING(for a known getrusage prototype in sys/resource.h)
+AC_CACHE_VAL(sim_cv_decl_getrusage_sys_resource_h,
+[AC_COMPILE_IFELSE([AC_LANG_PROGRAM([#include <sys/resource.h>], [extern int getrusage (int, struct rusage *);])],
+sim_cv_decl_getrusage_sys_resource_h=yes, sim_cv_decl_getrusage_sys_resource_h=no)])
+AC_MSG_RESULT($sim_cv_decl_getrusage_sys_resource_h)
+if test $sim_cv_decl_getrusage_sys_resource_h = yes; then
+  AC_DEFINE([HAVE_DECL_GETRUSAGE], 1,
+	    [Is the prototype for getrusage in <sys/resource.h> in the expected format?])
+fi
+
 dnl These are unfortunate.  They are conditionally called by other sim macros
 dnl but always used by common/Make-common.in.  So we have to subst here even
 dnl when the rest of the code is in the respective macros.  Once we merge the
-- 
2.34.1

[PATCH 03/40] sim/aarch64: Remove unused functions

[Tsukasa OI]

Clang generates a warning if there is a unused static function
("-Wunused-function").  On the default configuration, it causes a build
failure (unless "--disable-werror" is specified).

This commit removes unused functions from the AArch64 simulator.
---
 sim/aarch64/simulator.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 516a7830522..5881725cefd 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -83,22 +83,6 @@
     }									\
   while (0)
 
-/* Helper functions used by expandLogicalImmediate.  */
-
-/* for i = 1, ... N result<i-1> = 1 other bits are zero  */
-static inline uint64_t
-ones (int N)
-{
-  return (N == 64 ? (uint64_t)-1UL : ((1UL << N) - 1));
-}
-
-/* result<0> to val<N>  */
-static inline uint64_t
-pickbit (uint64_t val, int N)
-{
-  return pickbits64 (val, N, N);
-}
-
 static uint64_t
 expand_logical_immediate (uint32_t S, uint32_t R, uint32_t N)
 {
-- 
2.34.1

[PATCH 04/40] cpu/cris: Initialize some variables on CRIS CPU

[Tsukasa OI]

GCC / Clang generate a warning if a variable may be used uninitialized on
some cases (Clang: "-Wsometimes-uninitialized").  When the program is being
built by Clang with the default configuration, it causes a build failure
(unless "--disable-werror" is specified).

Those error occur on sim/cris/semcrisv{10,32}f-switch.c but they are
CGEN-generated files.  The real cause of this problem is in cpu/cris.cpu
which does not initialize certain variables.

This commit ensures such variables are initialized to zero by default.
Note that this commit itself does not regenerate CRIS CPU related files
with CGEN because it still has several issues preventing regeneration.
They are to be fixed in the later commits.

cpu/ChangeLog:

	* cris.cpu: Initialize condres, newval and tmpres variables.
---
 cpu/cris.cpu | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/cpu/cris.cpu b/cpu/cris.cpu
index 97b44581e78..cd85f4e94e2 100644
--- a/cpu/cris.cpu
+++ b/cpu/cris.cpu
@@ -541,6 +541,7 @@
   (sequence
     BI
     ((SI tmpcond) (BI condres))
+    (set condres 0)
     (set tmpcond condno)
      (.splice
       cond
@@ -2655,6 +2656,7 @@
      (sequence
        ((SI rno) (SI newval))
        (set rno (regno Pd))
+       (set newval 0)
        (.splice
 	cond
 	; No sanity check for constant special register here, since the
@@ -3698,6 +3700,7 @@
   (sequence
     SI
     ((SI tmpcode) (SI tmpval) (SI tmpres))
+    (set tmpres 0)
     (set tmpcode swapcode)
     (set tmpval val)
     (.splice
-- 
2.34.1

[PATCH 05/40] cpu/cris: Add u-stall virtual unit to CRIS v32

[Tsukasa OI]

Because CRIS v32 model does not define u-stall virtual unit, CGEN-generated
sim/cris/decodev32.h does not define the function declaration of
crisv32f_model_crisv32_u_stall.

It led to a hack in commit 4e6e8ba7c565 ("sim: cris: clean up missing func
prototype warnings"), manually adding the declaration of
crisv32f_model_crisv32_u_stall.

To **not** touch CGEN-generated files manually, this commit adds u-stall
virtual unit for CRIS v32 to let CGEN generate the function declaration of
crisv32f_model_crisv32_u_stall automatically.

This is still hackish but less than the previous one.

cpu/ChangeLog:

	* cris.cpu: Add u-stall virtual unit to CRIS v32.
---
 cpu/cris.cpu | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cpu/cris.cpu b/cpu/cris.cpu
index cd85f4e94e2..a2d054f954c 100644
--- a/cpu/cris.cpu
+++ b/cpu/cris.cpu
@@ -284,6 +284,7 @@
   (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ())
   (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ())
   (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ())
+  (unit u-stall "Stall unit" () 1 1 () () () ())
 
   ; For v32, we need to keep track of inputs (for movem destination
   ; cycle penalties) and output (for e.g. memory source and jump
-- 
2.34.1

[PATCH 06/40] sim/cris: Move declarations of f_specific_init

[Tsukasa OI]

Declarations for MY (f_specific_init) functions are defined in CGEN-
generated header files: sim/cris/decodev10.h (crisv10f_specific_init) and
sim/cris/decodev32.h (crisv32f_specific_init).  However, those declarations
are manually added by the commit 4e6e8ba7c565 ("sim: cris: clean up missing
func prototype warnings") as a hack and not a CGEN-generated part.

Those definitions are required by $(builddir)/sim/cris/mloopv{10,32}f.c,
generated from $(srcdir)/sim/cris/mloop.in.  If we define a declaration in
mloop.in, we no longer need manually added one.

This commit adds a template for function declaration so that we no longer
have to touch CGEN-generated code.  With this and the previous commit
"cpu/cris: Add stall unit to CRIS v32", we can now safely regenerate
CRIS CPU declarations with CGEN.
---
 sim/cris/cris-tmpl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c
index 9f0c06e755e..8694d38b2af 100644
--- a/sim/cris/cris-tmpl.c
+++ b/sim/cris/cris-tmpl.c
@@ -264,6 +264,8 @@ MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
 
 /* Hook function for per-cpu simulator initialization.  */
 
+extern void MY (f_specific_init) (SIM_CPU *);
+
 void
 MY (f_specific_init) (SIM_CPU *current_cpu)
 {
-- 
2.34.1

[PATCH 07/40] sim/cris: Regenerate with CGEN

[Tsukasa OI]

All CRIS-related files are regenerated by custom CGEN that is modified by
the author (CGEN change will be separately upstreamed).
---
 sim/cris/arch.c               |  5 +++--
 sim/cris/arch.h               | 21 +++++++++++++++------
 sim/cris/cpuall.h             |  5 +++--
 sim/cris/cpuv10.c             |  6 ++++--
 sim/cris/cpuv10.h             |  5 +++--
 sim/cris/cpuv32.c             |  6 ++++--
 sim/cris/cpuv32.h             |  5 +++--
 sim/cris/decodev10.c          | 21 +++++++++++----------
 sim/cris/decodev10.h          |  6 +++---
 sim/cris/decodev32.c          | 21 +++++++++++----------
 sim/cris/decodev32.h          |  8 ++++----
 sim/cris/modelv10.c           |  5 +++--
 sim/cris/modelv32.c           |  5 +++--
 sim/cris/semcrisv10f-switch.c | 20 +++++++++++++-------
 sim/cris/semcrisv32f-switch.c | 20 +++++++++++++-------
 15 files changed, 96 insertions(+), 63 deletions(-)

diff --git a/sim/cris/arch.c b/sim/cris/arch.c
index 1d50838f0a1..b502c239fca 100644
--- a/sim/cris/arch.c
+++ b/sim/cris/arch.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/cris/arch.h b/sim/cris/arch.h
index 037b463438d..57d51236c03 100644
--- a/sim/cris/arch.h
+++ b/sim/cris/arch.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
 #ifndef CRIS_ARCH_H
 #define CRIS_ARCH_H
 
+#define TARGET_BIG_ENDIAN 1
+
+#define WI  SI
+#define UWI USI
+#define AI  USI
+
+#define IAI USI
+
 /* Enum declaration for model types.  */
 typedef enum model_type {
   MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX
@@ -36,10 +45,10 @@ typedef enum unit_type {
   UNIT_NONE, UNIT_CRISV10_U_MOVEM, UNIT_CRISV10_U_MULTIPLY, UNIT_CRISV10_U_SKIP4
  , UNIT_CRISV10_U_STALL, UNIT_CRISV10_U_CONST32, UNIT_CRISV10_U_CONST16, UNIT_CRISV10_U_MEM
  , UNIT_CRISV10_U_EXEC, UNIT_CRISV32_U_EXEC_TO_SR, UNIT_CRISV32_U_EXEC_MOVEM, UNIT_CRISV32_U_EXEC
- , UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16, UNIT_CRISV32_U_JUMP
- , UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH, UNIT_CRISV32_U_MULTIPLY
- , UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W, UNIT_CRISV32_U_MEM_R
- , UNIT_CRISV32_U_MEM, UNIT_MAX
+ , UNIT_CRISV32_U_STALL, UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16
+ , UNIT_CRISV32_U_JUMP, UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH
+ , UNIT_CRISV32_U_MULTIPLY, UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W
+ , UNIT_CRISV32_U_MEM_R, UNIT_CRISV32_U_MEM, UNIT_MAX
 } UNIT_TYPE;
 
 #define MAX_UNITS (4)
diff --git a/sim/cris/cpuall.h b/sim/cris/cpuall.h
index 145646f4ed0..c600f5d3a31 100644
--- a/sim/cris/cpuall.h
+++ b/sim/cris/cpuall.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/cris/cpuv10.c b/sim/cris/cpuv10.c
index d53aa556e73..d188590e486 100644
--- a/sim/cris/cpuv10.c
+++ b/sim/cris/cpuv10.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -490,3 +491,4 @@ crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *current_cpu, SI newval)
 {
   CPU (h_prefixreg_pre_v32) = newval;
 }
+
diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h
index 30555c8244e..296279ff918 100644
--- a/sim/cris/cpuv10.h
+++ b/sim/cris/cpuv10.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/cris/cpuv32.c b/sim/cris/cpuv32.c
index ad9af980aa1..997ef2c7533 100644
--- a/sim/cris/cpuv32.c
+++ b/sim/cris/cpuv32.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -586,3 +587,4 @@ crisv32f_h_prefixreg_v32_set (SIM_CPU *current_cpu, SI newval)
 {
   SET_H_PREFIXREG_V32 (newval);
 }
+
diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h
index b23eff4f52a..affb72f99b8 100644
--- a/sim/cris/cpuv32.h
+++ b/sim/cris/cpuv32.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/cris/decodev10.c b/sim/cris/decodev10.c
index 257961ae160..ebf511c1a2d 100644
--- a/sim/cris/decodev10.c
+++ b/sim/cris/decodev10.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -41,12 +42,12 @@ static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX];
 
 static const struct insn_sem crisv10f_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY },
   { CRIS_INSN_NOP, CRISV10F_INSN_NOP, CRISV10F_SFMT_NOP },
   { CRIS_INSN_MOVE_B_R, CRISV10F_INSN_MOVE_B_R, CRISV10F_SFMT_MOVE_B_R },
   { CRIS_INSN_MOVE_W_R, CRISV10F_INSN_MOVE_W_R, CRISV10F_SFMT_MOVE_B_R },
@@ -254,7 +255,7 @@ static const struct insn_sem crisv10f_insn_sem[] =
 
 static const struct insn_sem crisv10f_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */
@@ -303,7 +304,7 @@ crisv10f_init_idesc_table (SIM_CPU *cpu)
     init_idesc (cpu, id, t);
 
   /* Now fill in the values for the chosen cpu.  */
-  for (t = crisv10f_insn_sem, tend = t + ARRAY_SIZE (crisv10f_insn_sem);
+  for (t = crisv10f_insn_sem, tend = t + sizeof (crisv10f_insn_sem) / sizeof (*t);
        t != tend; ++t)
     {
       init_idesc (cpu, & table[t->index], t);
diff --git a/sim/cris/decodev10.h b/sim/cris/decodev10.h
index c742c2fe9c6..a3307ad8d21 100644
--- a/sim/cris/decodev10.h
+++ b/sim/cris/decodev10.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -30,7 +31,6 @@ extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
 extern void crisv10f_init_idesc_table (SIM_CPU *);
 extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
 extern void crisv10f_semf_init_idesc_table (SIM_CPU *);
-extern void crisv10f_specific_init (SIM_CPU *);
 
 /* Enum declaration for instructions in cpu family crisv10f.  */
 typedef enum crisv10f_insn_type {
diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c
index d6afafa377f..c382f9f6b2f 100644
--- a/sim/cris/decodev32.c
+++ b/sim/cris/decodev32.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -41,12 +42,12 @@ static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX];
 
 static const struct insn_sem crisv32f_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY },
   { CRIS_INSN_MOVE_B_R, CRISV32F_INSN_MOVE_B_R, CRISV32F_SFMT_MOVE_B_R },
   { CRIS_INSN_MOVE_W_R, CRISV32F_INSN_MOVE_W_R, CRISV32F_SFMT_MOVE_B_R },
   { CRIS_INSN_MOVE_D_R, CRISV32F_INSN_MOVE_D_R, CRISV32F_SFMT_MOVE_D_R },
@@ -258,7 +259,7 @@ static const struct insn_sem crisv32f_insn_sem[] =
 
 static const struct insn_sem crisv32f_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */
@@ -307,7 +308,7 @@ crisv32f_init_idesc_table (SIM_CPU *cpu)
     init_idesc (cpu, id, t);
 
   /* Now fill in the values for the chosen cpu.  */
-  for (t = crisv32f_insn_sem, tend = t + ARRAY_SIZE (crisv32f_insn_sem);
+  for (t = crisv32f_insn_sem, tend = t + sizeof (crisv32f_insn_sem) / sizeof (*t);
        t != tend; ++t)
     {
       init_idesc (cpu, & table[t->index], t);
diff --git a/sim/cris/decodev32.h b/sim/cris/decodev32.h
index aae993b7881..94c483b03a1 100644
--- a/sim/cris/decodev32.h
+++ b/sim/cris/decodev32.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -30,7 +31,6 @@ extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
 extern void crisv32f_init_idesc_table (SIM_CPU *);
 extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
 extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
-extern void crisv32f_specific_init (SIM_CPU *);
 
 /* Enum declaration for instructions in cpu family crisv32f.  */
 typedef enum crisv32f_insn_type {
@@ -126,8 +126,8 @@ typedef enum crisv32f_sfmt_type {
 extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
 extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
 extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
-extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
 extern int crisv32f_model_crisv32_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
 extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
 extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
 extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
diff --git a/sim/cris/modelv10.c b/sim/cris/modelv10.c
index 2ff4f5262b2..1f0d5fa367d 100644
--- a/sim/cris/modelv10.c
+++ b/sim/cris/modelv10.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/cris/modelv32.c b/sim/cris/modelv32.c
index 86087f99ff4..f056fd41c26 100644
--- a/sim/cris/modelv32.c
+++ b/sim/cris/modelv32.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c
index f31b29442fd..a2f1505405e 100644
--- a/sim/cris/semcrisv10f-switch.c
+++ b/sim/cris/semcrisv10f-switch.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -260,7 +261,7 @@ This file is part of the GNU simulators.
 
 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
    off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
+/* FIXME: A better way would be to have TRACE_RESULT check for something
    that can cause it to be optimized out.  Another way would be to emit
    special handlers into the instruction "stream".  */
 
@@ -3379,6 +3380,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
   SI tmp_rno;
   SI tmp_newval;
   tmp_rno = FLD (f_operand2);
+  tmp_newval = 0;
 if (EQSI (tmp_rno, 5)) {
   tmp_newval = EXTHISI (({   SI tmp_addr;
   HI tmp_tmp_mem;
@@ -10993,7 +10995,8 @@ SET_H_VBIT_MOVE (0);
   tmp_tmpd = ({   SI tmp_tmpcode;
   SI tmp_tmpval;
   SI tmp_tmpres;
-  tmp_tmpcode = FLD (f_operand2);
+  tmp_tmpres = 0;
+;   tmp_tmpcode = FLD (f_operand2);
 ;   tmp_tmpval = tmp_tmps;
 ; if (EQSI (tmp_tmpcode, 0)) {
   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
@@ -12060,7 +12063,8 @@ if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
   BI tmp_truthval;
   tmp_truthval = ({   SI tmp_tmpcond;
   BI tmp_condres;
-  tmp_tmpcond = FLD (f_operand2);
+  tmp_condres = 0;
+;   tmp_tmpcond = FLD (f_operand2);
 ; if (EQSI (tmp_tmpcond, 0)) {
   tmp_condres = NOTBI (CPU (h_cbit));
 }
@@ -12192,7 +12196,8 @@ if (tmp_truthval) {
   BI tmp_truthval;
   tmp_truthval = ({   SI tmp_tmpcond;
   BI tmp_condres;
-  tmp_tmpcond = FLD (f_operand2);
+  tmp_condres = 0;
+;   tmp_tmpcond = FLD (f_operand2);
 ; if (EQSI (tmp_tmpcond, 0)) {
   tmp_condres = NOTBI (CPU (h_cbit));
 }
@@ -13065,7 +13070,8 @@ SET_H_VBIT_MOVE (0);
   BI tmp_truthval;
   tmp_truthval = ({   SI tmp_tmpcond;
   BI tmp_condres;
-  tmp_tmpcond = FLD (f_operand2);
+  tmp_condres = 0;
+;   tmp_tmpcond = FLD (f_operand2);
 ; if (EQSI (tmp_tmpcond, 0)) {
   tmp_condres = NOTBI (CPU (h_cbit));
 }
diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c
index ab15d6ee36c..bf06e8aa6ca 100644
--- a/sim/cris/semcrisv32f-switch.c
+++ b/sim/cris/semcrisv32f-switch.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, see <http://www.gnu.org/licenses/>.
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -264,7 +265,7 @@ This file is part of the GNU simulators.
 
 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
    off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
+/* FIXME: A better way would be to have TRACE_RESULT check for something
    that can cause it to be optimized out.  Another way would be to emit
    special handlers into the instruction "stream".  */
 
@@ -3291,6 +3292,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
   SI tmp_rno;
   SI tmp_newval;
   tmp_rno = FLD (f_operand2);
+  tmp_newval = 0;
 if (EQSI (tmp_rno, 2)) {
   tmp_newval = ({   SI tmp_addr;
   SI tmp_tmp_mem;
@@ -11263,7 +11265,8 @@ SET_H_VBIT_MOVE (0);
   tmp_tmpd = ({   SI tmp_tmpcode;
   SI tmp_tmpval;
   SI tmp_tmpres;
-  tmp_tmpcode = FLD (f_operand2);
+  tmp_tmpres = 0;
+;   tmp_tmpcode = FLD (f_operand2);
 ;   tmp_tmpval = tmp_tmps;
 ; if (EQSI (tmp_tmpcode, 0)) {
   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
@@ -12460,7 +12463,8 @@ crisv32f_rfg_handler (current_cpu, pc);
   BI tmp_truthval;
   tmp_truthval = ({   SI tmp_tmpcond;
   BI tmp_condres;
-  tmp_tmpcond = FLD (f_operand2);
+  tmp_condres = 0;
+;   tmp_tmpcond = FLD (f_operand2);
 ; if (EQSI (tmp_tmpcond, 0)) {
   tmp_condres = NOTBI (CPU (h_cbit));
 }
@@ -12592,7 +12596,8 @@ if (tmp_truthval) {
   BI tmp_truthval;
   tmp_truthval = ({   SI tmp_tmpcond;
   BI tmp_condres;
-  tmp_tmpcond = FLD (f_operand2);
+  tmp_condres = 0;
+;   tmp_tmpcond = FLD (f_operand2);
 ; if (EQSI (tmp_tmpcond, 0)) {
   tmp_condres = NOTBI (CPU (h_cbit));
 }
@@ -13380,7 +13385,8 @@ SET_H_VBIT_MOVE (0);
   BI tmp_truthval;
   tmp_truthval = ({   SI tmp_tmpcond;
   BI tmp_condres;
-  tmp_tmpcond = FLD (f_operand2);
+  tmp_condres = 0;
+;   tmp_tmpcond = FLD (f_operand2);
 ; if (EQSI (tmp_tmpcond, 0)) {
   tmp_condres = NOTBI (CPU (h_cbit));
 }
-- 
2.34.1

[PATCH 08/40] sim/erc32: Insert void parameter

[Tsukasa OI]

Clang generates a warning if there is a function declaration/definition
with zero arguments.  Such declarations/definitions without a prototype (an
argument list) are deprecated forms of indefinite arguments
("-Wdeprecated-non-prototype").  On the default configuration, it causes a
build failure (unless "--disable-werror" is specified).

This commit replaces () with (void) to avoid this warning.
---
 sim/erc32/func.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/erc32/func.c b/sim/erc32/func.c
index 4d1942065b8..af92c9f7d48 100644
--- a/sim/erc32/func.c
+++ b/sim/erc32/func.c
@@ -298,7 +298,7 @@ disp_reg(struct pstate *sregs, char *reg)
 #ifdef ERRINJ
 
 void
-errinj()
+errinj (void)
 {
     int	err;
 
@@ -322,7 +322,7 @@ errinj()
 }
 
 void
-errinjstart()
+errinjstart (void)
 {
     if (errper) event(errinj, 0, (random()%errper));
 }
@@ -855,7 +855,7 @@ event(void (*cfunc) (), int32_t arg, uint64_t delta)
 
 #if 0	/* apparently not used */
 void
-stop_event()
+stop_event(void)
 {
 }
 #endif
-- 
2.34.1

[PATCH 09/40] sim/erc32: Use int32_t as event callback argument

[Tsukasa OI]

Clang generates a warning if an argument is passed to a function without
prototype (zero arguments, even without (void)).  Such calls are deprecated
forms of indefinite arguments passing ("-Wdeprecated-non-prototype").
On the default configuration, it causes a build failure (unless
"--disable-werror" is specified).

To fix that, this commit makes struct evcell to use int32_t as a callback
(cfunc) argument of an event.
---
 sim/erc32/erc32.c | 28 ++++++++++++++--------------
 sim/erc32/func.c  |  8 ++++----
 sim/erc32/sis.h   |  4 ++--
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/sim/erc32/erc32.c b/sim/erc32/erc32.c
index 0206c02e6f0..d7cc1f1cf3b 100644
--- a/sim/erc32/erc32.c
+++ b/sim/erc32/erc32.c
@@ -274,19 +274,19 @@ static void	port_init (void);
 static uint32_t	read_uart (uint32_t addr);
 static void	write_uart (uint32_t addr, uint32_t data);
 static void	flush_uart (void);
-static void	uarta_tx (void);
-static void	uartb_tx (void);
-static void	uart_rx (void *arg);
-static void	uart_intr (void *arg);
+static void	uarta_tx (int32_t);
+static void	uartb_tx (int32_t);
+static void	uart_rx (int32_t);
+static void	uart_intr (int32_t);
 static void	uart_irq_start (void);
-static void	wdog_intr (void *arg);
+static void	wdog_intr (int32_t);
 static void	wdog_start (void);
-static void	rtc_intr (void *arg);
+static void	rtc_intr (int32_t);
 static void	rtc_start (void);
 static uint32_t	rtc_counter_read (void);
 static void	rtc_scaler_set (uint32_t val);
 static void	rtc_reload_set (uint32_t val);
-static void	gpt_intr (void *arg);
+static void	gpt_intr (int32_t);
 static void	gpt_start (void);
 static uint32_t	gpt_counter_read (void);
 static void	gpt_scaler_set (uint32_t val);
@@ -1245,7 +1245,7 @@ flush_uart(void)
 
 ATTRIBUTE_UNUSED
 static void
-uarta_tx(void)
+uarta_tx(int32_t arg ATTRIBUTE_UNUSED)
 {
 
     while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
@@ -1261,7 +1261,7 @@ uarta_tx(void)
 
 ATTRIBUTE_UNUSED
 static void
-uartb_tx(void)
+uartb_tx(int32_t arg ATTRIBUTE_UNUSED)
 {
     while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
     if (uart_stat_reg & UARTB_HRE) {
@@ -1276,7 +1276,7 @@ uartb_tx(void)
 
 ATTRIBUTE_UNUSED
 static void
-uart_rx(void *arg)
+uart_rx(int32_t arg ATTRIBUTE_UNUSED)
 {
     int32_t           rsize;
     char            rxd;
@@ -1318,7 +1318,7 @@ uart_rx(void *arg)
 }
 
 static void
-uart_intr(void *arg)
+uart_intr(int32_t arg ATTRIBUTE_UNUSED)
 {
     read_uart(0xE8);		/* Check for UART interrupts every 1000 clk */
     flush_uart();		/* Flush UART ports      */
@@ -1341,7 +1341,7 @@ uart_irq_start(void)
 /* Watch-dog */
 
 static void
-wdog_intr(void *arg)
+wdog_intr(int32_t arg ATTRIBUTE_UNUSED)
 {
     if (wdog_status == disabled) {
 	wdog_status = stopped;
@@ -1379,7 +1379,7 @@ wdog_start(void)
 
 
 static void
-rtc_intr(void *arg)
+rtc_intr(int32_t arg ATTRIBUTE_UNUSED)
 {
     if (rtc_counter == 0) {
 
@@ -1430,7 +1430,7 @@ rtc_reload_set(uint32_t val)
 }
 
 static void
-gpt_intr(void *arg)
+gpt_intr(int32_t arg ATTRIBUTE_UNUSED)
 {
     if (gpt_counter == 0) {
 	mec_irq(12);
diff --git a/sim/erc32/func.c b/sim/erc32/func.c
index af92c9f7d48..6971ae0129d 100644
--- a/sim/erc32/func.c
+++ b/sim/erc32/func.c
@@ -298,7 +298,7 @@ disp_reg(struct pstate *sregs, char *reg)
 #ifdef ERRINJ
 
 void
-errinj (void)
+errinj (int32_t arg ATTRIBUTE_UNUSED)
 {
     int	err;
 
@@ -887,8 +887,8 @@ advance_time(struct pstate *sregs)
 {
 
     struct evcell  *evrem;
-    void            (*cfunc) ();
-    uint32_t          arg;
+    void            (*cfunc) (int32_t);
+    int32_t           arg;
     uint64_t          endtime;
 
 #ifdef STAT
@@ -926,7 +926,7 @@ int
 wait_for_irq(void)
 {
     struct evcell  *evrem;
-    void            (*cfunc) ();
+    void            (*cfunc) (int32_t);
     int32_t           arg;
     uint64_t          endtime;
 
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h
index 71033137f2c..36346cae641 100644
--- a/sim/erc32/sis.h
+++ b/sim/erc32/sis.h
@@ -124,7 +124,7 @@ struct pstate {
 };
 
 struct evcell {
-    void            (*cfunc) ();
+    void            (*cfunc) (int32_t);
     int32_t           arg;
     uint64_t          time;
     struct evcell  *nxt;
@@ -183,7 +183,7 @@ extern void	init_signals (void);
 struct disassemble_info;
 extern void	dis_mem (uint32_t addr, uint32_t len,
 			 struct disassemble_info *info);
-extern void	event (void (*cfunc) (), int32_t arg, uint64_t delta);
+extern void	event (void (*cfunc) (int32_t), int32_t arg, uint64_t delta);
 extern void	set_int (int32_t level, void (*callback) (), int32_t arg);
 extern void	advance_time (struct pstate  *sregs);
 extern uint32_t	now (void);
-- 
2.34.1

[PATCH 10/40] sim/erc32: Use int32_t as IRQ callback argument

[Tsukasa OI]

Clang generates a warning if an argument is passed to a function without
prototype (zero arguments, even without (void)).  Such calls are deprecated
forms of indefinite arguments passing ("-Wdeprecated-non-prototype").
On the default configuration, it (somehow) doesn't cause a build failure but
a warning is generated.

But because the cause is the same as the issue the author fixed in
"sim/erc32: Use int32_t as event callback argument", it would be better to
fix it now to prevent problems in the future.

To fix the issue, this commit makes struct irqcall to use int32_t as a
callback (callback) argument of an IRQ.
---
 sim/erc32/func.c | 2 +-
 sim/erc32/sis.h  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/erc32/func.c b/sim/erc32/func.c
index 6971ae0129d..527df172660 100644
--- a/sim/erc32/func.c
+++ b/sim/erc32/func.c
@@ -874,7 +874,7 @@ init_event(void)
 }
 
 void
-set_int(int32_t level, void (*callback) (), int32_t arg)
+set_int(int32_t level, void (*callback) (int32_t), int32_t arg)
 {
     irqarr[level & 0x0f].callback = callback;
     irqarr[level & 0x0f].arg = arg;
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h
index 36346cae641..df6b22c47b0 100644
--- a/sim/erc32/sis.h
+++ b/sim/erc32/sis.h
@@ -137,7 +137,7 @@ struct estate {
 };
 
 struct irqcell {
-    void            (*callback) ();
+    void            (*callback) (int32_t);
     int32_t           arg;
 };
 
@@ -184,7 +184,7 @@ struct disassemble_info;
 extern void	dis_mem (uint32_t addr, uint32_t len,
 			 struct disassemble_info *info);
 extern void	event (void (*cfunc) (int32_t), int32_t arg, uint64_t delta);
-extern void	set_int (int32_t level, void (*callback) (), int32_t arg);
+extern void	set_int (int32_t level, void (*callback) (int32_t), int32_t arg);
 extern void	advance_time (struct pstate  *sregs);
 extern uint32_t	now (void);
 extern int	wait_for_irq (void);
-- 
2.34.1

[PATCH 11/40] cpu/frv: Initialize some variables

[Tsukasa OI]

GCC generates a warning if a variable may be used uninitialized on some
cases ("-Wmaybe-uninitialized").  Despite that this will not cause a build
failure even on the default configuration (with "--enable-werror"), it is
better to be fixed.

The cause of this warning, sim/frv/sem.c is generated by CGEN from
cpu/frv.cpu.  This commit adds initialization of some variables that caused
GCC warnings.

cpu/ChangeLog:

	* frv.cpu (cmpb): Initialize cc variable.
	(load-double-gr-u-semantics, clddu) Initialize address variable.
---
 cpu/frv.cpu | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/cpu/frv.cpu b/cpu/frv.cpu
index cdb169eddc1..6af8c3ab347 100644
--- a/cpu/frv.cpu
+++ b/cpu/frv.cpu
@@ -4266,6 +4266,7 @@
      "cmpb$pack $GRi,$GRj,$ICCi_1"
      (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj)
      (sequence ((QI cc))
+	       (set cc 0)
 	       (set-n cc (eq (and GRi #xff000000) (and GRj #xff000000)))
 	       (set-z cc (eq (and GRi #x00ff0000) (and GRj #x00ff0000)))
 	       (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00)))
@@ -4655,6 +4656,7 @@
 
 (define-pmacro (load-double-gr-u-semantics)
   (sequence ((WI address))
+	    (set address 0)
 	    (load-double-semantics 0 DI GR address GRj)
 	    (if (ne (index-of GRi) (index-of GRdoublek))
 		(sequence ()
@@ -5309,6 +5311,7 @@
      (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj)
      (if (eq CCi (or cond 2))
 	 (sequence ((WI address))
+		   (set address 0)
 		   (load-double-semantics 0 DI GR address GRj)
 		   (if (ne (index-of GRi) (index-of GRdoublek))
 		       (set GRi address))))
-- 
2.34.1

[PATCH 12/40] sim/frv: Initialize nesr variable

[Tsukasa OI]

GCC generates a warning if a variable may be used uninitialized on some
cases ("-Wmaybe-uninitialized").  Despite that GCC will not cause a build
failure even when "--enable-werror" is specified, it would be nice to get
rid of it.

This commit initializes the variable nesr when declared.
---
 sim/frv/traps.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/frv/traps.c b/sim/frv/traps.c
index 0c9eacd0bfd..b142c7890ad 100644
--- a/sim/frv/traps.c
+++ b/sim/frv/traps.c
@@ -432,7 +432,7 @@ frvbf_check_non_excepting_load (
   int do_elos;
   SI NE_flags[2];
   SI NE_base;
-  SI nesr;
+  SI nesr = 0;
   SI ne_index;
   FRV_REGISTER_CONTROL *control;
 
-- 
2.34.1

[PATCH 13/40] sim/frv: Initialize some variables

[Tsukasa OI]

This commit is strongly related to "cpu/frv: Initialize some variables" and
applies corresponding changes to sim/frv/sem.c.

Note:
This commit touches CGEN-generated files directly.
Modifying cpu/frv.cpu (which is done) and regenerating with CGEN is the best
way to prevent this issue from happening again but there is another known
regression in CGEN to resolve.
---
 sim/frv/sem.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sim/frv/sem.c b/sim/frv/sem.c
index cc7cbeee318..28610f4eac7 100644
--- a/sim/frv/sem.c
+++ b/sim/frv/sem.c
@@ -3054,6 +3054,7 @@ SEM_FN_NAME (frvbf,cmpb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   QI tmp_cc;
+  tmp_cc = 0;
 if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 0xff000000), ANDSI (GET_H_GR (FLD (f_GRj)), 0xff000000)), 0)) {
   tmp_cc = ANDQI (tmp_cc, 7);
 } else {
@@ -4545,6 +4546,7 @@ SEM_FN_NAME (frvbf,lddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   SI tmp_address;
+  tmp_address = 0;
 if (NESI (FLD (f_GRk), 0)) {
 {
   tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
@@ -4591,6 +4593,7 @@ SEM_FN_NAME (frvbf,nlddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (tmp_do_op) {
 {
   SI tmp_address;
+  tmp_address = 0;
 if (NESI (FLD (f_GRk), 0)) {
 {
   tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
@@ -6706,6 +6709,7 @@ SEM_FN_NAME (frvbf,clddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
 {
   SI tmp_address;
+  tmp_address = 0;
 if (NESI (FLD (f_GRk), 0)) {
 {
   tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-- 
2.34.1

[PATCH 14/40] sim/frv: Add explicit casts

[Tsukasa OI]

Clang generates a warning if there is an enum value with a mismatching type
without an explicit cast ("-Wenum-conversion").
On the default configuration, it causes a build failure
(unless "--disable-werror" is specified).

This commit adds explicit casts on the FR-V instruction decoder.

Note:
This commit touches CGEN-generated files directly.
Modifying CGEN is the best way to prevent this issue from happening again
but there is another known regression in CGEN to resolve.
---
 sim/frv/decode.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/sim/frv/decode.c b/sim/frv/decode.c
index 307b593e148..9c4a97833ad 100644
--- a/sim/frv/decode.c
+++ b/sim/frv/decode.c
@@ -39,12 +39,12 @@ static IDESC frvbf_insn_data[FRVBF_INSN__MAX];
 
 static const struct insn_sem frvbf_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, FRVBF_INSN_X_AFTER, FRVBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, FRVBF_INSN_X_BEFORE, FRVBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, FRVBF_INSN_X_CTI_CHAIN, FRVBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, FRVBF_INSN_X_CHAIN, FRVBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, FRVBF_INSN_X_BEGIN, FRVBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, FRVBF_INSN_X_AFTER, FRVBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, FRVBF_INSN_X_BEFORE, FRVBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, FRVBF_INSN_X_CTI_CHAIN, FRVBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, FRVBF_INSN_X_CHAIN, FRVBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, FRVBF_INSN_X_BEGIN, FRVBF_SFMT_EMPTY },
   { FRV_INSN_ADD, FRVBF_INSN_ADD, FRVBF_SFMT_ADD },
   { FRV_INSN_SUB, FRVBF_INSN_SUB, FRVBF_SFMT_ADD },
   { FRV_INSN_AND, FRVBF_INSN_AND, FRVBF_SFMT_ADD },
@@ -792,7 +792,7 @@ static const struct insn_sem frvbf_insn_sem[] =
 
 static const struct insn_sem frvbf_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */
-- 
2.34.1

[PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments

[Tsukasa OI]

Clang generates a warning if there is a redundant self-assignment
("-Wself-assign").  On the default configuration, it causes a build failure
(unless "--disable-werror" is specified).

However, removing self-assignments in step_once function makes the code less
readable.  Instead, this commit inserts dummy addition to match the comments
"Value added == 0".  This is redundant but will suppress warnings and
matches with other branches better.  It will be also optimized away so we
can ignore performance impact on this.
---
 sim/h8300/compile.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 9be7dd565a9..f7d8d590b69 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -4141,7 +4141,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
 	  res = GET_B_REG (code->src.reg);	/* FIXME fetch? */
 	  if (!c && (0 <= (res >>  4) && (res >>  4) <= 9) && 
 	      !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
-	    res = res;		/* Value added == 0.  */
+	    res = res + 0x0;		/* Value added == 0.  */
 	  else if (!c && (0  <= (res >>  4) && (res >>  4) <=  8) && 
 		   !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
 	    res = res + 0x6;		/* Value added == 6.  */
@@ -4174,7 +4174,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
 	  res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
 	  if (!c && (0 <= (res >>  4) && (res >>  4) <= 9) && 
 	      !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
-	    res = res;		/* Value added == 0.  */
+	    res = res + 0x0;		/* Value added == 0.  */
 	  else if (!c && (0 <= (res >>  4) && (res >>  4) <=  8) && 
 		    h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
 	    res = res + 0xfa;		/* Value added == 0xfa.  */
-- 
2.34.1

[PATCH 16/40] sim/lm32: fix some missing function declaration warnings

[Tsukasa OI]

From: Andrew Burgess <aburgess@redhat.com>

In the lm32 simulator, I was seeing some warnings about missing
function declarations.

The lm32 simulator has a weird header structure, in order to pull in
the full cpu.h header we need to define WANT_CPU_LM32BF.  This is done
in some files, but not in others.  Critically, it's not done in some
files that then use functions declared in cpu.h

In this commit I added the missing #define so that the full cpu.h can
be included.

After doing this there are still a few functions that are used
undeclared, these functions appear to be missing any declarations at
all, so I've added some to cpu.h.

With this done all the warnings when compiling lm32 are resolved for
both gcc and clang, so I've removed the SIM_WERROR_CFLAGS line from
Makefile.in, this allows lm32 to build with -Werror.
---
 sim/lm32/Makefile.in  |  3 ---
 sim/lm32/cpu.h        | 11 +++++++++++
 sim/lm32/dv-lm32cpu.c |  3 +++
 sim/lm32/user.c       |  3 +++
 4 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/sim/lm32/Makefile.in b/sim/lm32/Makefile.in
index d827b711d45..db15bef47a7 100644
--- a/sim/lm32/Makefile.in
+++ b/sim/lm32/Makefile.in
@@ -24,9 +24,6 @@ SIM_EXTRA_DEPS = $(CGEN_INCLUDE_DEPS) $(srcdir)/../../opcodes/lm32-desc.h \
 
 SIM_EXTRA_CLEAN = lm32-clean
 
-# Some modules don't build cleanly yet.
-dv-lm32cpu.o mloop.o sem.o traps.o user.o: SIM_WERROR_CFLAGS =
-
 ## COMMON_POST_CONFIG_FRAG
 
 arch = lm32 
diff --git a/sim/lm32/cpu.h b/sim/lm32/cpu.h
index 05b98be8cf1..d025065f2ba 100644
--- a/sim/lm32/cpu.h
+++ b/sim/lm32/cpu.h
@@ -163,6 +163,17 @@ struct scache {
   struct argbuf argbuf;
 };
 
+/* From traps.c.  */
+extern USI lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0);
+extern USI lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2);
+extern USI lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2);
+extern void lm32bf_wcsr_insn (SIM_CPU * current_cpu, USI f_csr, USI r1);
+extern USI lm32bf_break_insn (SIM_CPU * current_cpu, IADDR pc);
+extern USI lm32bf_scall_insn (SIM_CPU * current_cpu, IADDR pc);
+
+/* From user.c.  */
+extern UINT lm32bf_user_insn (SIM_CPU * current_cpu, INT r0, INT r1, UINT imm);
+
 /* Macros to simplify extraction, reading and semantic code.
    These define and assign the local vars that contain the insn's fields.  */
 
diff --git a/sim/lm32/dv-lm32cpu.c b/sim/lm32/dv-lm32cpu.c
index b97580e80a3..15a08eee815 100644
--- a/sim/lm32/dv-lm32cpu.c
+++ b/sim/lm32/dv-lm32cpu.c
@@ -18,6 +18,9 @@
    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
+#define WANT_CPU lm32bf
+#define WANT_CPU_LM32BF
+
 /* This must come before any other includes.  */
 #include "defs.h"
 
diff --git a/sim/lm32/user.c b/sim/lm32/user.c
index 3cc21a208ee..d301d482c1b 100644
--- a/sim/lm32/user.c
+++ b/sim/lm32/user.c
@@ -21,6 +21,9 @@
 /* This must come before any other includes.  */
 #include "defs.h"
 
+#define WANT_CPU lm32bf
+#define WANT_CPU_LM32BF
+
 #include "sim-main.h"
 
 /* Handle user defined instructions.  */
-- 
2.34.1

[PATCH 17/40] sim/lm32: Add explicit casts

[Tsukasa OI]

Clang generates a warning if there is an enum value with a mismatching type
without an explicit cast ("-Wenum-conversion").
On the default configuration, it causes a build failure
(unless "--disable-werror" is specified).

This commit adds explicit casts on the LatticeMico32 instruction decoder.

Note:
This commit touches CGEN-generated files directly.
Modifying CGEN is the best way to prevent this issue from happening again
but there is another known regression in CGEN or sim/lm32 to resolve.
---
 sim/lm32/decode.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/sim/lm32/decode.c b/sim/lm32/decode.c
index 9faef289132..889a0de9026 100644
--- a/sim/lm32/decode.c
+++ b/sim/lm32/decode.c
@@ -39,12 +39,12 @@ static IDESC lm32bf_insn_data[LM32BF_INSN__MAX];
 
 static const struct insn_sem lm32bf_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY },
   { LM32_INSN_ADD, LM32BF_INSN_ADD, LM32BF_SFMT_ADD },
   { LM32_INSN_ADDI, LM32BF_INSN_ADDI, LM32BF_SFMT_ADDI },
   { LM32_INSN_AND, LM32BF_INSN_AND, LM32BF_SFMT_ADD },
@@ -111,7 +111,7 @@ static const struct insn_sem lm32bf_insn_sem[] =
 
 static const struct insn_sem lm32bf_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */
-- 
2.34.1

Re: [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1)

[Tsukasa OI]

Oh no.

Despite that
-   PATCH 04/40
-   PATCH 05/40
-   PATCH 11/40
are to be reviewed in this ML, I am not supposed to send whole this
patchset to this mailing list.

I apologize for inconvenience and confusion.

On 2022/10/20 18:25, Tsukasa OI wrote:
> Hi all,
> 
> In my environment (Ubuntu 22.04.1 LTS + LLVM Clang 15.0.0/15.0.3), I have
> finally managed to build almost default configuration of all-arch Binutils +
> GDB ("--enable-targets=all") with Clang and -Werror enabled (by default).
> 
> This patchset is what I originally intended to split to multiple parts (in
> fact, I submitted several patchsets that are originally a part of this) but
> shared here (without splitting) to discuss and share information who wants
> to build Binutils + GDB with Clang.
> 
> Related components (for review):
> -   3 : cpu (Binutils)
>     -   PATCH 04/40 (CRIS)
>     -   PATCH 05/40 (CRIS)
>     -   PATCH 11/40 (FR-V)
> -   1 : gdb (GDB)
>     -   PATCH 01/40 (same patch as below):
>         <https://sourceware.org/pipermail/gdb-patches/2022-October/192802.html>
> -  36 : sim (GDB)
> 
> Each resolves relatively small issue and/or non-issue (which Clang thinks
> it is a problem).
> 
> 
> [Credit]
> 
> PATCH 16/40 is entirely authored by Andrew Burgess (exactly the same as):
> <https://sourceware.org/pipermail/gdb-patches/2022-October/192841.html>
> 
> 
> [Limitation]
> 
> I only tested this on Linux (x86_64) and with almost default configuration.
> My initial submission of gdb patch above confirmed broken on Mac due to
> different C++ standard library (fixed though) but I cannot guarantee whether
> this patchset is all we need.
> So, non-default components and non-default configurations may still have
> problems building with Clang (e.g. assemblers except x86).
> 
> 
> [Shared Technique: Explicit cast to CGEN_INSN_TYPE]
> 
> -   PATCH 07/40: CRIS (in the process of regenerating all files)
> -   PATCH 14/40: FR-V
> -   PATCH 17/40: LatticeMicro32
> -   PATCH 23/40: M32R
> -   PATCH 38/40: BPF
> -   PATCH 39/40: IQ2000
> -   PATCH 40/40: OpenRISC 1000
> 
> In CGEN-generated instruction decoder, instruction type has CGEN_INSN_TYPE
> values but some contain CGEN_INSN_VIRTUAL_TYPE values.  On such cases,
> CGEN_INSN_VIRTUAL_TYPE values must be explicitly converted to CGEN_INSN_TYPE
> to prevent build failure caused by Clang warnings ("-Wenum-conversion").
> 
> I'm going to upstream this change to CGEN but due to known regressions,
> I did not regenerate those files using CGEN (except CRIS (PATCH 07/40),
> which I used a WIP version of CGEN).
> 
> 
> [Related Patches]
> 
> -   PATCH 02/40 is a prerequisite of PATCH 26/40.
>     We don't want to declare getrusage ourself (as possible).
>     If we have a known declaration of getrusage with known prototype,
>     we no longer need to declare getrusage with indeterminate arguments
>     (without prototype).  This is similar to getopt in Binutils.
> 
> 
> Thanks,
> Tsukasa
> 
> 
> 
> 
> Andrew Burgess (1):
>   sim/lm32: fix some missing function declaration warnings
> 
> Tsukasa OI (39):
>   gdb/unittests: PR28413, suppress warnings generated by Gnulib
>   sim: Check known getrusage declaration existence
>   sim/aarch64: Remove unused functions
>   cpu/cris: Initialize some variables on CRIS CPU
>   cpu/cris: Add u-stall virtual unit to CRIS v32
>   sim/cris: Move declarations of f_specific_init
>   sim/cris: Regenerate with CGEN
>   sim/erc32: Insert void parameter
>   sim/erc32: Use int32_t as event callback argument
>   sim/erc32: Use int32_t as IRQ callback argument
>   cpu/frv: Initialize some variables
>   sim/frv: Initialize nesr variable
>   sim/frv: Initialize some variables
>   sim/frv: Add explicit casts
>   sim/h8300: Add "+ 0x0" to avoid self-assignments
>   sim/lm32: Add explicit casts
>   sim/m32c: Stop using middle dot
>   sim/m32r: Initialize "list" variable
>   sim/m32r: Prepare required functions
>   sim/m32r: Declare all required functions
>   sim/m32r: Fixes to Linux emulator
>   sim/m32r: Add explicit casts
>   sim/mips: Fix enum type-related issues on cp1.c
>   sim/mn10300: Add an explicit cast
>   sim/ppc: Remove getrusage declarations if possible
>   sim/ppc: Add extra parenthesis to avoid ambiguity
>   sim/ppc: Initialize stat type buffer
>   sim/ppc: Fix indentation on generated code
>   sim/ppc: Use TRACE with initialized entry_point
>   sim/ppc: Initialize help variables
>   sim/ppc: Add an explicit cast
>   sim/ppc: Initialize reg and control_nr
>   sim/rx: Mark unused function
>   sim/sh: Initialize some variables
>   sim/sh: Use fabs instead of abs
>   sim/sh: Remove redundant function declaration
>   sim/bpf: Add explicit casts
>   sim/iq2000: Add explicit casts
>   sim/or1k: Add explicit casts
> 
>  cpu/cris.cpu                          |  4 ++++
>  cpu/frv.cpu                           |  3 +++
>  gdb/unittests/string_view-selftests.c |  7 ++++++
>  sim/aarch64/simulator.c               | 16 --------------
>  sim/bpf/decode-be.c                   | 14 ++++++------
>  sim/bpf/decode-le.c                   | 14 ++++++------
>  sim/config.h.in                       |  4 ++++
>  sim/configure                         | 32 +++++++++++++++++++++++++++
>  sim/configure.ac                      | 10 +++++++++
>  sim/cris/arch.c                       |  5 +++--
>  sim/cris/arch.h                       | 21 +++++++++++++-----
>  sim/cris/cpuall.h                     |  5 +++--
>  sim/cris/cpuv10.c                     |  6 +++--
>  sim/cris/cpuv10.h                     |  5 +++--
>  sim/cris/cpuv32.c                     |  6 +++--
>  sim/cris/cpuv32.h                     |  5 +++--
>  sim/cris/cris-tmpl.c                  |  2 ++
>  sim/cris/decodev10.c                  | 21 +++++++++---------
>  sim/cris/decodev10.h                  |  6 ++---
>  sim/cris/decodev32.c                  | 21 +++++++++---------
>  sim/cris/decodev32.h                  |  8 +++----
>  sim/cris/modelv10.c                   |  5 +++--
>  sim/cris/modelv32.c                   |  5 +++--
>  sim/cris/semcrisv10f-switch.c         | 20 +++++++++++------
>  sim/cris/semcrisv32f-switch.c         | 20 +++++++++++------
>  sim/erc32/erc32.c                     | 28 +++++++++++------------
>  sim/erc32/func.c                      | 14 ++++++------
>  sim/erc32/sis.h                       |  8 +++----
>  sim/frv/decode.c                      | 14 ++++++------
>  sim/frv/sem.c                         |  4 ++++
>  sim/frv/traps.c                       |  2 +-
>  sim/h8300/compile.c                   |  4 ++--
>  sim/iq2000/decode.c                   | 14 ++++++------
>  sim/lm32/Makefile.in                  |  3 ---
>  sim/lm32/cpu.h                        | 11 +++++++++
>  sim/lm32/decode.c                     | 14 ++++++------
>  sim/lm32/dv-lm32cpu.c                 |  3 +++
>  sim/lm32/user.c                       |  3 +++
>  sim/m32c/mem.c                        |  2 +-
>  sim/m32r/decode.c                     | 14 ++++++------
>  sim/m32r/decode2.c                    | 14 ++++++------
>  sim/m32r/decodex.c                    | 14 ++++++------
>  sim/m32r/m32r-sim.h                   | 24 +++++++++++++++-----
>  sim/m32r/m32r2.c                      |  5 +++++
>  sim/m32r/m32rx.c                      |  5 +++++
>  sim/m32r/sim-if.c                     |  4 ++++
>  sim/m32r/traps.c                      | 28 +++++++++++++++++++++--
>  sim/mips/cp1.c                        |  8 +++----
>  sim/mn10300/op_utils.c                |  5 +++--
>  sim/or1k/decode.c                     | 14 ++++++------
>  sim/ppc/altivec.igen                  |  2 +-
>  sim/ppc/emul_netbsd.c                 |  4 +++-
>  sim/ppc/emul_unix.c                   |  2 ++
>  sim/ppc/hw_ide.c                      |  8 +++----
>  sim/ppc/hw_phb.c                      |  2 +-
>  sim/ppc/hw_sem.c                      |  4 ++--
>  sim/ppc/igen.c                        |  2 +-
>  sim/ppc/mon.c                         |  2 ++
>  sim/ppc/sim_calls.c                   |  4 ++--
>  sim/rx/rx.c                           |  2 +-
>  sim/sh/gencode.c                      |  4 ++--
>  sim/sh/interp.c                       |  4 +---
>  62 files changed, 358 insertions(+), 206 deletions(-)
> 
> 
> base-commit: 837e225ba1992f9745e5bbbd5e8443243a7f475f

Re: [PATCH 05/40] cpu/cris: Add u-stall virtual unit to CRIS v32

[Hans-Peter Nilsson]

On Thu, 20 Oct 2022, Tsukasa OI via Binutils wrote:

> Because CRIS v32 model does not define u-stall virtual unit, CGEN-generated
> sim/cris/decodev32.h does not define the function declaration of
> crisv32f_model_crisv32_u_stall.
> 
> It led to a hack in commit 4e6e8ba7c565 ("sim: cris: clean up missing func
> prototype warnings"), manually adding the declaration of
> crisv32f_model_crisv32_u_stall.
> 
> To **not** touch CGEN-generated files manually, this commit adds u-stall
> virtual unit for CRIS v32 to let CGEN generate the function declaration of
> crisv32f_model_crisv32_u_stall automatically.
> 
> This is still hackish but less than the previous one.

Why "hackish"?  You mean cgen should not hork on not 
all models defining all the same units even if unused?

> cpu/ChangeLog:
> 
> 	* cris.cpu: Add u-stall virtual unit to CRIS v32.

Ok, thanks, with or without a comment above it saying "This unit 
is not used in CRIS v32 but needs to be defined for CGEN".

brgds, H-P

Re: [PATCH 06/40] sim/cris: Move declarations of f_specific_init

[Hans-Peter Nilsson]

On Thu, 20 Oct 2022, Tsukasa OI via Binutils wrote:

> Declarations for MY (f_specific_init) functions are defined in CGEN-
> generated header files: sim/cris/decodev10.h (crisv10f_specific_init) and
> sim/cris/decodev32.h (crisv32f_specific_init).  However, those declarations
> are manually added by the commit 4e6e8ba7c565 ("sim: cris: clean up missing
> func prototype warnings") as a hack and not a CGEN-generated part.
> 
> Those definitions are required by $(builddir)/sim/cris/mloopv{10,32}f.c,
> generated from $(srcdir)/sim/cris/mloop.in.  If we define a declaration in
> mloop.in, we no longer need manually added one.
> 
> This commit adds a template for function declaration so that we no longer
> have to touch CGEN-generated code.  With this and the previous commit
> "cpu/cris: Add stall unit to CRIS v32", we can now safely regenerate
> CRIS CPU declarations with CGEN.
> ---
>  sim/cris/cris-tmpl.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c
> index 9f0c06e755e..8694d38b2af 100644
> --- a/sim/cris/cris-tmpl.c
> +++ b/sim/cris/cris-tmpl.c
> @@ -264,6 +264,8 @@ MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
>  
>  /* Hook function for per-cpu simulator initialization.  */
>  
> +extern void MY (f_specific_init) (SIM_CPU *);
> +
>  void
>  MY (f_specific_init) (SIM_CPU *current_cpu)
>  {
> -- 
> 2.34.1
> 
> 

Ok, thanks.

brgds, H-P

Re: [PATCH 04/40] cpu/cris: Initialize some variables on CRIS CPU

[Hans-Peter Nilsson]

On Thu, 20 Oct 2022, Tsukasa OI via Binutils wrote:

> GCC / Clang generate a warning if a variable may be used uninitialized on
> some cases (Clang: "-Wsometimes-uninitialized").  When the program is being
> built by Clang with the default configuration, it causes a build failure
> (unless "--disable-werror" is specified).
> 
> Those error occur on sim/cris/semcrisv{10,32}f-switch.c but they are
> CGEN-generated files.  The real cause of this problem is in cpu/cris.cpu
> which does not initialize certain variables.

I'd say the problem is an artefact of CGEN code generation, as 
the conditions are exhaustive.  In the generated code it's far 
from obvious though...

> This commit ensures such variables are initialized to zero by default.
> Note that this commit itself does not regenerate CRIS CPU related files
> with CGEN because it still has several issues preventing regeneration.
> They are to be fixed in the later commits.
> 
> cpu/ChangeLog:
> 
> 	* cris.cpu: Initialize condres, newval and tmpres variables.

Ok with a comment saying something to the effect of "It's not 
obvious in generated code that all cases are covered in the 
conditional settings below, so initialize this to avoid compiler 
warnings" (and referring to the previous comment for all but the 
first).

Thanks!
brgds, H-P

Re: [PATCH 07/40] sim/cris: Regenerate with CGEN

[Hans-Peter Nilsson]

On Thu, 20 Oct 2022, Tsukasa OI via Binutils wrote:

> All CRIS-related files are regenerated by custom CGEN that is modified by
> the author (CGEN change will be separately upstreamed).
> ---
>  sim/cris/arch.c               |  5 +++--
>  sim/cris/arch.h               | 21 +++++++++++++++------
>  sim/cris/cpuall.h             |  5 +++--
>  sim/cris/cpuv10.c             |  6 ++++--
>  sim/cris/cpuv10.h             |  5 +++--
>  sim/cris/cpuv32.c             |  6 ++++--
>  sim/cris/cpuv32.h             |  5 +++--
>  sim/cris/decodev10.c          | 21 +++++++++++----------
>  sim/cris/decodev10.h          |  6 +++---
>  sim/cris/decodev32.c          | 21 +++++++++++----------
>  sim/cris/decodev32.h          |  8 ++++----
>  sim/cris/modelv10.c           |  5 +++--
>  sim/cris/modelv32.c           |  5 +++--
>  sim/cris/semcrisv10f-switch.c | 20 +++++++++++++-------
>  sim/cris/semcrisv32f-switch.c | 20 +++++++++++++-------
>  15 files changed, 96 insertions(+), 63 deletions(-)

This is ok and obvious.

BTW, I see you sent this and other sim/ patches to just 
binutils.  I CC:ed gdb-patches@, the proper list for sim/ 
patches.  (A bit odd that cpu/ patches need to go to just 
binutils@; logically they should go to both lists.)

brgds, H-P

Re: [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1)

[Mike Frysinger]

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this patch series is for gdb & sim, but you've sent it to the binutils group.
gdb & sim patches should be sent to the gdb-patches@ mailing list instead.
-mike

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Re: [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1)

[Tsukasa OI]

On 2022/10/23 4:01, Mike Frysinger wrote:
> this patch series is for gdb & sim, but you've sent it to the binutils group.
> gdb & sim patches should be sent to the gdb-patches@ mailing list instead.
> -mike

My mistake.
I noticed while "git send-email" command sent PATCH 17/40 and I stopped
the process immediately (and reposted whole patchset to gdb-patches).
Not only that, this patchset should have been [RFC PATCH], not [PATCH]
(because it was a mere copy of my working branch, to share/sync with
other developers, especially Andrew).

I'll respond your reviews in gdb-patches separately.

Thanks,
Tsukasa

Re: [PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments

[Jeff Law]

On 10/20/22 03:26, Tsukasa OI via Binutils wrote:
> Clang generates a warning if there is a redundant self-assignment
> ("-Wself-assign").  On the default configuration, it causes a build failure
> (unless "--disable-werror" is specified).
>
> However, removing self-assignments in step_once function makes the code less
> readable.  Instead, this commit inserts dummy addition to match the comments
> "Value added == 0".  This is redundant but will suppress warnings and
> matches with other branches better.  It will be also optimized away so we
> can ignore performance impact on this.
> ---
>   sim/h8300/compile.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

OK.

jeff