From: Haochen Jiang <haochen.jiang@intel.com>
To: binutils@sourceware.org
Cc: jbeulich@suse.com, hjl.tools@gmail.com,
Kong Lingling <lingling.kong@intel.com>
Subject: [PATCH 06/10] Support Intel RAO-INT
Date: Fri, 14 Oct 2022 17:12:44 +0800 [thread overview]
Message-ID: <20221014091248.4920-7-haochen.jiang@intel.com> (raw)
In-Reply-To: <20221014091248.4920-1-haochen.jiang@intel.com>
From: Kong Lingling <lingling.kong@intel.com>
gas/ChangeLog:
* NEWS: Support Intel RAO-INT.
* config/tc-i386.c: Add raoint.
* doc/c-i386.texi: Document .raoint and noraoint.
* testsuite/gas/i386/i386.exp: Run RAOINT tests.
* testsuite/gas/i386/raoint-intel.d: New test.
* testsuite/gas/i386/raoint.d: Ditto.
* testsuite/gas/i386/raoint.s: Ditto.
* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (MOD_0F38FC): New.
(PREFIX_0F38FC): Ditto.
(mod_table): Add MOD_0F38FC.
(prefix_table): Add PREFIX_0F38FC.
* i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and
CPU_ANY_RAOINT_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h: (CpuRAOINT): New.
(i386_cpu_flags): Add cpuraoint.
* i386-opc.tbl: Add RAOINT instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 3 +-
gas/doc/c-i386.texi | 4 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/raoint-intel.d | 18 +
gas/testsuite/gas/i386/raoint.d | 18 +
gas/testsuite/gas/i386/raoint.s | 15 +
gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
opcodes/i386-dis.c | 16 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 514 +-
opcodes/i386-opc.h | 5 +-
opcodes/i386-opc.tbl | 9 +
opcodes/i386-tbl.h | 7874 +++++++++---------
16 files changed, 4379 insertions(+), 4159 deletions(-)
create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/raoint.d
create mode 100644 gas/testsuite/gas/i386/raoint.s
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
diff --git a/gas/NEWS b/gas/NEWS
index 9757209a9f..f352c5ab89 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel RAO-INT instructions.
+
* Add support for Intel CMPccXADD instructions.
* Add support for Intel AVX-NE-CONVERT instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 7045e18cff..07d72d1af1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
- SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
+ SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
+ SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 62202157b3..3832628e6e 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -217,6 +217,7 @@ accept various extension mnemonics. For example,
@code{avx_vnni_int8},
@code{avx_ne_convert},
@code{cmpccxadd},
+@code{raoint},
@code{noavx512f},
@code{noavx512cd},
@code{noavx512er},
@@ -241,6 +242,7 @@ accept various extension mnemonics. For example,
@code{noavx_vnni_int8},
@code{noavx_ne_convert},
@code{nocmpccxadd},
+@code{noraoint},
@code{noenqcmd},
@code{noserialize},
@code{notsxldtrk},
@@ -1542,7 +1544,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd}
+@item @samp{.cmpccxadd} @tab @samp{.raoint}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index fb2e2aa446..1eb0eabb6b 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -486,6 +486,8 @@ if [gas_32_check] then {
run_dump_test "avx-ne-convert"
run_dump_test "avx-ne-convert-intel"
run_list_test "cmpccxadd-inval"
+ run_dump_test "raoint"
+ run_dump_test "raoint-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1162,6 +1164,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx-ne-convert-intel"
run_dump_test "x86-64-cmpccxadd"
run_dump_test "x86-64-cmpccxadd-intel"
+ run_dump_test "x86-64-raoint"
+ run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
new file mode 100644
index 0000000000..b50d423a5f
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAOINT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
new file mode 100644
index 0000000000..2c310c5cc7
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAOINT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
new file mode 100644
index 0000000000..63398dfb82
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.s
@@ -0,0 +1,15 @@
+# Check 32bit AVX-NE-CONVERT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %edx, (%eax) #RAO-INT
+ aand %edx, (%eax) #RAO-INT
+ aor %edx, (%eax) #RAO-INT
+ axor %edx, (%eax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd DWORD PTR [eax], %edx #RAO-INT
+ aand DWORD PTR [eax], %edx #RAO-INT
+ aor DWORD PTR [eax], %edx #RAO-INT
+ axor DWORD PTR [eax], %edx #RAO-INT
diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
new file mode 100644
index 0000000000..d7de4849a2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAOINT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
new file mode 100644
index 0000000000..711fe48064
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAOINT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
new file mode 100644
index 0000000000..28590626ca
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.s
@@ -0,0 +1,15 @@
+# Check 64bit RAOINT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %rdx, (%rax) #RAO-INT
+ aand %rdx, (%rax) #RAO-INT
+ aor %rdx, (%rax) #RAO-INT
+ axor %rdx, (%rax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd QWORD PTR [rax], %rdx #RAO-INT
+ aand QWORD PTR [rax], %rdx #RAO-INT
+ aor QWORD PTR [rax], %rdx #RAO-INT
+ axor QWORD PTR [rax], %rdx #RAO-INT
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 37bbbd3815..60a334bbd6 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -887,6 +887,7 @@ enum
MOD_0F38F9,
MOD_0F38FA_PREFIX_1,
MOD_0F38FB_PREFIX_1,
+ MOD_0F38FC,
MOD_0F3A0F_PREFIX_1,
MOD_VEX_0F12_PREFIX_0,
@@ -1086,6 +1087,7 @@ enum
PREFIX_0F38F8,
PREFIX_0F38FA,
PREFIX_0F38FB,
+ PREFIX_0F38FC,
PREFIX_0F3A0F,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
@@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
{ MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
+ /* PREFIX_0F38FC */
+ {
+ { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
+ { "axor", { Edq, Gdq }, PREFIX_OPCODE },
+ { "aand", { Edq, Gdq }, PREFIX_OPCODE },
+ { "aor", { Edq, Gdq }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F3A0F */
{
{ Bad_Opcode },
@@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = {
{ MOD_TABLE (MOD_0F38F9) },
{ PREFIX_TABLE (PREFIX_0F38FA) },
{ PREFIX_TABLE (PREFIX_0F38FB) },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38FC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = {
{ Bad_Opcode },
{ "encodekey256", { Gd, Ed }, 0 },
},
+ {
+ /* MOD_0F38FC */
+ { PREFIX_TABLE (PREFIX_0F38FC) },
+ },
{
/* MOD_0F3A0F_PREFIX_1 */
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 96d8d2ceb8..3a7511a242 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -253,6 +253,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
{ "CPU_CMPCCXADD_FLAGS",
"CpuCMPCCXADD" },
+ { "CPU_RAOINT_FLAGS",
+ "CpuRAOINT" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -455,6 +457,8 @@ static initializer cpu_flag_init[] =
"CpuAVX_NE_CONVERT" },
{ "CPU_ANY_CMPCCXADD_FLAGS",
"CpuCMPCCXADD" },
+ { "CPU_ANY_RAOINT_FLAGS",
+ "CpuRAOINT" },
};
static initializer operand_type_init[] =
@@ -660,6 +664,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_VNNI_INT8),
BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuCMPCCXADD),
+ BITFIELD (CpuRAOINT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 052c59b162..cb6c372203 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -217,6 +217,8 @@ enum
CpuAVX_NE_CONVERT,
/* Intel CMPccXADD instructions support required. */
CpuCMPCCXADD,
+ /* Intel RAO INT Instructions support required. */
+ CpuRAOINT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -400,6 +402,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_vnni_int8:1;
unsigned int cpuavx_ne_convert:1;
unsigned int cpucmpccxadd:1;
+ unsigned int cpuraoint:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -436,7 +439,7 @@ typedef union i386_cpu_flags
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
- // unsigned int unused:(CpuNumOfBits - CpuUnused);
+ unsigned int unused:(CpuNumOfBits - CpuUnused);
#endif
} bitfield;
unsigned int array[CpuNumOfUints];
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 2b704708a4..4affd056b2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
// CMPCCXADD instructions end.
+
+// RAOINT instructions.
+
+aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+
+// RAOINT instructions end.
--
2.18.2
next prev parent reply other threads:[~2022-10-14 9:14 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` Haochen Jiang [this message]
2022-10-14 14:38 ` [PATCH 06/10] Support Intel RAO-INT Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221014091248.4920-7-haochen.jiang@intel.com \
--to=haochen.jiang@intel.com \
--cc=binutils@sourceware.org \
--cc=hjl.tools@gmail.com \
--cc=jbeulich@suse.com \
--cc=lingling.kong@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).