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From: "Kong, Lingling" <lingling.kong@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>,
	"Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
	"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 06/10] Support Intel RAO-INT
Date: Mon, 7 Nov 2022 13:37:06 +0000	[thread overview]
Message-ID: <DM4PR11MB54876D3DE0B6C4DEC61EBD0CEC3C9@DM4PR11MB5487.namprd11.prod.outlook.com> (raw)
In-Reply-To: <d1be684d-eae3-72bd-1f64-0d07a3556d66@suse.com>

> On 06.11.2022 13:50, Kong, Lingling wrote:
> >>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>
> >>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
> >>>> does enough for Intel syntax memory operands - please double check;
> >>>> if not this will need fixing).
> >>>>
> > Yes,  now it changed to CheckRegSize.
> 
> For one I'm pretty sure I said I was wrong about IgnoreSize. And as to
> CheckRegSize - did you actually double check as indicated? While I think the
> attribute should be there, I've also observed recently that it missing on e.g.
> MOVBE does not currently make any difference (there are the same bogus
> diagnostics with and without it). So while I don't mind it being put there, H.J.
> may view this differently as long as the attribute doesn't really have any effect.

Thanks for reminding, IgnoreSize was deleted by mistake.  Although I tested some difference Intel syntax memory operands,  there is no difference in the result with or without CheckRegSize. For CheckRegSize, as far as the semantics of rao-int's operand is concerned, it needs to be checked.

> > --- a/opcodes/i386-opc.h
> > +++ b/opcodes/i386-opc.h
> > @@ -223,6 +223,8 @@ enum
> >    CpuMSRLIST,
> >    /* Intel AVX NE CONVERT Instructions support required.  */
> >    CpuAVX_NE_CONVERT,
> > +  /* Intel RAO INT Instructions support required.  */  CpuRAO_INT,
> >    /* mwaitx instruction required */
> >    CpuMWAITX,
> >    /* Clzero instruction required */
> 
> This and ...
> 
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64,
> > No_bSuf|No_wSuf|No_lSuf|No_sSuf|N  wrmsrlist, 0xf30f01c6, None,
> > CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> {}
> >
> >  // MSRLIST instructions end.
> > +
> > +// RAO-INT instructions.
> > +
> > +aadd, 0xf38fc, None, CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc,
> > +None, CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc,
> > +Reg32|None,
> > +CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc,
> > +None, CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> > +
> > +// RAO-INT instructions end.
> 
> ... this doesn't look like valid changes - line breaks are at the wrong spots.
> 
> Jan

Sorry, It is mistake about my git send-email, updated again.

Subject: [PATCH] Support Intel RAO-INT

gas/ChangeLog:

	* NEWS: Support Intel RAO-INT.
	* config/tc-i386.c: Add raoint.
	* doc/c-i386.texi: Document .raoint.
	* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
	* testsuite/gas/i386/raoint-intel.d: New test.
	* testsuite/gas/i386/raoint.d: Ditto.
	* testsuite/gas/i386/raoint.s: Ditto.
	* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F38FC): New.
	(prefix_table): Add PREFIX_0F38FC.
	* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
	CPU_ANY_RAO_INT_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h: (CpuRAO_INT): New.
	(i386_cpu_flags): Add cpuraoint.
	* i386-opc.tbl: Add RAO_INT instructions.
	* i386-tbl.h: Regenerated.
---
 gas/NEWS                                     |    2 +
 gas/config/tc-i386.c                         |    1 +
 gas/doc/c-i386.texi                          |    3 +-
 gas/testsuite/gas/i386/i386.exp              |    4 +
 gas/testsuite/gas/i386/raoint-intel.d        |   18 +
 gas/testsuite/gas/i386/raoint.d              |   18 +
 gas/testsuite/gas/i386/raoint.s              |   15 +
 gas/testsuite/gas/i386/x86-64-raoint-intel.d |   18 +
 gas/testsuite/gas/i386/x86-64-raoint.d       |   18 +
 gas/testsuite/gas/i386/x86-64-raoint.s       |   15 +
 opcodes/i386-dis.c                           |   11 +-
 opcodes/i386-gen.c                           |    5 +
 opcodes/i386-init.h                          |  518 +-
 opcodes/i386-opc.h                           |    3 +
 opcodes/i386-opc.tbl                         |    9 +
 opcodes/i386-tbl.h                           | 7906 +++++++++---------
 16 files changed, 4389 insertions(+), 4175 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
 create mode 100644 gas/testsuite/gas/i386/raoint.d
 create mode 100644 gas/testsuite/gas/i386/raoint.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s

diff --git a/gas/NEWS b/gas/NEWS
index f35e8a93a0..86731348e3 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for Intel RAO-INT instructions.
+
 * Add support for Intel AVX-NE-CONVERT instructions.
 
 * Add support for Intel MSRLIST instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a846b9e865..6dcf11470c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
   SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
   SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
+  SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false),
 };
 
 #undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 0ef1cece48..6fa1199f32 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -201,6 +201,7 @@ accept various extension mnemonics.  For example,
 @code{wrmsrns},
 @code{msrlist},
 @code{avx_ne_convert},
+@code{rao_int},
 @code{amx_int8},
 @code{amx_bf16},
 @code{amx_fp16},
@@ -1496,7 +1497,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
 @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
-@item @samp{.avx_ne_convert}
+@item @samp{.avx_ne_convert} @tab @samp{.rao_int}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9ddf2b451e..5b20ac7ce5 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -485,6 +485,8 @@ if [gas_32_check] then {
     run_list_test "msrlist-inval"
     run_dump_test "avx-ne-convert"
     run_dump_test "avx-ne-convert-intel"
+    run_dump_test "raoint"
+    run_dump_test "raoint-intel"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "invlpgb"
@@ -1166,6 +1168,8 @@ if [gas_64_check] then {
     run_dump_test "x86-64-msrlist-intel"
     run_dump_test "x86-64-avx-ne-convert"
     run_dump_test "x86-64-avx-ne-convert-intel"
+    run_dump_test "x86-64-raoint"
+    run_dump_test "x86-64-raoint-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
new file mode 100644
index 0000000000..2c22b9c8d0
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAO_INT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   DWORD PTR \[eax\],edx
diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
new file mode 100644
index 0000000000..4a6a4e9b21
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAO_INT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   %edx,\(%eax\)
diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
new file mode 100644
index 0000000000..04a13ddeb9
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.s
@@ -0,0 +1,15 @@
+# Check 32bit RAO-INT instructions
+
+	.allow_index_reg
+	.text
+_start:
+        aadd    %edx, (%eax)     #RAO-INT
+        aand    %edx, (%eax)     #RAO-INT
+        aor     %edx, (%eax)     #RAO-INT
+        axor    %edx, (%eax)     #RAO-INT
+
+.intel_syntax noprefix
+        aadd    DWORD PTR [eax], %edx    #RAO-INT
+        aand    DWORD PTR [eax], %edx    #RAO-INT
+        aor     DWORD PTR [eax], %edx    #RAO-INT
+        axor    DWORD PTR [eax], %edx    #RAO-INT
diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
new file mode 100644
index 0000000000..5b5c9051ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAO_INT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   QWORD PTR \[rax\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
new file mode 100644
index 0000000000..ccdf027737
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAO_INT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   %rdx,\(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
new file mode 100644
index 0000000000..645bcfc3c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.s
@@ -0,0 +1,15 @@
+# Check 64bit RAO_INT instructions
+
+	.allow_index_reg
+	.text
+_start:
+        aadd    %rdx, (%rax)     #RAO-INT
+        aand    %rdx, (%rax)     #RAO-INT
+        aor     %rdx, (%rax)     #RAO-INT
+        axor    %rdx, (%rax)     #RAO-INT
+
+.intel_syntax noprefix
+        aadd    QWORD PTR [rax], %rdx    #RAO-INT
+        aand    QWORD PTR [rax], %rdx    #RAO-INT
+        aor     QWORD PTR [rax], %rdx    #RAO-INT
+        axor    QWORD PTR [rax], %rdx    #RAO-INT
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f0638a3193..ee7fc09932 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1076,6 +1076,7 @@ enum
   PREFIX_0F38F8,
   PREFIX_0F38FA,
   PREFIX_0F38FB,
+  PREFIX_0F38FC,
   PREFIX_0F3A0F,
   PREFIX_VEX_0F10,
   PREFIX_VEX_0F11,
@@ -3620,6 +3621,14 @@ static const struct dis386 prefix_table[][4] = {
     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
   },
 
+  /* PREFIX_0F38FC */
+  {
+    { "aadd",	{ Mdq, Gdq }, 0 },
+    { "axor",	{ Mdq, Gdq }, 0 },
+    { "aand",	{ Mdq, Gdq }, 0 },
+    { "aor",	{ Mdq, Gdq }, 0 },
+  },
+
   /* PREFIX_0F3A0F */
   {
     { Bad_Opcode },
@@ -4846,7 +4855,7 @@ static const struct dis386 three_byte_table[][256] = {
     { MOD_TABLE (MOD_0F38F9) },
     { PREFIX_TABLE (PREFIX_0F38FA) },
     { PREFIX_TABLE (PREFIX_0F38FB) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38FC) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 6e723681df..60e6d89a29 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
     "CpuMSRLIST" },
   { "CPU_AVX_NE_CONVERT_FLAGS",
     "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
+  { "CPU_RAO_INT_FLAGS",
+    "CpuRAO_INT" },
   { "CPU_IAMCU_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
   { "CPU_ADX_FLAGS",
@@ -467,6 +469,8 @@ static initializer cpu_flag_init[] =
     "CpuMSRLIST" },
   { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
     "CpuAVX_NE_CONVERT" },
+  { "CPU_ANY_RAO_INT_FLAGS",
+    "CpuRAO_INT"},
 };
 
 static initializer operand_type_init[] =
@@ -673,6 +677,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuWRMSRNS),
   BITFIELD (CpuMSRLIST),
   BITFIELD (CpuAVX_NE_CONVERT),
+  BITFIELD (CpuRAO_INT),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 78fc019c3c..b93a402f9f 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -223,6 +223,8 @@ enum
   CpuMSRLIST,
   /* Intel AVX NE CONVERT Instructions support required.  */
   CpuAVX_NE_CONVERT,
+  /* Intel RAO INT Instructions support required.  */
+  CpuRAO_INT,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
       unsigned int cpuwrmsrns:1;
       unsigned int cpumsrlist:1;
       unsigned int cpuavx_ne_convert:1;
+      unsigned int cpurao_int:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 16f59d3476..2c6e424a9a 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 
 // MSRLIST instructions end.
+
+// RAO-INT instructions.
+
+aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }+
+// RAO-INT instructions end.
-- 
2.27.0

  reply	other threads:[~2022-11-07 13:37 UTC|newest]

Thread overview: 120+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-14  9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14  9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14  9:52   ` Jan Beulich
2022-10-14 18:10     ` H.J. Lu
2022-10-16  6:39       ` Jan Beulich
2022-10-17 22:23         ` H.J. Lu
2022-10-18  5:33           ` Jan Beulich
2022-10-18 21:28             ` H.J. Lu
2022-10-19  6:01               ` Jan Beulich
2022-10-19 21:27                 ` H.J. Lu
2022-10-20  6:15                   ` Jan Beulich
2022-10-24  2:07     ` Jiang, Haochen
2022-10-24  5:53     ` Jiang, Haochen
2022-10-24 19:09       ` H.J. Lu
2022-10-25  6:29       ` Jan Beulich
2022-10-14  9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57   ` Jan Beulich
2022-10-21  3:22     ` Jiang, Haochen
2022-10-25  1:52       ` H.J. Lu
2022-10-14  9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58   ` Jan Beulich
2022-10-24  5:37     ` Kong, Lingling
2022-10-24  5:59     ` Kong, Lingling
2022-10-24 19:25       ` H.J. Lu
2022-10-25  6:44       ` Jan Beulich
2022-10-14  9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46   ` Jan Beulich
2022-10-14 18:27     ` H.J. Lu
2022-10-14 21:51       ` H.J. Lu
2022-10-16  6:34         ` Jan Beulich
2022-10-17 23:31           ` H.J. Lu
2022-10-16  6:25       ` Jan Beulich
2022-10-17 23:44         ` H.J. Lu
2022-10-16  6:19     ` Jan Beulich
2022-10-24  2:30     ` Jiang, Haochen
2022-10-24 19:12       ` H.J. Lu
2022-10-24  5:55     ` Jiang, Haochen
2022-10-25  6:53       ` Jan Beulich
2022-10-26  3:03         ` Jiang, Haochen
2022-10-26  8:49           ` Jan Beulich
2022-10-27  3:09             ` Jiang, Haochen
2022-10-27  6:37               ` Jan Beulich
2022-10-28  0:59                 ` Jiang, Haochen
2022-10-14  9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53   ` Jan Beulich
2022-10-14  9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38   ` Jan Beulich
2022-10-16  6:15     ` Jan Beulich
2022-10-24  3:12     ` Jiang, Haochen
2022-10-24 19:17       ` H.J. Lu
2022-10-24  5:56     ` Jiang, Haochen
2022-10-25  7:01       ` Jan Beulich
2022-10-26  5:16         ` Jiang, Haochen
2022-10-26  8:56           ` Jan Beulich
2022-10-27  3:50             ` Jiang, Haochen
2022-10-27  6:39               ` Jan Beulich
2022-10-27 18:46                 ` H.J. Lu
2022-10-28  6:52                   ` Jan Beulich
2022-10-28  8:10                     ` Jiang, Haochen
2022-10-28  8:22                       ` Jan Beulich
2022-10-28  8:31                         ` Jiang, Haochen
2022-10-28  8:40                           ` Jan Beulich
2022-10-28 16:08                             ` H.J. Lu
2022-10-31  9:41                               ` Jan Beulich
2022-10-31 16:49                                 ` H.J. Lu
2022-11-06 12:50         ` Kong, Lingling
2022-11-07  9:24           ` Jan Beulich
2022-11-07 13:37             ` Kong, Lingling [this message]
2022-11-07 20:03               ` H.J. Lu
2022-10-17 23:23   ` H.J. Lu
2022-10-18  5:38     ` Jan Beulich
2022-10-14  9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17  7:17   ` Jan Beulich
2022-10-24  2:52     ` Jiang, Haochen
2022-10-24  5:56     ` Jiang, Haochen
2022-10-24 19:14       ` H.J. Lu
2022-10-25  7:04       ` Jan Beulich
2022-10-14  9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17  7:20   ` Jan Beulich
2022-10-24  3:03     ` Jiang, Haochen
2022-10-24  5:56     ` Jiang, Haochen
2022-10-24 19:15       ` H.J. Lu
2022-10-25  7:07       ` Jan Beulich
2022-10-14  9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17  7:35   ` Jan Beulich
2022-10-18  9:01     ` Cui, Lili
2022-10-18  9:23       ` Jan Beulich
2022-10-18  9:33         ` Jiang, Haochen
2022-10-19 10:33         ` Cui, Lili
2022-10-19 13:35           ` Jan Beulich
2022-10-19 14:05             ` Cui, Lili
2022-10-19 14:09               ` Jan Beulich
2022-10-19 14:41                 ` Cui, Lili
2022-10-19 15:04                   ` Jan Beulich
2022-10-19 15:21                     ` Cui, Lili
2022-10-19 14:01           ` Jiang, Haochen
2022-10-19 14:13             ` Jan Beulich
2022-10-19 14:58               ` Jiang, Haochen
2022-10-25  6:02         ` Jan Beulich
2022-10-25 13:05           ` Cui, Lili
2022-10-14  9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17  8:15   ` Jan Beulich
2022-10-25 13:03     ` Cui, Lili
2022-10-25 15:41       ` Jan Beulich
2022-10-25 15:52       ` Jan Beulich
2022-10-25 17:01         ` H.J. Lu
2022-10-26 13:42           ` Cui, Lili
2022-10-26 13:53             ` Jan Beulich
2022-10-27  6:04               ` Cui, Lili
2022-10-27  6:45                 ` Jan Beulich
2022-10-27  7:01                   ` Cui, Lili
2022-10-27  7:15                     ` Jan Beulich
2022-10-27  7:43                       ` Cui, Lili
2022-10-28  9:03                       ` Cui, Lili
2022-10-28 15:54                     ` H.J. Lu
2022-10-31 13:23                       ` Cui, Lili
2022-10-31 14:45                     ` Mike Frysinger
2022-10-31 16:25                       ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang

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