From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"Hu, Lin1" <lin1.hu@intel.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 08/10] Support Intel MSRLIST
Date: Mon, 24 Oct 2022 05:56:28 +0000 [thread overview]
Message-ID: <SA1PR11MB594683D52649CCC3352C2CB8EC2E9@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <9d80838e-6b6a-339c-820d-90e3da899384@suse.com>
[-- Attachment #1: Type: text/plain, Size: 3275 bytes --]
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, October 17, 2022 3:20 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Hu, Lin1 <lin1.hu@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 08/10] Support Intel MSRLIST
>
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > From: "Hu, Lin1" <lin1.hu@intel.com>
> >
> > gas/ChangeLog:
> >
> > * NEWS: Support Intel MSRLIST.
> > * config/tc-i386.c: Add msrlist.
> > * doc/c-i386.texi: Document .msrlist and nomsrlist.
> > * testsuite/gas/i386/i386.exp: Add MSRLIST tests.
> > * testsuite/gas/i386/x86-64-lockbad-1.l: Add msrlist.
> > * testsuite/gas/i386/x86-64-lockbad-1.s: Ditto.
> > * testsuite/gas/i386/msrlist-inval.l: New test.
> > * testsuite/gas/i386/msrlist-inval.s: Ditto.
> > * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
> > * testsuite/gas/i386/x86-64-msrlist.d: Ditto.
> > * testsuite/gas/i386/x86-64-msrlist.s: Ditto.
> >
> > opcodes/ChangeLog:
> >
> > * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
> > (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
> > (prefix_table): New entry for msrlist.
> > (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
> > and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
> > * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
> > and CPU_ANY_MSRLIST_FLAGS.
> > * i386-init.h: Regenerated.
> > * i386-opc.h (CpuMSRLIST): New.
> > (i386_cpu_flags): Add cpumsrlist.
> > * i386-opc.tbl: Add MSRLIST instructions.
> > * i386-tbl.h: Regenerated.
> > ---
> > gas/NEWS | 2 +
> > gas/config/tc-i386.c | 1 +
> > gas/doc/c-i386.texi | 3 +
> > gas/testsuite/gas/i386/i386.exp | 3 +
> > gas/testsuite/gas/i386/msrlist-inval.l | 3 +
> > gas/testsuite/gas/i386/msrlist-inval.s | 7 +
> > gas/testsuite/gas/i386/x86-64-lockbad-1.l | 100 +-
> > gas/testsuite/gas/i386/x86-64-lockbad-1.s | 4 +
> > gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 14 +
> > gas/testsuite/gas/i386/x86-64-msrlist.d | 14 +
> > gas/testsuite/gas/i386/x86-64-msrlist.s | 11 +
> > opcodes/i386-dis.c | 17 +
> > opcodes/i386-gen.c | 5 +
> > opcodes/i386-init.h | 516 +-
> > opcodes/i386-opc.h | 3 +
> > opcodes/i386-opc.tbl | 7 +
> > opcodes/i386-tbl.h | 7844 +++++++++--------
> > 17 files changed, 4350 insertions(+), 4204 deletions(-) create mode
> > 100644 gas/testsuite/gas/i386/msrlist-inval.l
> > create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s
> > create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d
> > create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d
> > create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s
>
> See some of the comments to patch 7, which apply here equally.
Changes are quite same as patch 7.
In tc-i386.c, we changed ANY_MSRLIST to MSRLIST.
Removed lockbad testcases.
Removed not needed allow_index_reg.
Haochen
>
> Jan
[-- Attachment #2: 0008-Support-Intel-MSRLIST.patch --]
[-- Type: application/octet-stream, Size: 10314 bytes --]
From 3a7fa16027d024376405df57dcc892e8ea4c61b5 Mon Sep 17 00:00:00 2001
From: "Hu, Lin1" <lin1.hu@intel.com>
Date: Wed, 3 Aug 2022 16:13:07 +0800
Subject: [PATCH 8/8] Support Intel MSRLIST
gas/ChangeLog:
* NEWS: Support Intel MSRLIST.
* config/tc-i386.c: Add msrlist.
* doc/c-i386.texi: Document .msrlist.
* testsuite/gas/i386/i386.exp: Add MSRLIST tests.
* testsuite/gas/i386/msrlist-inval.l: New test.
* testsuite/gas/i386/msrlist-inval.s: Ditto.
* testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
* testsuite/gas/i386/x86-64-msrlist.d: Ditto.
* testsuite/gas/i386/x86-64-msrlist.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
(X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
(prefix_table): New entry for msrlist.
(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
and CPU_ANY_MSRLIST_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuMSRLIST): New.
(i386_cpu_flags): Add cpumsrlist.
* i386-opc.tbl: Add MSRLIST instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 2 +
gas/testsuite/gas/i386/i386.exp | 3 +
gas/testsuite/gas/i386/msrlist-inval.l | 3 +
gas/testsuite/gas/i386/msrlist-inval.s | 7 +
gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 14 +
gas/testsuite/gas/i386/x86-64-msrlist.d | 14 +
gas/testsuite/gas/i386/x86-64-msrlist.s | 10 +
opcodes/i386-dis.c | 17 +
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 516 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7872 +++++++++--------
15 files changed, 4304 insertions(+), 4172 deletions(-)
create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l
create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d
create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s
diff --git a/gas/NEWS b/gas/NEWS
index 2d745dfc31..3246e7e825 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel MSRLIST instructions.
+
* Add support for Intel WRMSRNS instructions.
* Add support for Intel RAO-INT instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 3a4790d107..dc04bbf2b4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
SUBARCH (rao_int, RAO_INT, RAO_INT, false),
SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
+ SUBARCH (msrlist, MSRLIST, MSRLIST, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 019401e8ab..20043ed76e 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -200,6 +200,7 @@ accept various extension mnemonics. For example,
@code{cmpccxadd},
@code{rao_int},
@code{wrmsrns},
+@code{msrlist},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1494,6 +1495,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.cmpccxadd} @tab @samp{.rao_int} @tab @samp{.wrmsrns}
+@item @samp{.msrlist}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index c924075180..5da64b4076 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -490,6 +490,7 @@ if [gas_32_check] then {
run_dump_test "raoint-intel"
run_dump_test "wrmsrns"
run_dump_test "wrmsrns-intel"
+ run_list_test "msrlist-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1170,6 +1171,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-wrmsrns"
run_dump_test "x86-64-wrmsrns-intel"
+ run_dump_test "x86-64-msrlist"
+ run_dump_test "x86-64-msrlist-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l
new file mode 100644
index 0000000000..456f41c38f
--- /dev/null
+++ b/gas/testsuite/gas/i386/msrlist-inval.l
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: `rdmsrlist' is only supported in 64-bit mode
+.*:7: Error: `wrmsrlist' is only supported in 64-bit mode
diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s
new file mode 100644
index 0000000000..3c3258a375
--- /dev/null
+++ b/gas/testsuite/gas/i386/msrlist-inval.s
@@ -0,0 +1,7 @@
+# Check Illegal MSRLIST instructions
+
+ .allow_index_reg
+ .text
+_start:
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d
new file mode 100644
index 0000000000..97a2a60e43
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 MSRLIST insns (Intel disassembly)
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d
new file mode 100644
index 0000000000..64beed7aa3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-msrlist.d
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw
+#name: x86_64 MSRLIST insns
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s
new file mode 100644
index 0000000000..45fb45256a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-msrlist.s
@@ -0,0 +1,10 @@
+# Check 64bit MSRLIST instructions
+
+ .text
+_start:
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
+
+.intel_syntax noprefix
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 3a60837281..29c6086a5c 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1264,6 +1264,8 @@ enum
X86_64_E9,
X86_64_EA,
X86_64_0F01_REG_0,
+ X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
+ X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
X86_64_0F01_REG_1,
X86_64_0F01_REG_1_RM_5_PREFIX_2,
X86_64_0F01_REG_1_RM_6_PREFIX_2,
@@ -2957,6 +2959,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
{
{ "wrmsrns", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
},
/* PREFIX_0F01_REG_1_RM_4 */
@@ -4295,6 +4300,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "sgdt", { M }, 0 },
},
+ /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
+ {
+ { Bad_Opcode },
+ { "wrmsrlist", { Skip_MODRM }, 0 },
+ },
+
+ /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
+ {
+ { Bad_Opcode },
+ { "rdmsrlist", { Skip_MODRM }, 0 },
+ },
+
/* X86_64_0F01_REG_1 */
{
{ "sidt{Q|Q}", { M }, 0 },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 5428278d7e..8e2f8b5e06 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -257,6 +257,8 @@ static initializer cpu_flag_init[] =
"CpuRAO_INT" },
{ "CPU_WRMSRNS_FLAGS",
"CpuWRMSRNS" },
+ { "CPU_MSRLIST_FLAGS",
+ "CpuMSRLIST" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -463,6 +465,8 @@ static initializer cpu_flag_init[] =
"CpuRAO_INT" },
{ "CPU_ANY_WRMSRNS_FLAGS",
"CpuWRMSRNS" },
+ { "CPU_ANY_MSRLIST_FLAGS",
+ "CpuMSRLIST" },
};
static initializer operand_type_init[] =
@@ -670,6 +674,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuRAO_INT),
BITFIELD (CpuWRMSRNS),
+ BITFIELD (CpuMSRLIST),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 39229b3be6..77a82d5afe 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -221,6 +221,8 @@ enum
CpuRAO_INT,
/* Intel WRMSRNS Instructions support required */
CpuWRMSRNS,
+ /* Intel MSRLIST Instructions support required. */
+ CpuMSRLIST,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -406,6 +408,7 @@ typedef union i386_cpu_flags
unsigned int cpucmpccxadd:1;
unsigned int cpurao_int:1;
unsigned int cpuwrmsrns:1;
+ unsigned int cpumsrlist:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index d142670037..dc22eb5028 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3313,3 +3313,10 @@ axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_
wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// WRMSRNS instruction end.
+
+// MSRLIST instructions.
+
+rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// MSRLIST instructions end.
--
2.18.1
next prev parent reply other threads:[~2022-10-24 5:56 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen [this message]
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
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