From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Cui, Lili" <lili.cui@intel.com>, "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 09/10] Support Intel AMX-FP16
Date: Wed, 19 Oct 2022 14:01:29 +0000 [thread overview]
Message-ID: <SA1PR11MB59468349423789B526535F9FEC2B9@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <SJ0PR11MB56006575107C5BD2C5427A8C9E2B9@SJ0PR11MB5600.namprd11.prod.outlook.com>
> -----Original Message-----
> From: Cui, Lili <lili.cui@intel.com>
> Sent: Wednesday, October 19, 2022 6:34 PM
> To: Beulich, Jan <JBeulich@suse.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Jiang, Haochen
> <haochen.jiang@intel.com>
> Subject: RE: [PATCH 09/10] Support Intel AMX-FP16
>
> > >>> - "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16" },
> > >>> + "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16|CpuAMX_FP16" },
> > >>> { "CPU_ANY_MSRLIST_FLAGS",
> > >>> "CpuMSRLIST" },
> > >>> + { "CPU_ANY_AMX_FP16_FLAGS",
> > >>> + "CpuAMX_FP16" },
> > >>> };
> > >>
> > >> Same here then.
> > > Done.
> >
> > I guess my comment here was a little misleading (I'm sorry for that),
> > in that in addition I was expecting you to consider the comment
> > regarding the need for the *_ANY_* constants that I did give for several of the
> patches in this series.
> > I think the question applies here as well: Are there dependent
> > features known to appear? If not, there's no need for the extra constant.
> >
> Get you, there are no known dependencies now, and I will pay attention on it in
> future ISAs.
But I suppose for AMX-FP16, the possibility of potential dependency is bigger than
some like CMPCCXADD, MSRLIST. Since FP16 type is not that rare.
I prefer to keep the ANY there. BTW, I have just revised all of patches according to
review and will send out very soon.
BRs,
Haochen
>
> > > --- a/gas/config/tc-i386.c
> > > +++ b/gas/config/tc-i386.c
> > > @@ -1101,6 +1101,7 @@ static const arch_entry cpu_arch[] =
> > > SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> > > SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
> > > SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
> > > + SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
> > > };
> >
> > This might also benefit from moving up, but I'm not going to insist.
> Done, I missed this place.
>
> >
> > There are no @code{no...} entries here anymore, as of earlier today.
> > Hence no new ones should appear (and you need to re-base in any event).
> Rebased, thanks Jan.
>
>
> gas/
>
> * NEWS: Add support for Intel AMX-FP16 instruction.
> * config/tc-i386.c: Add amx_fp16.
> * doc/c-i386.texi: Document .amx_fp16.
> * testsuite/gas/i386/i386.exp: Add AMX-FP16 tests.
> * testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test.
> * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise.
> * testsuite/gas/i386/x86-64-amx-fp16.s: Likewise.
> * testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise.
> * testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise.
>
> opcodes/
>
> * i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New.
> (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise.
> (VEX_W_0F385C_X86_64_P_3): Likewise.
> (prefix_table): Add VEX_W_0F385C_X86_64_P_3.
> (vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0.
> (vex_w_table): Add VEX_W_0F385C_X86_64_P_3.
> (mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0.
> * i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS and
> CPU_ANY_AMX-FP16_FLAGS.
> (CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16.
> (cpu_flags): Add CpuAMX-FP16.
> * i386-opc.h (enum): Add CpuAMX-FP16.
> (i386_cpu_flags): Add cpuamx_fp16.
> * i386-opc.tbl: Add Intel AMX-FP16 instruction.
> * i386-init.h: Regenerate.
> * i386-tbl.h: Likewise.
> ---
> gas/NEWS | 2 ++
> gas/config/tc-i386.c | 1 +
> gas/doc/c-i386.texi | 3 +-
> gas/testsuite/gas/i386/i386.exp | 3 ++
> gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d | 19 ++++++++++
> gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s | 35 +++++++++++++++++++
> .../gas/i386/x86-64-amx-fp16-intel.d | 13 +++++++
> gas/testsuite/gas/i386/x86-64-amx-fp16.d | 13 +++++++
> gas/testsuite/gas/i386/x86-64-amx-fp16.s | 9 +++++
> opcodes/i386-dis.c | 18 ++++++++++
> opcodes/i386-gen.c | 7 +++-
> opcodes/i386-opc.h | 3 ++
> opcodes/i386-opc.tbl | 1 +
> 13 files changed, 125 insertions(+), 2 deletions(-) create mode 100644
> gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16.s
>
> diff --git a/gas/NEWS b/gas/NEWS
> index 3246e7e825..961449545d 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for Intel AMX-FP16 instructions.
> +
> * Add support for Intel MSRLIST instructions.
>
> * Add support for Intel WRMSRNS instructions.
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index
> c9432e4188..906e9db9ad 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1076,6 +1076,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
> SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
> SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
> + SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
> SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
> SUBARCH (movdiri, MOVDIRI, ANY_MOVDIRI, false),
> SUBARCH (movdir64b, MOVDIR64B, ANY_MOVDIR64B, false), diff --git
> a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 49582b29a6..b739d5f32e
> 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -203,6 +203,7 @@ accept various extension mnemonics. For example,
> @code{msrlist}, @code{amx_int8}, @code{amx_bf16},
> +@code{amx_fp16},
> @code{amx_tile},
> @code{vmx},
> @code{vmfunc},
> @@ -1499,7 +1500,7 @@ supported on the CPU specified. The choices for
> @var{cpu_type} are:
> @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg}
> @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab
> @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab
> @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} -@item
> @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
> +@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
> @tab
> +@samp{.amx_tile}
> @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab
> @samp{.hreset} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab
> @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab
> @samp{.rdtscp} @tab @samp{.svme} diff --git
> a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index
> 5da64b4076..9f5fa7f612 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -1173,6 +1173,9 @@ if [gas_64_check] then {
> run_dump_test "x86-64-wrmsrns-intel"
> run_dump_test "x86-64-msrlist"
> run_dump_test "x86-64-msrlist-intel"
> + run_dump_test "x86-64-amx-fp16"
> + run_dump_test "x86-64-amx-fp16-intel"
> + run_dump_test "x86-64-amx-fp16-bad"
> run_dump_test "x86-64-clzero"
> run_dump_test "x86-64-mwaitx-bdver4"
> run_list_test "x86-64-mwaitx-reg"
> diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
> b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
> new file mode 100644
> index 0000000000..a53ebf486d
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
> @@ -0,0 +1,19 @@
> +#as:
> +#objdump: -drw
> +#name: x86_64 Illegal AMX-FP16 insns
> +#source: x86-64-amx-fp16-bad.s
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> +[ ]*[a-f0-9]+:[ ]*c4 e2 d3 5c[ ]*\(bad\)[ ]*
> +[ ]*[a-f0-9]+:[ ]*dc 90 90 90 90 90[ ]*fcoml.*
> +[ ]*[a-f0-9]+:[ ]*c4 e2 57 5c[ ]*\(bad\)[ ]*
> +[ ]*[a-f0-9]+:[ ]*dc 90 90 90 90 90[ ]*fcoml.*
> +[ ]*[a-f0-9]+:[ ]*c4 62 53 5c dc[
> ]*tdpfp16ps %tmm5,%tmm4,\(bad\)
> +[ ]*[a-f0-9]+:[ ]*c4 c2 53 5c dc[
> ]*tdpfp16ps %tmm5,\(bad\),%tmm3
> +[ ]*[a-f0-9]+:[ ]*c4 e2 33 5c dc[ ]*tdpfp16ps
> \(bad\),%tmm4,%tmm3
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
> b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
> new file mode 100644
> index 0000000000..da5be1086e
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
> @@ -0,0 +1,35 @@
> +# Check Illegal 64bit AMX-FP16 instructions
> +
> +.text
> + #tdpfp16ps %tmm5,%tmm4,%tmm3 set VEX.W = 1 (illegal value).
> + .byte 0xc4
> + .byte 0xe2
> + .byte 0xd3
> + .byte 0x5c
> + .byte 0xdc
> + .fill 0x05, 0x01, 0x90
> + #tdpfp16ps %tmm5,%tmm4,%tmm3 set VEX.L = 1 (illegal value).
> + .byte 0xc4
> + .byte 0xe2
> + .byte 0x57
> + .byte 0x5c
> + .byte 0xdc
> + .fill 0x05, 0x01, 0x90
> + #tdpfp16ps %tmm5,%tmm4,%tmm3 set VEX.R = 0 (illegal value).
> + .byte 0xc4
> + .byte 0x62
> + .byte 0x53
> + .byte 0x5c
> + .byte 0xdc
> + #tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.B = 0 (illegal value).
> + .byte 0xc4
> + .byte 0xc2
> + .byte 0x53
> + .byte 0x5c
> + .byte 0xdc
> + #tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.VVVV = 0110 (illegal value).
> + .byte 0xc4
> + .byte 0xe2
> + .byte 0x33
> + .byte 0x5c
> + .byte 0xdc
> diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
> b/gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
> new file mode 100644
> index 0000000000..497898b760
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
> @@ -0,0 +1,13 @@
> +#as:
> +#objdump: -d -Mintel
> +#name: x86_64 AMX-FP16 insns (Intel disassembly)
> +#source: x86-64-amx-fp16.s
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[ ]*tdpfp16ps
> tmm3,tmm4,tmm5
> +[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[ ]*tdpfp16ps
> tmm3,tmm4,tmm5
> diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16.d
> b/gas/testsuite/gas/i386/x86-64-amx-fp16.d
> new file mode 100644
> index 0000000000..7d3af95a4d
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-fp16.d
> @@ -0,0 +1,13 @@
> +#as:
> +#objdump: -dw
> +#name: x86_64 AMX-FP16 insns
> +#source: x86-64-amx-fp16.s
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[
> ]*tdpfp16ps %tmm5,%tmm4,%tmm3
> +[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[
> ]*tdpfp16ps %tmm5,%tmm4,%tmm3
> diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16.s
> b/gas/testsuite/gas/i386/x86-64-amx-fp16.s
> new file mode 100644
> index 0000000000..5a007904ed
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-fp16.s
> @@ -0,0 +1,9 @@
> +# Check 64bit AMX-FP16 instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + tdpfp16ps %tmm5, %tmm4, %tmm3
> +
> +.intel_syntax noprefix
> + tdpfp16ps tmm3, tmm4, tmm5
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index
> 0aa41bd5fb..60712c7c5b 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -933,6 +933,7 @@ enum
> MOD_VEX_0F384B_X86_64_P_3_W_0,
> MOD_VEX_0F385A,
> MOD_VEX_0F385C_X86_64_P_1_W_0,
> + MOD_VEX_0F385C_X86_64_P_3_W_0,
> MOD_VEX_0F385E_X86_64_P_0_W_0,
> MOD_VEX_0F385E_X86_64_P_1_W_0,
> MOD_VEX_0F385E_X86_64_P_2_W_0,
> @@ -1399,6 +1400,7 @@ enum
> VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
> VEX_LEN_0F385A_M_0,
> VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
> + VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
> VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
> VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
> VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
> @@ -1565,6 +1567,7 @@ enum
> VEX_W_0F3859,
> VEX_W_0F385A_M_0_L_0,
> VEX_W_0F385C_X86_64_P_1,
> + VEX_W_0F385C_X86_64_P_3,
> VEX_W_0F385E_X86_64_P_0,
> VEX_W_0F385E_X86_64_P_1,
> VEX_W_0F385E_X86_64_P_2,
> @@ -4088,6 +4091,7 @@ static const struct dis386 prefix_table[][4] = {
> { Bad_Opcode },
> { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
> { Bad_Opcode },
> + { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
> },
>
> /* PREFIX_VEX_0F385E_X86_64 */
> @@ -7120,6 +7124,11 @@ static const struct dis386 vex_len_table[][2] = {
> { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
> },
>
> + /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */ {
> + { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 }, },
> +
> /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
> {
> { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, @@ -7788,6 +7797,10 @@ static
> const struct dis386 vex_w_table[][2] = {
> /* VEX_W_0F385C_X86_64_P_1 */
> { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
> },
> + {
> + /* VEX_W_0F385C_X86_64_P_3 */
> + { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) }, },
> {
> /* VEX_W_0F385E_X86_64_P_0 */
> { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, @@ -8610,6
> +8623,11 @@ static const struct dis386 mod_table[][2] = {
> { Bad_Opcode },
> { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
> },
> + {
> + /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
> + { Bad_Opcode },
> + { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) }, },
> {
> /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
> { Bad_Opcode },
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index
> 435d67711f..86383ba793 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -319,6 +319,8 @@ static initializer cpu_flag_init[] =
> "CPU_AMX_TILE_FLAGS|CpuAMX_INT8" },
> { "CPU_AMX_BF16_FLAGS",
> "CPU_AMX_TILE_FLAGS|CpuAMX_BF16" },
> + { "CPU_AMX_FP16_FLAGS",
> + "CPU_AMX_TILE_FLAGS|CpuAMX_FP16" },
> { "CPU_AMX_TILE_FLAGS",
> "CpuAMX_TILE" },
> { "CPU_MOVDIRI_FLAGS",
> @@ -425,8 +427,10 @@ static initializer cpu_flag_init[] =
> "CpuAMX_INT8" },
> { "CPU_ANY_AMX_BF16_FLAGS",
> "CpuAMX_BF16" },
> + { "CPU_ANY_AMX_FP16_FLAGS",
> + "CpuAMX_FP16" },
> { "CPU_ANY_AMX_TILE_FLAGS",
> - "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16" },
> + "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16|CpuAMX_FP16" },
> { "CPU_ANY_AVX_VNNI_FLAGS",
> "CpuAVX_VNNI" },
> { "CPU_ANY_MOVDIRI_FLAGS",
> @@ -692,6 +696,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuCLDEMOTE),
> BITFIELD (CpuAMX_INT8),
> BITFIELD (CpuAMX_BF16),
> + BITFIELD (CpuAMX_FP16),
> BITFIELD (CpuAMX_TILE),
> BITFIELD (CpuMOVDIRI),
> BITFIELD (CpuMOVDIR64B),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index
> 75c23aaec6..b548769d75 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -240,6 +240,8 @@ enum
> CpuAMX_INT8,
> /* AMX-BF16 instructions required */
> CpuAMX_BF16,
> + /* AMX-FP16 instructions required */
> + CpuAMX_FP16,
> /* AMX-TILE instructions required */
> CpuAMX_TILE,
> /* GFNI instructions required */
> @@ -418,6 +420,7 @@ typedef union i386_cpu_flags
> unsigned int cpushstk:1;
> unsigned int cpuamx_int8:1;
> unsigned int cpuamx_bf16:1;
> + unsigned int cpuamx_fp16:1;
> unsigned int cpuamx_tile:1;
> unsigned int cpugfni:1;
> unsigned int cpuvaes:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index
> 42d6423942..6057664193 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3113,6 +3113,7 @@ ldtilecfg, 0x49, None, CpuAMX_TILE|Cpu64,
> Modrm|Vex128|Space0F38|VexW0|No_bSuf|N
> sttilecfg, 0x6649, None, CpuAMX_TILE|Cpu64,
> Modrm|Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_
> qSuf|No_ldSuf, { Unspecified|BaseIndex }
>
> tdpbf16ps, 0xf35c, None, CpuAMX_BF16|Cpu64,
> Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_w
> Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
> +tdpfp16ps, 0xf25c, None, CpuAMX_FP16|Cpu64,
> +Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|No_bSuf|No_wS
> uf|No_lSu
> +f|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
> tdpbssd, 0xf25e, None, CpuAMX_INT8|Cpu64,
> Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_w
> Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
> tdpbuud, 0x5e, None, CpuAMX_INT8|Cpu64,
> Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_w
> Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
> tdpbusd, 0x665e, None, CpuAMX_INT8|Cpu64,
> Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_w
> Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
> --
> 2.17.1
>
> Thanks,
> Lili.
next prev parent reply other threads:[~2022-10-19 14:02 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen [this message]
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=SA1PR11MB59468349423789B526535F9FEC2B9@SA1PR11MB5946.namprd11.prod.outlook.com \
--to=haochen.jiang@intel.com \
--cc=JBeulich@suse.com \
--cc=binutils@sourceware.org \
--cc=hjl.tools@gmail.com \
--cc=lili.cui@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).