From: "H.J. Lu" <hjl.tools@gmail.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "Beulich, Jan" <JBeulich@suse.com>,
"Kong, Lingling" <lingling.kong@intel.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 06/10] Support Intel RAO-INT
Date: Mon, 24 Oct 2022 12:17:27 -0700 [thread overview]
Message-ID: <CAMe9rOpibkg6swN40jzeFWaUkQiM+ymm+Dv+kx3sz1A5HoTrVQ@mail.gmail.com> (raw)
In-Reply-To: <SA1PR11MB5946F3611F651B6AC8DB57A6EC2E9@SA1PR11MB5946.namprd11.prod.outlook.com>
On Sun, Oct 23, 2022 at 8:12 PM Jiang, Haochen <haochen.jiang@intel.com> wrote:
>
> > -----Original Message-----
> > From: Jan Beulich <jbeulich@suse.com>
> > Sent: Friday, October 14, 2022 10:38 PM
> > To: Jiang, Haochen <haochen.jiang@intel.com>
> > Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> > binutils@sourceware.org
> > Subject: Re: [PATCH 06/10] Support Intel RAO-INT
> >
> > On 14.10.2022 11:12, Haochen Jiang wrote:
> > > --- a/gas/config/tc-i386.c
> > > +++ b/gas/config/tc-i386.c
> > > @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
> > > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> > > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> > > SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT,
> > > false),
> > > - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> > > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), SUBARCH
> > > + (raoint, RAOINT, ANY_RAOINT, false),
> >
> > As for the earlier patch - likely no need for ANY_RAOINT. Also please have the
> > earlier patch add the comma so you don't need to touch that line again here
> > (helping at least "git blame").
>
> Done and fixed for CMPccXADD patch.
Please also remove CPU_ANY_RAO_INT_FLAGS since it isn't used.
>
> >
> > > --- a/opcodes/i386-dis.c
> > > +++ b/opcodes/i386-dis.c
> > > @@ -887,6 +887,7 @@ enum
> > > MOD_0F38F9,
> > > MOD_0F38FA_PREFIX_1,
> > > MOD_0F38FB_PREFIX_1,
> > > + MOD_0F38FC,
> > > MOD_0F3A0F_PREFIX_1,
> > >
> > > MOD_VEX_0F12_PREFIX_0,
> > > @@ -1086,6 +1087,7 @@ enum
> > > PREFIX_0F38F8,
> > > PREFIX_0F38FA,
> > > PREFIX_0F38FB,
> > > + PREFIX_0F38FC,
> >
> > PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However, like in
> > the earlier patch - if you used Mdq below, you could avoid going through
> > mod_table[] altogether.
>
> Removed pass modrm table since Edq seems also judges modrm.
>
> >
> > > @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
> > > { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
> > > },
> > >
> > > + /* PREFIX_0F38FC */
> > > + {
> > > + { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
> > > + { "axor", { Edq, Gdq }, PREFIX_OPCODE },
> > > + { "aand", { Edq, Gdq }, PREFIX_OPCODE },
> > > + { "aor", { Edq, Gdq }, PREFIX_OPCODE },
> > > + },
> >
> > Once having gone through prefix_table[], PREFIX_OPCODE (and
> > PREFIX_DATA) are meaningless iirc and should hence be omitted.
> >
>
> Fixed.
>
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64,
> > > Modrm|Vex128|Space0F38|VexVVVV=1|Swa
> > > cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64,
> > >
> > Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|
> > No_w
> > > Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64,
> > > Dword|Qword|Unspecified|BaseIndex }
> > >
> > > // CMPCCXADD instructions end.
> > > +
> > > +// RAOINT instructions.
> >
> > Nit: Better RAO-INT, like in the title?
>
> Done.
>
> >
> > > +aadd, 0xf38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> > > +aand, 0x660f38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> > > +aor, 0xf20f38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> > > +axor, 0xf30f38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> >
> > Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
> > enough for Intel syntax memory operands - please double check; if not this will
> > need fixing).
> >
>
> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf since
> the suffixes are not required.
>
> In future, if suffixes are not required, we will add all the No_xxSuf.
>
> BTW, can we write a macro named No_allSuf including all of them to shorten
> the line?
>
> Haochen
> > Jan
--
H.J.
next prev parent reply other threads:[~2022-10-24 19:18 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu [this message]
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
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