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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches
Date: Wed, 19 Apr 2023 16:22:57 +0000 (GMT) [thread overview]
Message-ID: <20230419162257.677393858D33@sourceware.org> (raw)
https://gcc.gnu.org/g:f26f6724ef0f75cfebc84434f4c1fbfbd0ff2154
commit f26f6724ef0f75cfebc84434f4c1fbfbd0ff2154
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 12:22:53 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 139 ++-------------------
| 24 ----
| 44 -------
| 37 ------
| 40 ------
| 37 ------
6 files changed, 7 insertions(+), 314 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e3466f3aa74..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -241,17 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Constraint to use for floating point types that a direct conversion
-;; from 64-bit integer to floating point.
-(define_mode_attr FL_CONSTRAINT [(SF "wa")
- (DF "wa")
- (KF "v")
- (TF "v")])
-
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO [(float "SIGN")
- (unsigned_float "ZERO")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3941,126 +3930,13 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V4SI element from memory with constant element number.
-(define_insn_and_split "*vsx_extract_v4si_load"
- [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 4))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to DImode with zero or sign extension.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number and
-;; convert it to DImode with zero extension.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,v,v")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "YZ,m,Z,Q")
- (parallel
- [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
-
-;; Extract a V8HI element from memory with constant element number and
-;; convert it to DImode with sign extension.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "YZ,m")
- (parallel
- [(match_operand:QI 2 "const_0_to_7_operand" "0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
-;; unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>")
- (any_float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<FL_CONSTRAINT>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (any_float:FL_CONV (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO>_EXTEND (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4069,9 +3945,8 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index e57dd0e8bb9..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsb\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 209ca926b97..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode directly into vector registers. */
-
-#include <altivec.h>
-
-void
-extract_sign_v4si_0 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_sign_v4si_1 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_v4si_1 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlfiw[az]x\M|\mlxsiw[az]x\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index bf135789bf8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index edaa2ccc9bf..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, double, and _Float128 by loading the
- value directly into a vector register, and not loading up the GPRs
- first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-_Float128
-extract_ieee_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index a2c482f556e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lha, no extsh. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lha, no extsh. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lhz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lhz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
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