[gcc(refs/users/meissner/heads/work119)] Revert patches

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:5a759794517862efcfa7ac6a5b18afdb6e16bd5e

commit 5a759794517862efcfa7ac6a5b18afdb6e16bd5e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 26 11:35:06 2023 -0400

    Revert patches

Diff:
---
 gcc/config/rs6000/vsx.md                           | 66 ----------------------
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     | 31 ----------
 .../gcc.target/powerpc/vec-extract-mem-short-3.c   | 19 -------
 3 files changed, 116 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4a93523090a..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,72 +4107,6 @@
   [(set_attr "type" "load,fpload")
    (set_attr "isa" "*,<VSX_EX_ISA>")])
 
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
-	(any_extend:DI
-	 (unspec:SI
-	  [(match_operand:V4SI 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(any_extend:DI (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   SImode);
-}
-  [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
-	(zero_extend:GPR
-	 (unspec:<VSX_EXTRACT_I2:MODE>
-	  [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(zero_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VSX_EXTRACT_I2:MODE>mode);
-}
-  [(set_attr "type" "load,fpload")
-   (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(sign_extend:GPR
-	 (unspec:HI
-	  [(match_operand:V8HI 1 "memory_operand" "Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(sign_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   HImode);
-}
-  [(set_attr "type" "load")])
-
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f6b027db3bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
-   SImode and fold both zero and sign extension into the load.  Both uses
-   generate a rldicl to clear the bits in the variable element number, but this
-   test verifies that there is no rldicl after the lwzx to do the zero
-   extension.  */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
-  return vec_extract (*p, n);	/* lwax, no extsw.  */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
-  return vec_extract (*p, n);	/* lwzx, no extra rldicl.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M}   2 } } */
-/* { dg-final { scan-assembler-not   {\mlw[az]\M}   } } */
-/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index a1d3947fabb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
-   HImode and fold sign extension into the load.  */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
-  return vec_extract (*p, n);		/* lwax, no extsw.  */
-}
-
-/* { dg-final { scan-assembler     {\mlhax\M}   } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M}  } } */