[gcc(refs/users/meissner/heads/work119)] Revert patches

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:5da57dff3157bed9513718a9a2fe9e41d3764a49

commit 5da57dff3157bed9513718a9a2fe9e41d3764a49
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 19 15:21:31 2023 -0400

    Revert patches

Diff:
---
 gcc/config/rs6000/rs6000.cc | 56 ++++++++++++++-------------------------------
 gcc/config/rs6000/vsx.md    | 29 ++++++++---------------
 2 files changed, 26 insertions(+), 59 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (CONST_INT_P (element))
     return GEN_INT (INTVAL (element) * scalar_size);
 
-  if (GET_CODE (base_tmp) == SCRATCH)
-    base_tmp = gen_reg_rtx (Pmode);
-
-  /* After register allocation, all insns should use the 'Q' constraint
-     (address is a single register) if the element number is not a
-     constant.  */
-  gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+  /* All insns should use the 'Q' constraint (address is a single register) if
+     the element number is not a constant.  */
+  gcc_assert (satisfies_constraint_Q (mem));
 
   /* Mask the element to make sure the element number is between 0 and the
      maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (shift > 0)
     {
       rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
-      if (can_create_pseudo_p ())
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_insn (gen_rtx_SET (base_tmp, shift_op));
     }
 
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
 
       else
 	{
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_move_insn (base_tmp, addr);
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
    that is valid for reads or writes to a given register (SCALAR_REG).
 
-   The temporary BASE_TMP might be set multiple times with this code if this is
-   called after register allocation.  */
+   This function is expected to be called after reload is completed when we are
+   splitting insns.  The temporary BASE_TMP might be set multiple times with
+   this code.  */
 
 rtx
 rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
   rtx addr = XEXP (mem, 0);
   rtx new_addr;
 
-  if (GET_CODE (base_tmp) != SCRATCH)
-    {
-      gcc_assert (!reg_mentioned_p (base_tmp, addr));
-      gcc_assert (!reg_mentioned_p (base_tmp, element));
-    }
+  gcc_assert (!reg_mentioned_p (base_tmp, addr));
+  gcc_assert (!reg_mentioned_p (base_tmp, element));
 
   /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY.  */
   gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 	     offset, it has the benefit that if D-FORM instructions are
 	     allowed, the offset is part of the memory access to the vector
 	     element. */
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 
   else
     {
-      if (GET_CODE (base_tmp) == SCRATCH)
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_move_insn (base_tmp, addr);
       new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
     }
 
-    /* If register allocation has been done and the address isn't valid, move
-       the address into the temporary base register.  Some reasons it could not
-       be valid include:
+    /* If the address isn't valid, move the address into the temporary base
+       register.  Some reasons it could not be valid include:
 
        The address offset overflowed the 16 or 34 bit offset size;
        We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
        We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
        Only X_FORM loads can be done, and the address is D_FORM.  */
 
-  if (!can_create_pseudo_p ())
-    {
-      enum insn_form iform
-	= address_to_insn_form (new_addr, scalar_mode,
-				reg_to_non_prefixed (scalar_reg, scalar_mode));
+  enum insn_form iform
+    = address_to_insn_form (new_addr, scalar_mode,
+			    reg_to_non_prefixed (scalar_reg, scalar_mode));
 
-      if (iform == INSN_FORM_BAD)
-	{
-	  emit_move_insn (base_tmp, new_addr);
-	  new_addr = base_tmp;
-	}
+  if (iform == INSN_FORM_BAD)
+    {
+      emit_move_insn (base_tmp, new_addr);
+      new_addr = base_tmp;
     }
 
   return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c3b870640ed..0e681844243 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
-			      (V8HI "p9v")
-			      (V4SI "p8v")])
-
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -3957,28 +3951,23 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
-;; If the element number is 0, we don't need to do a load immediate operation.
-;; Likewise for GPRs with offsettable loads, we can fold the offset into the
-;; address.  For vector registers, we are limited to X-FORM memory addresses.
-;; PowerPC64 is needed because we need a DI temporary base register.
+;; Optimize extracting a single scalar element from memory.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
-  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+   (clobber (match_scratch:DI 3 "=&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& 1"
+  "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "4,4,8,4,8")
-   (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"