[gcc(refs/users/meissner/heads/work119)] Revert patches

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:a1f248363949c5533957524329b5a600f06c1dac

commit a1f248363949c5533957524329b5a600f06c1dac
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 11:36:14 2023 -0400

    Revert patches

Diff:
---
 gcc/config/rs6000/vsx.md                           | 30 ----------------------
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     |  5 +---
 .../gcc.target/powerpc/vec-extract-mem-int-4.c     | 27 -------------------
 3 files changed, 1 insertion(+), 61 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 457513a4eaa..3364a0791c2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4214,36 +4214,6 @@
    (set_attr "length" "12,16,16,20")
    (set_attr "isa" "*,*,p9v,p9v")])
 
-;; Extract a V4SI element from memory with variable element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
-  [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
-	(any_float:SFDF
-	 (unspec:SI
-	  [(match_operand:V4SI 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))
-   (clobber (match_scratch:DI 4 "=f,v"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
-  "#"
-  "&& 1"
-  [(set (match_dup 4)
-	(match_dup 5))
-   (set (match_dup 0)
-	(float:SFDF (match_dup 4)))]
-{
-  if (GET_CODE (operands[4]) == SCRATCH)
-    operands[4] = gen_reg_rtx (DImode);
-
-  rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
-					   operands[3], SImode);
-  operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
-  [(set_attr "type" "fpload")
-   (set_attr "length" "20")
-   (set_attr "isa" "*,p8v")])
-
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index 17db9bbe107..437001a6177 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -22,8 +22,5 @@ extract_uns_v4si_var (vector unsigned int *p, size_t n)
 
 /* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
 /* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
-/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
-
-/* There are 2 rldicl's to make the variable element number, but there is not a
-   third one to do the zero extension.  */
 /* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 415dee36d8a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
-   SImode and convert the value to float, and double by loading the value
-   directly into a vector register, and not loading up the GPRs first.  */
-
-#include <altivec.h>
-#include <stddef.h>
-
-float
-extract_float_sign_v4si_var (vector int *p, size_t n)
-{
-  return vec_extract (*p, n);		/* lfiwax or lxsiwax.  */
-}
-
-double
-extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
-{
-  return vec_extract (*p, n);		/* lfiwzx or lxsiwzx.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M}  1 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M}  1 } } */
-/* { dg-final { scan-assembler-not   {\mlw[az]\M}                } } */
-/* { dg-final { scan-assembler-not   {\mmtvsrw[sz]\M}            } } */