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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches
Date: Fri, 21 Apr 2023 03:45:14 +0000 (GMT) [thread overview]
Message-ID: <20230421034514.271023858D37@sourceware.org> (raw)
https://gcc.gnu.org/g:f28af2061dadc51d25e9eab33226ce214226f194
commit f28af2061dadc51d25e9eab33226ce214226f194
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 23:45:10 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 204 +--------------------
| 22 ---
| 17 --
| 37 ----
| 38 ----
| 26 ---
| 37 ----
| 26 ---
8 files changed, 6 insertions(+), 401 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 778d067e533..63f31980806 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,10 +207,6 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
-;; Iterator for vector extract/insert of small integer vectors that can be sign
-;; extended with the load.
-(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
-
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -251,10 +247,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
- (unsigned_float "ZERO_EXTEND")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3637,24 +3629,6 @@
}
[(set_attr "type" "fpload,load")])
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -4007,101 +3981,6 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a constant element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
- (any_extend:SI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")
- (set_attr "isa" "*,p8v")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4124,92 +4003,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI/V4SI element from memory with a variable element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,8,12")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a variable element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
- (any_extend:SI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,8,12")
- (set_attr "isa" "*,*,p9v,p9v")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index a392e4322bb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index ee6fb79993a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- QImode and fold the zero extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-unsigned long long
-extract_uns_var_v16qi (vector unsigned char *p, size_t n)
-{
- return vec_extract (*p, n); /* lbzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e81ab4954ae..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 91e85bf5a5b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-float
-extract_float_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-double
-extract_double_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f89eb617770..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 3c834a77948..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index efb5447f11b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_var (vector unsigned short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlhzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
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