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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches
Date: Fri, 21 Apr 2023 23:05:23 +0000 (GMT) [thread overview]
Message-ID: <20230421230523.5A0DE3858D20@sourceware.org> (raw)
https://gcc.gnu.org/g:7c4f1f61b3521c4050ff8c0d85fadbfd8adea8aa
commit 7c4f1f61b3521c4050ff8c0d85fadbfd8adea8aa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 19:05:19 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 +++++++-------------
gcc/config/rs6000/vsx.md | 59 ++++------------------
| 31 ------------
| 24 ---------
4 files changed, 26 insertions(+), 144 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1141e7b9fa7..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,45 +3549,23 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory convert to DFmode with constant element number. If
-;; the element number is 0, we don't need a temporary register.
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q")
- (parallel
- [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))
- (clobber (match_scratch:P 3 "=X,&b,X,&b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,fpload,load,load")
- (set_attr "length" "4,8,4,8")])
-
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=wa,wa")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:P 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3616,7 +3594,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 34ebc574339..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-
-void
-extract_float_0_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-void
-extract_float_1_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
-/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 65107ee0c74..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_float_0_gpr (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
-/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
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