[gcc(refs/users/meissner/heads/work119)] Revert patches

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:3f1c236b90f69acda6ba4dcabe07d60ff407a7f4

commit 3f1c236b90f69acda6ba4dcabe07d60ff407a7f4
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 24 21:51:19 2023 -0400

    Revert patches

Diff:
---
 gcc/config/rs6000/rs6000.cc                        | 56 ++++---------
 gcc/config/rs6000/vsx.md                           | 91 ++--------------------
 .../gcc.target/powerpc/vec-extract-mem-char-1.c    | 35 ---------
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     | 35 ---------
 .../gcc.target/powerpc/vec-extract-mem-int-2.c     | 63 ---------------
 .../gcc.target/powerpc/vec-extract-mem-short-1.c   | 35 ---------
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   | 36 ---------
 7 files changed, 24 insertions(+), 327 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (CONST_INT_P (element))
     return GEN_INT (INTVAL (element) * scalar_size);
 
-  if (GET_CODE (base_tmp) == SCRATCH)
-    base_tmp = gen_reg_rtx (Pmode);
-
-  /* After register allocation, all insns should use the 'Q' constraint
-     (address is a single register) if the element number is not a
-     constant.  */
-  gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+  /* All insns should use the 'Q' constraint (address is a single register) if
+     the element number is not a constant.  */
+  gcc_assert (satisfies_constraint_Q (mem));
 
   /* Mask the element to make sure the element number is between 0 and the
      maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (shift > 0)
     {
       rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
-      if (can_create_pseudo_p ())
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_insn (gen_rtx_SET (base_tmp, shift_op));
     }
 
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
 
       else
 	{
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_move_insn (base_tmp, addr);
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
    that is valid for reads or writes to a given register (SCALAR_REG).
 
-   The temporary BASE_TMP might be set multiple times with this code if this is
-   called after register allocation.  */
+   This function is expected to be called after reload is completed when we are
+   splitting insns.  The temporary BASE_TMP might be set multiple times with
+   this code.  */
 
 rtx
 rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
   rtx addr = XEXP (mem, 0);
   rtx new_addr;
 
-  if (GET_CODE (base_tmp) != SCRATCH)
-    {
-      gcc_assert (!reg_mentioned_p (base_tmp, addr));
-      gcc_assert (!reg_mentioned_p (base_tmp, element));
-    }
+  gcc_assert (!reg_mentioned_p (base_tmp, addr));
+  gcc_assert (!reg_mentioned_p (base_tmp, element));
 
   /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY.  */
   gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 	     offset, it has the benefit that if D-FORM instructions are
 	     allowed, the offset is part of the memory access to the vector
 	     element. */
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 
   else
     {
-      if (GET_CODE (base_tmp) == SCRATCH)
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_move_insn (base_tmp, addr);
       new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
     }
 
-    /* If register allocation has been done and the address isn't valid, move
-       the address into the temporary base register.  Some reasons it could not
-       be valid include:
+    /* If the address isn't valid, move the address into the temporary base
+       register.  Some reasons it could not be valid include:
 
        The address offset overflowed the 16 or 34 bit offset size;
        We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
        We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
        Only X_FORM loads can be done, and the address is D_FORM.  */
 
-  if (!can_create_pseudo_p ())
-    {
-      enum insn_form iform
-	= address_to_insn_form (new_addr, scalar_mode,
-				reg_to_non_prefixed (scalar_reg, scalar_mode));
+  enum insn_form iform
+    = address_to_insn_form (new_addr, scalar_mode,
+			    reg_to_non_prefixed (scalar_reg, scalar_mode));
 
-      if (iform == INSN_FORM_BAD)
-	{
-	  emit_move_insn (base_tmp, new_addr);
-	  new_addr = base_tmp;
-	}
+  if (iform == INSN_FORM_BAD)
+    {
+      emit_move_insn (base_tmp, new_addr);
+      new_addr = base_tmp;
     }
 
   return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c9634980302..04877dd51f6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
-			      (V8HI  "p9v")
-			      (V4SI  "p8v")])
-
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -3977,94 +3971,23 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number.  If the element number is 0 or the address is offsettable, we don't
-;; need a temporary base register.  For vector registers, we require X-form
-;; addressing.
+;; Optimize extracting a single scalar element from memory.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,Q,Z,Q")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,n,O,n")])))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+   (clobber (match_scratch:DI 3 "=&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& 1"
+  "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
-}
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "*,*,8,*,8")
-   (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
-	(any_extend:DI
-	 (vec_select:SI
-	  (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
-	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(any_extend:DI (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   SImode);
-}
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
-	(zero_extend:GPR
-	 (vec_select:<VEC_base>
-	  (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
-	  (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
-  "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(zero_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VSX_EXTRACT_I2:VEC_base>mode);
-}
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "*,*,8,*,8")
-   (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_z<mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
-	(sign_extend:GPR
-	 (vec_select:HI
-	  (match_operand:V8HI 1 "memory_operand" "m,o,Q")
-	  (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
-   (clobber (match_scratch:DI 3 "=X,X,&b"))]
-  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(sign_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   HImode);
 }
   [(set_attr "type" "load")
-   (set_attr "length" "*,*,8")])
+   (set_attr "length" "8")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 37cb9c0ae90..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   QImode and fold zero extension into the load.  */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
-  return vec_extract (*p, 0);		/* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
-  return vec_extract (*p, 1);          /* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
-  return vec_extract (p[4], 0);		/* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
-  return vec_extract (p[4], 3);		/* lbz, no rlwinm.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M}    4 } } */
-/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 3314f0cde3a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and fold zero extension into the load.  */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
-  return vec_extract (*p, 0);          /* lwz, no rldicl.  */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
-  return vec_extract (*p, 1);          /* lwz, no rldicl.  */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
-  return vec_extract (p[4], 0);		/* lwz, no rldicl.  */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
-  return vec_extract (p[4], 3);		/* lwz, no rldicl.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M}    4 } } */
-/* { dg-final { scan-assembler-not   {\mrldicl\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 4d0e08908cc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and fold sign extension into the load.  */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
-  return vec_extract (*p, 0);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
-  return vec_extract (*p, 1);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M}   4 } } */
-/* { dg-final { scan-assembler-not   {\mlwz\M}     } } */
-/* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
-
-extract_sign_v4si_0 (vector int *p)
-{
-  return vec_extract (*p, 0);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
-  return vec_extract (*p, 1);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M}   4 } } */
-/* { dg-final { scan-assembler-not   {\mlwz\M}     } } */
-/* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index f17bb874f01..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and fold zero extension into the load.  */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
-  return vec_extract (*p, 0);          /* lwz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
-  return vec_extract (*p, 1);          /* lwz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
-  return vec_extract (p[4], 0);		/* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
-  return vec_extract (p[4], 3);		/* lbz, no rlwinm.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlhz\M}    4 } } */
-/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 47c41027a28..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   HImode and fold sign extension into the load.  */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
-  return vec_extract (*p, 0);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
-  return vec_extract (*p, 1);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
-  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
-  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M}   4 } } */
-/* { dg-final { scan-assembler-not   {\mlhz\M}     } } */
-/* { dg-final { scan-assembler-not   {\mextsh\M}   } } */