[gcc(refs/users/meissner/heads/work119)] Revert patches

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:b88b631d6981f177487212d322bdb832c2fa8cbd

commit b88b631d6981f177487212d322bdb832c2fa8cbd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 27 15:11:22 2023 -0400

    Revert patches

Diff:
---
 gcc/config/rs6000/rs6000.cc                        |  56 ++---
 gcc/config/rs6000/rs6000.md                        |   3 -
 gcc/config/rs6000/vsx.md                           | 278 ++-------------------
 .../gcc.target/powerpc/vec-extract-mem-char-1.c    |  35 ---
 .../gcc.target/powerpc/vec-extract-mem-char-2.c    |  40 ---
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     |  35 ---
 .../gcc.target/powerpc/vec-extract-mem-int-2.c     |  36 ---
 .../gcc.target/powerpc/vec-extract-mem-int-3.c     |  31 ---
 .../gcc.target/powerpc/vec-extract-mem-int-4.c     |  40 ---
 .../gcc.target/powerpc/vec-extract-mem-int-5.c     |  40 ---
 .../gcc.target/powerpc/vec-extract-mem-short-1.c   |  35 ---
 .../gcc.target/powerpc/vec-extract-mem-short-2.c   |  36 ---
 .../gcc.target/powerpc/vec-extract-mem-short-3.c   |  19 --
 .../gcc.target/powerpc/vec-extract-mem-short-4.c   |  40 ---
 14 files changed, 33 insertions(+), 691 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (CONST_INT_P (element))
     return GEN_INT (INTVAL (element) * scalar_size);
 
-  if (GET_CODE (base_tmp) == SCRATCH)
-    base_tmp = gen_reg_rtx (Pmode);
-
-  /* After register allocation, all insns should use the 'Q' constraint
-     (address is a single register) if the element number is not a
-     constant.  */
-  gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+  /* All insns should use the 'Q' constraint (address is a single register) if
+     the element number is not a constant.  */
+  gcc_assert (satisfies_constraint_Q (mem));
 
   /* Mask the element to make sure the element number is between 0 and the
      maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
   if (shift > 0)
     {
       rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
-      if (can_create_pseudo_p ())
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_insn (gen_rtx_SET (base_tmp, shift_op));
     }
 
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
 
       else
 	{
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_move_insn (base_tmp, addr);
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
    that is valid for reads or writes to a given register (SCALAR_REG).
 
-   The temporary BASE_TMP might be set multiple times with this code if this is
-   called after register allocation.  */
+   This function is expected to be called after reload is completed when we are
+   splitting insns.  The temporary BASE_TMP might be set multiple times with
+   this code.  */
 
 rtx
 rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
   rtx addr = XEXP (mem, 0);
   rtx new_addr;
 
-  if (GET_CODE (base_tmp) != SCRATCH)
-    {
-      gcc_assert (!reg_mentioned_p (base_tmp, addr));
-      gcc_assert (!reg_mentioned_p (base_tmp, element));
-    }
+  gcc_assert (!reg_mentioned_p (base_tmp, addr));
+  gcc_assert (!reg_mentioned_p (base_tmp, element));
 
   /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY.  */
   gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 	     offset, it has the benefit that if D-FORM instructions are
 	     allowed, the offset is part of the memory access to the vector
 	     element. */
-	  if (GET_CODE (base_tmp) == SCRATCH)
-	    base_tmp = gen_reg_rtx (Pmode);
-
 	  emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
 	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
 
   else
     {
-      if (GET_CODE (base_tmp) == SCRATCH)
-	base_tmp = gen_reg_rtx (Pmode);
-
       emit_move_insn (base_tmp, addr);
       new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
     }
 
-    /* If register allocation has been done and the address isn't valid, move
-       the address into the temporary base register.  Some reasons it could not
-       be valid include:
+    /* If the address isn't valid, move the address into the temporary base
+       register.  Some reasons it could not be valid include:
 
        The address offset overflowed the 16 or 34 bit offset size;
        We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
        We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
        Only X_FORM loads can be done, and the address is D_FORM.  */
 
-  if (!can_create_pseudo_p ())
-    {
-      enum insn_form iform
-	= address_to_insn_form (new_addr, scalar_mode,
-				reg_to_non_prefixed (scalar_reg, scalar_mode));
+  enum insn_form iform
+    = address_to_insn_form (new_addr, scalar_mode,
+			    reg_to_non_prefixed (scalar_reg, scalar_mode));
 
-      if (iform == INSN_FORM_BAD)
-	{
-	  emit_move_insn (base_tmp, new_addr);
-	  new_addr = base_tmp;
-	}
+  if (iform == INSN_FORM_BAD)
+    {
+      emit_move_insn (base_tmp, new_addr);
+      new_addr = base_tmp;
     }
 
   return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
 		       (float		"")
 		       (unsigned_float	"uns")])
 
-(define_code_attr fp_int_extend [(float          "sign_extend")
-				 (unsigned_float "zero_extend")])
-
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.
 (define_mode_attr wd [(QI    "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2a5a9b45e34..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
-			      (V8HI  "p9v")
-			      (V4SI  "p8v")])
-
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -3555,7 +3549,6 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
-;; V4SF extract from memory with constant element number.
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3574,27 +3567,6 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
-;; V4SF extract from memory with constant element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
-  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
-	(float_extend:DF
-	 (vec_select:SF
-	  (match_operand:V4SF 1 "memory_operand" "m,Z,m")
-	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
-   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
-  "VECTOR_MEM_VSX_P (V4SFmode)"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(float_extend:DF (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], SFmode);
-}
-  [(set_attr "type" "fpload")
-   (set_attr "length" "8")
-   (set_attr "isa" "*,p7v,p9v")])
-
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3630,25 +3602,6 @@
 }
   [(set_attr "type" "fpload,load")])
 
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
-	(float_extend:DF
-	 (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
-		     (match_operand:DI 2 "gpc_reg_operand" "r")]
-		    UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b"))]
-  "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(float_extend:DF (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], SFmode);
-}
-  [(set_attr "type" "fpload")])
-
 ;; Expand the builtin form of xxpermdi to canonical rtl.
 (define_expand "vsx_xxpermdi_<mode>"
   [(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3977,151 +3930,23 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number.  If the element number is 0 or the address is offsettable, we don't
-;; need a temporary base register.  For vector registers, we require X-form
-;; addressing.
+;; Optimize extracting a single scalar element from memory.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,Q,Z,Q")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,n,O,n")])))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+   (clobber (match_scratch:DI 3 "=&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& 1"
+  "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VEC_base>mode);
-}
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "*,*,8,*,8")
-   (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
-	(any_extend:DI
-	 (vec_select:SI
-	  (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
-	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(any_extend:DI (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   SImode);
-}
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
-	(zero_extend:GPR
-	 (vec_select:<VEC_base>
-	  (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
-	  (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
-   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
-  "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(zero_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VSX_EXTRACT_I2:VEC_base>mode);
-}
-  [(set_attr "type" "load,load,load,fpload,fpload")
-   (set_attr "length" "*,*,8,*,8")
-   (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
-  [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
-	(any_float:SFDF
-	 (vec_select:SI
-	  (match_operand:V4SI 1 "memory_operand" "Z,Q")
-	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
-   (clobber (match_scratch:DI 3 "=X,&b"))
-   (clobber (match_scratch:DI 4 "=wa,wa"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 4)
-	(<fp_int_extend>:DI (match_dup 5)))
-   (set (match_dup 0)
-	(float:SFDF (match_dup 4)))]
-{
-  if (GET_CODE (operands[4]) == SCRATCH)
-    operands[4] = gen_reg_rtx (DImode);
-  
-  operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   SImode);
-}
-  [(set_attr "type" "fpload")
-   (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
-  [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
-	(unsigned_float:SFDF
-	 (vec_select:<VSX_EXTRACT_I2:VEC_base>
-	  (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
-	  (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
-   (clobber (match_scratch:DI 3 "=X,&b"))
-   (clobber (match_scratch:DI 4 "=v,v"))]
-  "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
-  "#"
-  "&& 1"
-  [(set (match_dup 4)
-	(zero_extend:DI (match_dup 5)))
-   (set (match_dup 0)
-	(float:SFDF (match_dup 4)))]
-{
-  if (GET_CODE (operands[4]) == SCRATCH)
-    operands[4] = gen_reg_rtx (DImode);
-  
-  operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VSX_EXTRACT_I2:VEC_base>mode);
-}
-  [(set_attr "type" "fpload")
-   (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
-	(sign_extend:GPR
-	 (vec_select:HI
-	  (match_operand:V8HI 1 "memory_operand" "m,o,Q")
-	  (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
-   (clobber (match_scratch:DI 3 "=X,X,&b"))]
-  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& 1"
-  [(set (match_dup 0)
-	(sign_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   HImode);
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
 }
   [(set_attr "type" "load")
-   (set_attr "length" "*,*,8")])
+   (set_attr "length" "8")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
@@ -4143,92 +3968,21 @@
 }
   [(set_attr "isa" "p9v,*")])
 
-;; Variable V16QI/V8HI/V4SI extract from memory.  We need to split after reload
-;; on power8 due to the vector byte swap support which creates Altivec
-;; addresses.  These are eliminated after register allocation since we use 'Q'
-;; or 'Z' constraints.
+;; Variable V16QI/V8HI/V4SI extract from memory
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
 	(unspec:<VEC_base>
-	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
-	  (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+	  (match_operand:DI 2 "gpc_reg_operand" "r")]
 	 UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
+   (clobber (match_scratch:DI 3 "=&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VEC_base>mode);
-}
-  [(set_attr "type" "load,fpload")
-   (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
-	(any_extend:DI
-	 (unspec:SI
-	  [(match_operand:V4SI 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(any_extend:DI (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   SImode);
-}
-  [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
-	(zero_extend:GPR
-	 (unspec:<VSX_EXTRACT_I2:MODE>
-	  [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   <VSX_EXTRACT_I2:MODE>mode);
-}
-  [(set_attr "type" "load,fpload")
-   (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(sign_extend:GPR
-	 (unspec:HI
-	  [(match_operand:V8HI 1 "memory_operand" "Q")
-	   (match_operand:DI 2 "gpc_reg_operand" "r")]
-	  UNSPEC_VSX_EXTRACT)))
-   (clobber (match_scratch:DI 3 "=&b"))]
-  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:GPR (match_dup 4)))]
-{
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
-					   operands[2], operands[3],
-					   HImode);
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], <VEC_base>mode);
 }
   [(set_attr "type" "load")])
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 61f021ee99f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   QImode and fold zero extension into the load.  */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
-  return vec_extract (*p, 0);		/* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
-  return vec_extract (*p, 1);          /* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
-  return vec_extract (p[4], 0);		/* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
-  return vec_extract (p[4], 3);		/* lbz, no rlwinm.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M}  4 } } */
-/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index fd6b6d03699..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   QImode and convert it to unsigned floating point, by loading the value
-   directly to a vector register, rather than loading up a GPR and transfering
-   the result to a vector register..  */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
-  return vec_extract (*p, 0);	/* lxsibzx, fcfid/xscvsxddp.  */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
-  return vec_extract (*p, 1);	/* lxsibzx, fcfid/xscvsxddp.  */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
-  return vec_extract (p[4], 0);	/* lxsibzx, fcfids/xscvsxdsp.  */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
-  return vec_extract (p[4], 3);	/* lxsibzx, fcfids/xscvsxdsp.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M}            4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp}  2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not   {\mlbzx?\M}                } } */
-/* { dg-final { scan-assembler-not   {\mmtvsr}                  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e59ceae6866..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and fold zero extension into the load.  */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
-  return vec_extract (*p, 0);          /* lwz, no rldicl.  */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
-  return vec_extract (*p, 1);          /* lwz, no rldicl.  */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
-  return vec_extract (p[4], 0);		/* lwz, no rldicl.  */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
-  return vec_extract (p[4], 3);		/* lwz, no rldicl.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M}  4 } } */
-/* { dg-final { scan-assembler-not   {\mrldicl\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 052371e72ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and fold sign extension into the load.  */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
-  return vec_extract (*p, 0);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
-  return vec_extract (*p, 1);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not   {\mlwzx?\M}   } } */
-/* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index f6b027db3bc..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
-   SImode and fold both zero and sign extension into the load.  Both uses
-   generate a rldicl to clear the bits in the variable element number, but this
-   test verifies that there is no rldicl after the lwzx to do the zero
-   extension.  */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
-  return vec_extract (*p, n);	/* lwax, no extsw.  */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
-  return vec_extract (*p, n);	/* lwzx, no extra rldicl.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M}   1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M}   1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M}   2 } } */
-/* { dg-final { scan-assembler-not   {\mlw[az]\M}   } } */
-/* { dg-final { scan-assembler-not   {\mextsw\M}    } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 79f634b33b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and convert it to unsigned floating point, by loading the value
-   directly to a vector register, rather than loading up a GPR and transfering
-   the result to a vector register..  */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
-  return vec_extract (*p, 0);	/* lfiwzx/lxsiwzx, fcfid/xscvsxddp.  */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
-  return vec_extract (*p, 1);	/* lfiwzx/lxsiwzx, fcfid/xscvsxddp.  */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
-  return vec_extract (p[4], 0);	/* lfiwzx/lxsiwzx, fcfids/xscvsxdsp.  */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
-  return vec_extract (p[4], 3);	/* lfiwzx/lxsiwzx, fcfids/xscvsxdsp.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not   {\mlw[az]x?\M}               } } */
-/* { dg-final { scan-assembler-not   {\mmtvsr}                    } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index d51d26482c3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and convert it to signed floating point, by loading the value
-   directly to a vector register, rather than loading up a GPR and transfering
-   the result to a vector register..  */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
-  return vec_extract (*p, 0);	/* lfiwzx/lxsiwzx, fcfid/xscvsxddp.  */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
-  return vec_extract (*p, 1);	/* lfiwzx/lxsiwzx, fcfid/xscvsxddp.  */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 0);	/* lfiwzx/lxsiwzx, fcfids/xscvsxdsp.  */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
-  return vec_extract (p[4], 3);	/* lfiwzx/lxsiwzx, fcfids/xscvsxdsp.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not   {\mlw[az]x?\M}               } } */
-/* { dg-final { scan-assembler-not   {\mmtvsr}                    } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 65ae21b1a1c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   SImode and fold zero extension into the load.  */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
-  return vec_extract (*p, 0);          /* lwz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
-  return vec_extract (*p, 1);          /* lwz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
-  return vec_extract (p[4], 0);		/* lbz, no rlwinm.  */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
-  return vec_extract (p[4], 3);		/* lbz, no rlwinm.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M}  4 } } */
-/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 6a2f23cfc57..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   HImode and fold sign extension into the load.  */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
-  return vec_extract (*p, 0);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
-  return vec_extract (*p, 1);          /* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
-  return vec_extract (p[4], 0);		/* lwa, no extsw.  */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
-  return vec_extract (p[4], 3);		/* lwa, no extsw.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not   {\mlhzx?\M}   } } */
-/* { dg-final { scan-assembler-not   {\mextsh\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index a1d3947fabb..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
-   HImode and fold sign extension into the load.  */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
-  return vec_extract (*p, n);		/* lwax, no extsw.  */
-}
-
-/* { dg-final { scan-assembler     {\mlhax\M}   } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M}  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 24ad6fd3a7e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
-   HImode and convert it to unsigned floating point, by loading the value
-   directly to a vector register, rather than loading up a GPR and transfering
-   the result to a vector register..  */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
-  return vec_extract (*p, 0);	/* lxsihzx, fcfid/xscvsxddp.  */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
-  return vec_extract (*p, 1);	/* lxsihzx, fcfid/xscvsxddp.  */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
-  return vec_extract (p[4], 0);	/* lxsihzx, fcfids/xscvsxdsp.  */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
-  return vec_extract (p[4], 3);	/* lxsihzx, fcfids/xscvsxdsp.  */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M}              4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not   {\mlh[az]x?\M}               } } */
-/* { dg-final { scan-assembler-not   {\mmtvsr}                    } } */