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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches
Date: Fri, 28 Apr 2023 06:29:15 +0000 (GMT) [thread overview]
Message-ID: <20230428062915.261333858C2D@sourceware.org> (raw)
https://gcc.gnu.org/g:36affc7dd7f6557971477250aa953345fb7e9671
commit 36affc7dd7f6557971477250aa953345fb7e9671
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 02:29:11 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 3 --
gcc/config/rs6000/vsx.md | 56 ----------------------
| 40 ----------------
| 40 ----------------
| 40 ----------------
| 40 ----------------
6 files changed, 219 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7fa64dca29a..838caaab9ec 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4043,62 +4043,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p9v")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
;; Fold extracting a V8HI element with a constant element with sign extension
;; to either DImode or SImode.
(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index fd6b6d03699..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 79f634b33b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index d51d26482c3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 24ad6fd3a7e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
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