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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches
Date: Tue, 25 Apr 2023 15:48:54 +0000 (GMT) [thread overview]
Message-ID: <20230425154854.E5DBE3858D1E@sourceware.org> (raw)
https://gcc.gnu.org/g:d7f650f4876ccf3ec6660b7672ad69eed4b5368b
commit d7f650f4876ccf3ec6660b7672ad69eed4b5368b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 11:48:51 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 149 +--------------------
| 35 -----
| 35 -----
| 36 -----
| 31 -----
| 35 -----
| 36 -----
| 19 ---
8 files changed, 7 insertions(+), 369 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4a93523090a..0b7b26c2e2f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,73 +4000,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4089,87 +4022,19 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 37cb9c0ae90..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 3314f0cde3a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index c8ba94ad824..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f6b027db3bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index f17bb874f01..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 47c41027a28..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index a1d3947fabb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
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for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).