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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches Date: Thu, 27 Apr 2023 19:33:55 +0000 (GMT) [thread overview] Message-ID: <20230427193355.078083858D37@sourceware.org> (raw) https://gcc.gnu.org/g:670ba6be726f7e3c7c351cadfcbf1a622935a804 commit 670ba6be726f7e3c7c351cadfcbf1a622935a804 Author: Michael Meissner <meissner@linux.ibm.com> Date: Thu Apr 27 15:33:51 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/rs6000.cc | 56 ++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 39 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 65295dbaf81..3be5860dd9b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (CONST_INT_P (element)) return GEN_INT (INTVAL (element) * scalar_size); - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - - /* After register allocation, all insns should use the 'Q' constraint - (address is a single register) if the element number is not a - constant. */ - gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem)); + /* All insns should use the 'Q' constraint (address is a single register) if + the element number is not a constant. */ + gcc_assert (satisfies_constraint_Q (mem)); /* Mask the element to make sure the element number is between 0 and the maximum number of elements - 1 so that we don't generate an address @@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (shift > 0) { rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift)); - if (can_create_pseudo_p ()) - base_tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (base_tmp, shift_op)); } @@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) else { - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) temporary (BASE_TMP) to fixup the address. Return the new memory address that is valid for reads or writes to a given register (SCALAR_REG). - The temporary BASE_TMP might be set multiple times with this code if this is - called after register allocation. */ + This function is expected to be called after reload is completed when we are + splitting insns. The temporary BASE_TMP might be set multiple times with + this code. */ rtx rs6000_adjust_vec_address (rtx scalar_reg, @@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg, rtx addr = XEXP (mem, 0); rtx new_addr; - if (GET_CODE (base_tmp) != SCRATCH) - { - gcc_assert (!reg_mentioned_p (base_tmp, addr)); - gcc_assert (!reg_mentioned_p (base_tmp, element)); - } + gcc_assert (!reg_mentioned_p (base_tmp, addr)); + gcc_assert (!reg_mentioned_p (base_tmp, element)); /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */ gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC); @@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg, offset, it has the benefit that if D-FORM instructions are allowed, the offset is part of the memory access to the vector element. */ - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1))); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg, else { - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } - /* If register allocation has been done and the address isn't valid, move - the address into the temporary base register. Some reasons it could not - be valid include: + /* If the address isn't valid, move the address into the temporary base + register. Some reasons it could not be valid include: The address offset overflowed the 16 or 34 bit offset size; We need to use a DS-FORM load, and the bottom 2 bits are non-zero; We need to use a DQ-FORM load, and the bottom 4 bits are non-zero; Only X_FORM loads can be done, and the address is D_FORM. */ - if (!can_create_pseudo_p ()) - { - enum insn_form iform - = address_to_insn_form (new_addr, scalar_mode, - reg_to_non_prefixed (scalar_reg, scalar_mode)); + enum insn_form iform + = address_to_insn_form (new_addr, scalar_mode, + reg_to_non_prefixed (scalar_reg, scalar_mode)); - if (iform == INSN_FORM_BAD) - { - emit_move_insn (base_tmp, new_addr); - new_addr = base_tmp; - } + if (iform == INSN_FORM_BAD) + { + emit_move_insn (base_tmp, new_addr); + new_addr = base_tmp; } return change_address (mem, scalar_mode, new_addr);
next reply other threads:[~2023-04-27 19:33 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-27 19:33 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2023-05-01 17:16 Michael Meissner 2023-04-29 1:28 Michael Meissner 2023-04-28 22:57 Michael Meissner 2023-04-28 21:39 Michael Meissner 2023-04-28 21:30 Michael Meissner 2023-04-28 19:07 Michael Meissner 2023-04-28 18:28 Michael Meissner 2023-04-28 18:11 Michael Meissner 2023-04-28 17:33 Michael Meissner 2023-04-28 6:29 Michael Meissner 2023-04-28 3:57 Michael Meissner 2023-04-27 20:50 Michael Meissner 2023-04-27 19:11 Michael Meissner 2023-04-27 2:58 Michael Meissner 2023-04-27 2:51 Michael Meissner 2023-04-27 2:48 Michael Meissner 2023-04-26 23:55 Michael Meissner 2023-04-26 15:37 Michael Meissner 2023-04-26 15:35 Michael Meissner 2023-04-26 5:05 Michael Meissner 2023-04-25 22:46 Michael Meissner 2023-04-25 15:48 Michael Meissner 2023-04-25 6:40 Michael Meissner 2023-04-25 6:28 Michael Meissner 2023-04-25 2:15 Michael Meissner 2023-04-25 1:58 Michael Meissner 2023-04-25 1:51 Michael Meissner 2023-04-24 22:57 Michael Meissner 2023-04-22 5:50 Michael Meissner 2023-04-21 23:07 Michael Meissner 2023-04-21 23:05 Michael Meissner 2023-04-21 20:19 Michael Meissner 2023-04-21 19:50 Michael Meissner 2023-04-21 19:36 Michael Meissner 2023-04-21 19:03 Michael Meissner 2023-04-21 18:10 Michael Meissner 2023-04-21 15:37 Michael Meissner 2023-04-21 15:36 Michael Meissner 2023-04-21 15:27 Michael Meissner 2023-04-21 15:09 Michael Meissner 2023-04-21 3:57 Michael Meissner 2023-04-21 3:45 Michael Meissner 2023-04-21 3:09 Michael Meissner 2023-04-20 23:41 Michael Meissner 2023-04-19 22:11 Michael Meissner 2023-04-19 21:47 Michael Meissner 2023-04-19 19:28 Michael Meissner 2023-04-19 19:21 Michael Meissner 2023-04-19 19:14 Michael Meissner 2023-04-19 16:36 Michael Meissner 2023-04-19 16:22 Michael Meissner 2023-04-18 22:13 Michael Meissner 2023-04-18 5:37 Michael Meissner 2023-04-17 22:28 Michael Meissner
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