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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches
Date: Thu, 27 Apr 2023 20:50:44 +0000 (GMT) [thread overview]
Message-ID: <20230427205044.D4A0E3858D37@sourceware.org> (raw)
https://gcc.gnu.org/g:dceb9d2a8859af37f420abd2272880952d54a35c
commit dceb9d2a8859af37f420abd2272880952d54a35c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 16:50:41 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 49 ++--------------------
| 29 -------------
2 files changed, 4 insertions(+), 74 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3a4b8cdb02a..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3566,28 +3565,7 @@
}
[(set_attr "type" "fpload,fpload,fpload,load")
(set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v,*")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v")])
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3607,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3616,7 +3594,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
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