[PATCH 00/11] Improvements for XThead* support

[PATCH 00/11] Improvements for XThead* support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This series improves the support for the XThead* ISA extensions
which are available e.g. on the T-Head XuanTie C906.

The ISA spec can be found here:
  https://github.com/T-head-Semi/thead-extension-spec

So far the following extension support has been merged in GCC:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadMemPair

This patchset builds upon that and contains the following changes:
* Fix for sign/zero extension support for th.ext and th.extu
  This is actually a resend, that has not been merged.
  Jeff Law acked the patch last Friday.
* Fix for CFA reg notes creation
* Small fix for documentation of th_mempair_order_operands()
* Introduction of Xmode macro
* Two non-functional preparation commits for additional addressing modes
* A patch that moves XThead* specific peephole passes in its own file
* Support for XTheadMemIdx and its addressing modes
* Support for XTheadFMemIdx, which is similar to XTheadMemIdx

All patches have been tested and don't introduce regressions
for RV32 or RV64. The patches have also been tested with
SPEC CPU2017 on QEMU (multiple combinations of extensions).

Support patches of these extensions for Binutils, QEMU, and
LLVM have already been merged in the corresponding upstream
projects.

Support patches for XTheadMemIdx and XTheadFMemIdx have been
submitted in an earlier series as well and received a couple of
rework-comments from Kito. We rewrote the whole support to
better meet the (reasonable) goal of keeping vendor extension
code separated from RISC-V standard code and to address other issues.
The resulting code is structured much better, which can be seen
in the small number of changes that are required for the last patch
(XTheadFMemIdx support).

Christoph Müllner (11):
  riscv: xtheadbb: Add sign/zero extension support for th.ext and
    th.extu
  riscv: xtheadmempair: Fix CFA reg notes
  riscv: xtheadmempair: Fix doc for th_mempair_order_operands()
  riscv: thead: Adjust constraints of th_addsl INSN
  riscv: Simplify output of MEM addresses
  riscv: Define Xmode macro
  riscv: Move address classification info types to riscv-protos.h
  riscv: Prepare backend for index registers
  riscv: thead: Factor out XThead*-specific peepholes
  riscv: thead: Add support for the XTheadMemIdx ISA extension
  riscv: thead: Add support for the XTheadFMemIdx ISA extension

 gcc/config/riscv/constraints.md               |  24 +
 gcc/config/riscv/peephole.md                  |  56 --
 gcc/config/riscv/riscv-protos.h               |  74 +++
 gcc/config/riscv/riscv.cc                     |  87 ++-
 gcc/config/riscv/riscv.h                      |  13 +-
 gcc/config/riscv/riscv.md                     |  26 +-
 gcc/config/riscv/thead-peephole.md            | 292 ++++++++++
 gcc/config/riscv/thead.cc                     | 506 +++++++++++++++++-
 gcc/config/riscv/thead.md                     | 240 ++++++++-
 .../gcc.target/riscv/xtheadbb-ext-1.c         |  67 +++
 .../gcc.target/riscv/xtheadbb-extu-1.c        |  67 +++
 .../riscv/xtheadfmemidx-index-update.c        |  20 +
 .../xtheadfmemidx-index-xtheadbb-update.c     |  20 +
 .../riscv/xtheadfmemidx-index-xtheadbb.c      |  22 +
 .../gcc.target/riscv/xtheadfmemidx-index.c    |  22 +
 .../riscv/xtheadfmemidx-uindex-update.c       |  20 +
 .../xtheadfmemidx-uindex-xtheadbb-update.c    |  20 +
 .../riscv/xtheadfmemidx-uindex-xtheadbb.c     |  24 +
 .../gcc.target/riscv/xtheadfmemidx-uindex.c   |  25 +
 .../gcc.target/riscv/xtheadmemidx-helpers.h   | 222 ++++++++
 .../riscv/xtheadmemidx-index-update.c         |  27 +
 .../xtheadmemidx-index-xtheadbb-update.c      |  27 +
 .../riscv/xtheadmemidx-index-xtheadbb.c       |  36 ++
 .../gcc.target/riscv/xtheadmemidx-index.c     |  36 ++
 .../riscv/xtheadmemidx-modify-xtheadbb.c      |  74 +++
 .../gcc.target/riscv/xtheadmemidx-modify.c    |  74 +++
 .../riscv/xtheadmemidx-uindex-update.c        |  27 +
 .../xtheadmemidx-uindex-xtheadbb-update.c     |  27 +
 .../riscv/xtheadmemidx-uindex-xtheadbb.c      |  44 ++
 .../gcc.target/riscv/xtheadmemidx-uindex.c    |  44 ++
 30 files changed, 2146 insertions(+), 117 deletions(-)
 create mode 100644 gcc/config/riscv/thead-peephole.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c

-- 
2.40.1

[PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.

gcc/ChangeLog:

	* config/riscv/riscv.md: No base-ISA extension splitter for XThead*.
	* config/riscv/thead.md (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
	New XThead extension INSN.
	(*zero_extendsidi2_th_extu): New XThead extension INSN.
	(*zero_extendhi<GPR:mode>2_th_extu): New XThead extension INSN.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadbb-ext-1.c: New test.
	* gcc.target/riscv/xtheadbb-extu-1.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv.md                     |  6 +-
 gcc/config/riscv/thead.md                     | 31 +++++++++
 .../gcc.target/riscv/xtheadbb-ext-1.c         | 67 +++++++++++++++++++
 .../gcc.target/riscv/xtheadbb-extu-1.c        | 67 +++++++++++++++++++
 4 files changed, 168 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1fb29da8a0b..f4cc99187ed 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal"
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT && !TARGET_ZBA
+  "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB
    && !(register_operand (operands[1], SImode)
         && reg_or_subregno (operands[1]) == VL_REGNUM)"
   "@
@@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi<GPR:mode>2"
   [(set (match_operand:GPR    0 "register_operand"     "=r,r")
 	(zero_extend:GPR
 	    (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
-  "!TARGET_ZBB"
+  "!TARGET_ZBB && !TARGET_XTHEADBB"
   "@
    #
    lhu\t%0,%1"
@@ -1451,7 +1451,7 @@ (define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
   [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
 	(sign_extend:SUPERQI
 	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
-  "!TARGET_ZBB"
+  "!TARGET_ZBB && !TARGET_XTHEADBB"
   "@
    #
    l<SHORT:size>\t%0,%1"
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 0623607d3dc..6a06d0dfcf2 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -59,6 +59,17 @@ (define_insn "*th_ext<mode>4"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<GPR:MODE>")])
 
+(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_th_ext"
+  [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
+	(sign_extend:SUPERQI
+	    (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_XTHEADBB"
+  "@
+   th.ext\t%0,%1,15,0
+   l<SHORT:size>\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "<SUPERQI:MODE>")])
+
 (define_insn "*th_extu<mode>4"
   [(set (match_operand:GPR 0 "register_operand" "=r")
 	(zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
@@ -72,6 +83,26 @@ (define_insn "*th_extu<mode>4"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<GPR:MODE>")])
 
+(define_insn "*zero_extendsidi2_th_extu"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_64BIT && TARGET_XTHEADBB"
+  "@
+   th.extu\t%0,%1,31,0
+   lwu\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "SI")])
+
+(define_insn "*zero_extendhi<GPR:mode>2_th_extu"
+  [(set (match_operand:GPR 0 "register_operand" "=r,r")
+	(zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_XTHEADBB"
+  "@
+   th.extu\t%0,%1,15,0
+   lhu\t%0,%1"
+  [(set_attr "type" "bitmanip,load")
+   (set_attr "mode" "HI")])
+
 (define_insn "*th_clz<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")
 	(clz:X (match_operand:X 1 "register_operand" "r")))]
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
new file mode 100644
index 00000000000..02f6ec1417d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+long sext64_32(int s32)
+{
+    return s32;
+}
+
+long sext64_16(short s16)
+{
+    return s16;
+}
+
+long sext64_8(char s8)
+{
+    return s8;
+}
+
+int sext32_64(long s64)
+{
+    return s64;
+}
+
+int sext32_16(short s16)
+{
+    return s16;
+}
+
+int sext32_8(char s8)
+{
+    return s8;
+}
+
+short sext16_64(long s64)
+{
+    return s64;
+}
+
+short sext16_32(int s32)
+{
+    return s32;
+}
+
+short sext16_8(char s8)
+{
+    return s8;
+}
+
+char sext8_64(long s64)
+{
+    return s64;
+}
+
+char sext8_32(int s32)
+{
+    return s32;
+}
+
+char sext8_16(short s16)
+{
+    return s16;
+}
+
+/* { dg-final { scan-assembler-not "slli" } } */
+/* { dg-final { scan-assembler-not "srli" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
new file mode 100644
index 00000000000..01e3eda7df2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+unsigned long zext64_32(unsigned int u32)
+{
+    return u32; //th.extu a0, a0, 31, 0
+}
+
+unsigned long zext64_16(unsigned short u16)
+{
+    return u16;
+}
+
+unsigned long zext64_8(unsigned char u8)
+{
+    return u8;
+}
+
+unsigned int zext32_64(unsigned long u64)
+{
+    return u64;
+}
+
+unsigned int zext32_16(unsigned short u16)
+{
+    return u16;
+}
+
+unsigned int zext32_8(unsigned char u8)
+{
+    return u8;
+}
+
+unsigned short zext16_64(unsigned long u64)
+{
+    return u64;
+}
+
+unsigned short zext16_32(unsigned int u32)
+{
+    return u32;
+}
+
+unsigned short zext16_8(unsigned char u8)
+{
+    return u8;
+}
+
+unsigned char zext8_64(unsigned long u64)
+{
+    return u64;
+}
+
+unsigned char zext8_32(unsigned int u32)
+{
+    return u32;
+}
+
+unsigned char zext8_16(unsigned short u16)
+{
+    return u16;
+}
+
+/* { dg-final { scan-assembler-not "slli" } } */
+/* { dg-final { scan-assembler-not "srli" } } */
-- 
2.40.1

[PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

The current implementation triggers an assertion in
dwarf2out_frame_debug_cfa_offset() under certain circumstances.
The standard code uses REG_FRAME_RELATED_EXPR notes instead
of REG_CFA_OFFSET notes when saving registers on the stack.
So let's do this as well.

gcc/ChangeLog:

	* config/riscv/thead.cc (th_mempair_save_regs):
	Emit REG_FRAME_RELATED_EXPR notes in prologue.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/thead.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 75203805310..d7e3cf80d9b 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -368,8 +368,12 @@ th_mempair_save_regs (rtx operands[4])
   rtx set2 = gen_rtx_SET (operands[2], operands[3]);
   rtx insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2)));
   RTX_FRAME_RELATED_P (insn) = 1;
-  add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set1));
-  add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set2));
+
+  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+				      copy_rtx (set1), REG_NOTES (insn));
+
+  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+				      copy_rtx (set2), REG_NOTES (insn));
 }
 
 /* Similar like riscv_restore_reg, but restores two registers from memory
-- 
2.40.1

[PATCH 03/11] riscv: xtheadmempair: Fix doc for th_mempair_order_operands()

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

There is an incorrect sentence in the documentation of the function
th_mempair_order_operands(). Let's remove it.

gcc/ChangeLog:

	* config/riscv/thead.cc (th_mempair_operands_p):
	Fix documentation of th_mempair_order_operands().

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/thead.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index d7e3cf80d9b..507c912bc39 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -336,8 +336,8 @@ th_mempair_operands_p (rtx operands[4], bool load_p,
 }
 
 /* Given OPERANDS of consecutive load/store that can be merged,
-   swap them if they are not in ascending order.
-   Return true if swap was performed.  */
+   swap them if they are not in ascending order.  */
+
 void
 th_mempair_order_operands (rtx operands[4], bool load_p, machine_mode mode)
 {
-- 
2.40.1

[PATCH 04/11] riscv: thead: Adjust constraints of th_addsl INSN

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

A recent change adjusted the constraints of ZBA's shNadd INSN.
Let's mirror this change here as well.

gcc/ChangeLog:

	* config/riscv/thead.md: Adjust constraints of th_addsl.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/thead.md | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 6a06d0dfcf2..aa933960a98 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -22,10 +22,9 @@
 (define_insn "*th_addsl<mode>4"
   [(set (match_operand:X 0 "register_operand" "=r")
 	(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
-			  (match_operand 2 "const_int_operand" "n"))
+			  (match_operand:QI 2 "imm123_operand" "Ds3"))
 		(match_operand:X 3 "register_operand" "r")))]
-  "TARGET_XTHEADBA
-   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
+  "TARGET_XTHEADBA"
   "th.addsl\t%0,%3,%1,%2"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
-- 
2.40.1

[PATCH 05/11] riscv: Simplify output of MEM addresses

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

We have the following situation for MEM RTX objects:
* TARGET_PRINT_OPERAND expands to riscv_print_operand()
* This falls into the default case (unknown or on letter) of the outer
  switch-case-block and the MEM case of the inner switch-case-block and
  calls output_address() in final.cc with XEXP (op, 0) (the address)
* This calls targetm.asm_out.print_operand_address() which is
  riscv_print_operand_address()
* riscv_print_operand_address() is targeting the address of a MEM RTX
* riscv_print_operand_address() calls riscv_print_operand() for the offset
  and directly prints the register if the address is classified as ADDRESS_REG
* This falls into the default case (unknown or on letter) of the outer
  switch-case-block and the default case of the inner switch-case-block and
  calls output_addr_const().

However, since we know that offset must be a CONST_INT (which will be
followed by a '(<reg>)' string), there is no need to call
riscv_print_operand() for the offset.
Instead we can take the shortcut and use output_addr_const().

This change also brings the code in riscv_print_operand_address()
in line with the other cases, where output_addr_const() is used
to print offsets.

Tested with GCC regression test suite and SPEC intrate.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5d2550871c7..92043236b17 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4581,7 +4581,7 @@ riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx
     switch (addr.type)
       {
       case ADDRESS_REG:
-	riscv_print_operand (file, addr.offset, 0);
+	output_addr_const (file, riscv_strip_unspec_address (addr.offset));
 	fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
 	return;
 
-- 
2.40.1

[PATCH 06/11] riscv: Define Xmode macro

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Define a Xmode macro that specifies the registers size (XLEN)
similar to Pmode. This allows the backend code to write generic
RV32/RV64 C code (under certain circumstances).

gcc/ChangeLog:

	* config/riscv/riscv.h (Xmode): New macro.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..90746fe14e3 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -791,6 +791,10 @@ typedef struct {
 
 #define Pmode word_mode
 
+/* Specify the machine mode that registers have.  */
+
+#define Xmode (TARGET_64BIT ? DImode : SImode)
+
 /* Give call MEMs SImode since it is the "most permissive" mode
    for both 32-bit and 64-bit targets.  */
 
-- 
2.40.1

[PATCH 07/11] riscv: Move address classification info types to riscv-protos.h

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

enum riscv_address_type and struct riscv_address_info are used
to store address classification information. Let's move this types
into our common header file in order to share them with other
compilation units.

This is a non-functional change without any intendet side-effects.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (enum riscv_address_type):
	New location of type definition.
	(struct riscv_address_info): Likewise.
	* config/riscv/riscv.cc (enum riscv_address_type):
	Old location of type definition.
	(struct riscv_address_info): Likewise.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-protos.h | 43 +++++++++++++++++++++++++++++++++
 gcc/config/riscv/riscv.cc       | 43 ---------------------------------
 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 5244e8dcbf0..628c64cf628 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -35,6 +35,49 @@ enum riscv_symbol_type {
 };
 #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
 
+/* Classifies an address.
+
+   ADDRESS_REG
+       A natural register + offset address.  The register satisfies
+       riscv_valid_base_register_p and the offset is a const_arith_operand.
+
+   ADDRESS_LO_SUM
+       A LO_SUM rtx.  The first operand is a valid base register and
+       the second operand is a symbolic address.
+
+   ADDRESS_CONST_INT
+       A signed 16-bit constant address.
+
+   ADDRESS_SYMBOLIC:
+       A constant symbolic address.  */
+enum riscv_address_type {
+  ADDRESS_REG,
+  ADDRESS_LO_SUM,
+  ADDRESS_CONST_INT,
+  ADDRESS_SYMBOLIC
+};
+
+/* Information about an address described by riscv_address_type.
+
+   ADDRESS_CONST_INT
+       No fields are used.
+
+   ADDRESS_REG
+       REG is the base register and OFFSET is the constant offset.
+
+   ADDRESS_LO_SUM
+       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
+       is the type of symbol it references.
+
+   ADDRESS_SYMBOLIC
+       SYMBOL_TYPE is the type of symbol that the address references.  */
+struct riscv_address_info {
+  enum riscv_address_type type;
+  rtx reg;
+  rtx offset;
+  enum riscv_symbol_type symbol_type;
+};
+
 /* Routines implemented in riscv.cc.  */
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 92043236b17..8388235d8cc 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -81,28 +81,6 @@ along with GCC; see the file COPYING3.  If not see
 /* True if bit BIT is set in VALUE.  */
 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
 
-/* Classifies an address.
-
-   ADDRESS_REG
-       A natural register + offset address.  The register satisfies
-       riscv_valid_base_register_p and the offset is a const_arith_operand.
-
-   ADDRESS_LO_SUM
-       A LO_SUM rtx.  The first operand is a valid base register and
-       the second operand is a symbolic address.
-
-   ADDRESS_CONST_INT
-       A signed 16-bit constant address.
-
-   ADDRESS_SYMBOLIC:
-       A constant symbolic address.  */
-enum riscv_address_type {
-  ADDRESS_REG,
-  ADDRESS_LO_SUM,
-  ADDRESS_CONST_INT,
-  ADDRESS_SYMBOLIC
-};
-
 /* Information about a function's frame layout.  */
 struct GTY(())  riscv_frame_info {
   /* The size of the frame in bytes.  */
@@ -182,27 +160,6 @@ struct riscv_arg_info {
   unsigned int fpr_offset;
 };
 
-/* Information about an address described by riscv_address_type.
-
-   ADDRESS_CONST_INT
-       No fields are used.
-
-   ADDRESS_REG
-       REG is the base register and OFFSET is the constant offset.
-
-   ADDRESS_LO_SUM
-       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
-       is the type of symbol it references.
-
-   ADDRESS_SYMBOLIC
-       SYMBOL_TYPE is the type of symbol that the address references.  */
-struct riscv_address_info {
-  enum riscv_address_type type;
-  rtx reg;
-  rtx offset;
-  enum riscv_symbol_type symbol_type;
-};
-
 /* One stage in a constant building sequence.  These sequences have
    the form:
 
-- 
2.40.1

[PATCH 08/11] riscv: Prepare backend for index registers

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

RISC-V does currently not support index registers.
However, there are some vendor extensions that specify them.
Let's do the necessary changes in the backend so that we can
add support for such a vendor extension in the future.

This is a non-functional change without any intended side-effects.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_regno_ok_for_index_p):
	New prototype.
	(riscv_index_reg_class): Likewise.
	* config/riscv/riscv.cc (riscv_regno_ok_for_index_p): New function.
	(riscv_index_reg_class): New function.
	* config/riscv/riscv.h (INDEX_REG_CLASS): Call new function
	riscv_index_reg_class().
	(REGNO_OK_FOR_INDEX_P): Call new function
	riscv_regno_ok_for_index_p().

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-protos.h |  2 ++
 gcc/config/riscv/riscv.cc       | 20 ++++++++++++++++++++
 gcc/config/riscv/riscv.h        |  6 ++++--
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 628c64cf628..b7417e97d99 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -82,6 +82,8 @@ struct riscv_address_info {
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
+extern enum reg_class riscv_index_reg_class ();
+extern int riscv_regno_ok_for_index_p (int);
 extern int riscv_address_insns (rtx, machine_mode, bool);
 extern int riscv_const_insns (rtx);
 extern int riscv_split_const_insns (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8388235d8cc..a33f0fff8ea 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -827,6 +827,26 @@ riscv_regno_mode_ok_for_base_p (int regno,
   return GP_REG_P (regno);
 }
 
+/* Get valid index register class.
+   The RISC-V base instructions don't support index registers,
+   but extensions might support that.  */
+
+enum reg_class
+riscv_index_reg_class ()
+{
+  return NO_REGS;
+}
+
+/* Return true if register REGNO is a valid index register.
+   The RISC-V base instructions don't support index registers,
+   but extensions might support that.  */
+
+int
+riscv_regno_ok_for_index_p (int regno)
+{
+  return 0;
+}
+
 /* Return true if X is a valid base register for mode MODE.
    STRICT_P is true if REG_OK_STRICT is in effect.  */
 
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 90746fe14e3..21b81c22dea 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -535,7 +535,7 @@ enum reg_class
    factor or added to another register (as well as added to a
    displacement).  */
 
-#define INDEX_REG_CLASS NO_REGS
+#define INDEX_REG_CLASS riscv_index_reg_class()
 
 /* We generally want to put call-clobbered registers ahead of
    call-saved ones.  (IRA expects this.)  */
@@ -705,7 +705,9 @@ typedef struct {
 
 /* Addressing modes, and classification of registers for them.  */
 
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+  riscv_regno_ok_for_index_p (REGNO)
+
 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 
-- 
2.40.1

[PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch moves the XThead*-specific peephole passes
into thead-peephole.md with the intend to keep vendor-specific
code separated from RISC-V standard code.

This patch does not contain any functional changes.

gcc/ChangeLog:

	* config/riscv/peephole.md: Remove XThead* peephole passes.
	* config/riscv/thead.md: Include thead-peephole.md.
	* config/riscv/thead-peephole.md: New file.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/peephole.md       | 56 ----------------------
 gcc/config/riscv/thead-peephole.md | 74 ++++++++++++++++++++++++++++++
 gcc/config/riscv/thead.md          |  2 +
 3 files changed, 76 insertions(+), 56 deletions(-)
 create mode 100644 gcc/config/riscv/thead-peephole.md

diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md
index 67e7046d7e6..0ef0c04410b 100644
--- a/gcc/config/riscv/peephole.md
+++ b/gcc/config/riscv/peephole.md
@@ -38,59 +38,3 @@ (define_peephole2
 {
   operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
 })
-
-;; XTheadMemPair: merge two SI or DI loads
-(define_peephole2
-  [(set (match_operand:GPR 0 "register_operand" "")
-	(match_operand:GPR 1 "memory_operand" ""))
-   (set (match_operand:GPR 2 "register_operand" "")
-	(match_operand:GPR 3 "memory_operand" ""))]
-  "TARGET_XTHEADMEMPAIR
-  && th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-	          (set (match_dup 2) (match_dup 3))])]
-{
-  th_mempair_order_operands (operands, true, <GPR:MODE>mode);
-})
-
-;; XTheadMemPair: merge two SI or DI stores
-(define_peephole2
-  [(set (match_operand:GPR 0 "memory_operand" "")
-	(match_operand:GPR 1 "register_operand" ""))
-   (set (match_operand:GPR 2 "memory_operand" "")
-	(match_operand:GPR 3 "register_operand" ""))]
-  "TARGET_XTHEADMEMPAIR
-  && th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-              (set (match_dup 2) (match_dup 3))])]
-{
-  th_mempair_order_operands (operands, false, <GPR:MODE>mode);
-})
-
-;; XTheadMemPair: merge two SI loads with sign-extension
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
-   (set (match_operand:DI 2 "register_operand" "")
-	(sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
-  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
-  && th_mempair_operands_p (operands, true, SImode)"
-  [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))
-              (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]
-{
-  th_mempair_order_operands (operands, true, SImode);
-})
-
-;; XTheadMemPair: merge two SI loads with zero-extension
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
-   (set (match_operand:DI 2 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
-  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
-  && th_mempair_operands_p (operands, true, SImode)"
-  [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
-              (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]
-{
-  th_mempair_order_operands (operands, true, SImode);
-})
diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md
new file mode 100644
index 00000000000..5b829b5b968
--- /dev/null
+++ b/gcc/config/riscv/thead-peephole.md
@@ -0,0 +1,74 @@
+;; Machine description for T-Head vendor extensions
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; XTheadMemPair: merge two SI or DI loads
+(define_peephole2
+  [(set (match_operand:GPR 0 "register_operand" "")
+	(match_operand:GPR 1 "memory_operand" ""))
+   (set (match_operand:GPR 2 "register_operand" "")
+	(match_operand:GPR 3 "memory_operand" ""))]
+  "TARGET_XTHEADMEMPAIR
+  && th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
+  [(parallel [(set (match_dup 0) (match_dup 1))
+	          (set (match_dup 2) (match_dup 3))])]
+{
+  th_mempair_order_operands (operands, true, <GPR:MODE>mode);
+})
+
+;; XTheadMemPair: merge two SI or DI stores
+(define_peephole2
+  [(set (match_operand:GPR 0 "memory_operand" "")
+	(match_operand:GPR 1 "register_operand" ""))
+   (set (match_operand:GPR 2 "memory_operand" "")
+	(match_operand:GPR 3 "register_operand" ""))]
+  "TARGET_XTHEADMEMPAIR
+  && th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
+  [(parallel [(set (match_dup 0) (match_dup 1))
+              (set (match_dup 2) (match_dup 3))])]
+{
+  th_mempair_order_operands (operands, false, <GPR:MODE>mode);
+})
+
+;; XTheadMemPair: merge two SI loads with sign-extension
+(define_peephole2
+  [(set (match_operand:DI 0 "register_operand" "")
+	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
+   (set (match_operand:DI 2 "register_operand" "")
+	(sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
+  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
+  && th_mempair_operands_p (operands, true, SImode)"
+  [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))
+              (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]
+{
+  th_mempair_order_operands (operands, true, SImode);
+})
+
+;; XTheadMemPair: merge two SI loads with zero-extension
+(define_peephole2
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
+   (set (match_operand:DI 2 "register_operand" "")
+	(zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
+  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
+  && th_mempair_operands_p (operands, true, SImode)"
+  [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
+              (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]
+{
+  th_mempair_order_operands (operands, true, SImode);
+})
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index aa933960a98..1ac4dd9b462 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -374,3 +374,5 @@ (define_insn "*th_mempair_load_zero_extendsidi2"
   [(set_attr "move_type" "load")
    (set_attr "mode" "DI")
    (set_attr "length" "8")])
+
+(include "thead-peephole.md")
-- 
2.40.1

Re: [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu

[Kito Cheng]

ok

On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The current support of the bitfield-extraction instructions
> th.ext and th.extu (XTheadBb extension) only covers sign_extract
> and zero_extract. This patch add support for sign_extend and
> zero_extend to avoid any shifts for sign or zero extensions.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: No base-ISA extension splitter for XThead*.
>         * config/riscv/thead.md (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
>         New XThead extension INSN.
>         (*zero_extendsidi2_th_extu): New XThead extension INSN.
>         (*zero_extendhi<GPR:mode>2_th_extu): New XThead extension INSN.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/xtheadbb-ext-1.c: New test.
>         * gcc.target/riscv/xtheadbb-extu-1.c: New test.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv.md                     |  6 +-
>  gcc/config/riscv/thead.md                     | 31 +++++++++
>  .../gcc.target/riscv/xtheadbb-ext-1.c         | 67 +++++++++++++++++++
>  .../gcc.target/riscv/xtheadbb-extu-1.c        | 67 +++++++++++++++++++
>  4 files changed, 168 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 1fb29da8a0b..f4cc99187ed 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal"
>    [(set (match_operand:DI     0 "register_operand"     "=r,r")
>         (zero_extend:DI
>             (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
> -  "TARGET_64BIT && !TARGET_ZBA
> +  "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB
>     && !(register_operand (operands[1], SImode)
>          && reg_or_subregno (operands[1]) == VL_REGNUM)"
>    "@
> @@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi<GPR:mode>2"
>    [(set (match_operand:GPR    0 "register_operand"     "=r,r")
>         (zero_extend:GPR
>             (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
> -  "!TARGET_ZBB"
> +  "!TARGET_ZBB && !TARGET_XTHEADBB"
>    "@
>     #
>     lhu\t%0,%1"
> @@ -1451,7 +1451,7 @@ (define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
>    [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
>         (sign_extend:SUPERQI
>             (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
> -  "!TARGET_ZBB"
> +  "!TARGET_ZBB && !TARGET_XTHEADBB"
>    "@
>     #
>     l<SHORT:size>\t%0,%1"
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 0623607d3dc..6a06d0dfcf2 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -59,6 +59,17 @@ (define_insn "*th_ext<mode>4"
>    [(set_attr "type" "bitmanip")
>     (set_attr "mode" "<GPR:MODE>")])
>
> +(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_th_ext"
> +  [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
> +       (sign_extend:SUPERQI
> +           (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
> +  "TARGET_XTHEADBB"
> +  "@
> +   th.ext\t%0,%1,15,0
> +   l<SHORT:size>\t%0,%1"
> +  [(set_attr "type" "bitmanip,load")
> +   (set_attr "mode" "<SUPERQI:MODE>")])
> +
>  (define_insn "*th_extu<mode>4"
>    [(set (match_operand:GPR 0 "register_operand" "=r")
>         (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
> @@ -72,6 +83,26 @@ (define_insn "*th_extu<mode>4"
>    [(set_attr "type" "bitmanip")
>     (set_attr "mode" "<GPR:MODE>")])
>
> +(define_insn "*zero_extendsidi2_th_extu"
> +  [(set (match_operand:DI 0 "register_operand" "=r,r")
> +       (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
> +  "TARGET_64BIT && TARGET_XTHEADBB"
> +  "@
> +   th.extu\t%0,%1,31,0
> +   lwu\t%0,%1"
> +  [(set_attr "type" "bitmanip,load")
> +   (set_attr "mode" "SI")])
> +
> +(define_insn "*zero_extendhi<GPR:mode>2_th_extu"
> +  [(set (match_operand:GPR 0 "register_operand" "=r,r")
> +       (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
> +  "TARGET_XTHEADBB"
> +  "@
> +   th.extu\t%0,%1,15,0
> +   lhu\t%0,%1"
> +  [(set_attr "type" "bitmanip,load")
> +   (set_attr "mode" "HI")])
> +
>  (define_insn "*th_clz<mode>2"
>    [(set (match_operand:X 0 "register_operand" "=r")
>         (clz:X (match_operand:X 1 "register_operand" "r")))]
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
> new file mode 100644
> index 00000000000..02f6ec1417d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
> @@ -0,0 +1,67 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
> +
> +long sext64_32(int s32)
> +{
> +    return s32;
> +}
> +
> +long sext64_16(short s16)
> +{
> +    return s16;
> +}
> +
> +long sext64_8(char s8)
> +{
> +    return s8;
> +}
> +
> +int sext32_64(long s64)
> +{
> +    return s64;
> +}
> +
> +int sext32_16(short s16)
> +{
> +    return s16;
> +}
> +
> +int sext32_8(char s8)
> +{
> +    return s8;
> +}
> +
> +short sext16_64(long s64)
> +{
> +    return s64;
> +}
> +
> +short sext16_32(int s32)
> +{
> +    return s32;
> +}
> +
> +short sext16_8(char s8)
> +{
> +    return s8;
> +}
> +
> +char sext8_64(long s64)
> +{
> +    return s64;
> +}
> +
> +char sext8_32(int s32)
> +{
> +    return s32;
> +}
> +
> +char sext8_16(short s16)
> +{
> +    return s16;
> +}
> +
> +/* { dg-final { scan-assembler-not "slli" } } */
> +/* { dg-final { scan-assembler-not "srli" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
> new file mode 100644
> index 00000000000..01e3eda7df2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
> @@ -0,0 +1,67 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
> +
> +unsigned long zext64_32(unsigned int u32)
> +{
> +    return u32; //th.extu a0, a0, 31, 0
> +}
> +
> +unsigned long zext64_16(unsigned short u16)
> +{
> +    return u16;
> +}
> +
> +unsigned long zext64_8(unsigned char u8)
> +{
> +    return u8;
> +}
> +
> +unsigned int zext32_64(unsigned long u64)
> +{
> +    return u64;
> +}
> +
> +unsigned int zext32_16(unsigned short u16)
> +{
> +    return u16;
> +}
> +
> +unsigned int zext32_8(unsigned char u8)
> +{
> +    return u8;
> +}
> +
> +unsigned short zext16_64(unsigned long u64)
> +{
> +    return u64;
> +}
> +
> +unsigned short zext16_32(unsigned int u32)
> +{
> +    return u32;
> +}
> +
> +unsigned short zext16_8(unsigned char u8)
> +{
> +    return u8;
> +}
> +
> +unsigned char zext8_64(unsigned long u64)
> +{
> +    return u64;
> +}
> +
> +unsigned char zext8_32(unsigned int u32)
> +{
> +    return u32;
> +}
> +
> +unsigned char zext8_16(unsigned short u16)
> +{
> +    return u16;
> +}
> +
> +/* { dg-final { scan-assembler-not "slli" } } */
> +/* { dg-final { scan-assembler-not "srli" } } */
> --
> 2.40.1
>

Re: [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes

[Kito Cheng]

ok

On Fri, Apr 28, 2023 at 2:15 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The current implementation triggers an assertion in
> dwarf2out_frame_debug_cfa_offset() under certain circumstances.
> The standard code uses REG_FRAME_RELATED_EXPR notes instead
> of REG_CFA_OFFSET notes when saving registers on the stack.
> So let's do this as well.
>
> gcc/ChangeLog:
>
>         * config/riscv/thead.cc (th_mempair_save_regs):
>         Emit REG_FRAME_RELATED_EXPR notes in prologue.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/thead.cc | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
> index 75203805310..d7e3cf80d9b 100644
> --- a/gcc/config/riscv/thead.cc
> +++ b/gcc/config/riscv/thead.cc
> @@ -368,8 +368,12 @@ th_mempair_save_regs (rtx operands[4])
>    rtx set2 = gen_rtx_SET (operands[2], operands[3]);
>    rtx insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2)));
>    RTX_FRAME_RELATED_P (insn) = 1;
> -  add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set1));
> -  add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set2));
> +
> +  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
> +                                     copy_rtx (set1), REG_NOTES (insn));
> +
> +  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
> +                                     copy_rtx (set2), REG_NOTES (insn));
>  }
>
>  /* Similar like riscv_restore_reg, but restores two registers from memory
> --
> 2.40.1
>

Re: [PATCH 03/11] riscv: xtheadmempair: Fix doc for th_mempair_order_operands()

[Kito Cheng]

LGTM

On Fri, Apr 28, 2023 at 2:17 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> There is an incorrect sentence in the documentation of the function
> th_mempair_order_operands(). Let's remove it.
>
> gcc/ChangeLog:
>
>         * config/riscv/thead.cc (th_mempair_operands_p):
>         Fix documentation of th_mempair_order_operands().
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/thead.cc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
> index d7e3cf80d9b..507c912bc39 100644
> --- a/gcc/config/riscv/thead.cc
> +++ b/gcc/config/riscv/thead.cc
> @@ -336,8 +336,8 @@ th_mempair_operands_p (rtx operands[4], bool load_p,
>  }
>
>  /* Given OPERANDS of consecutive load/store that can be merged,
> -   swap them if they are not in ascending order.
> -   Return true if swap was performed.  */
> +   swap them if they are not in ascending order.  */
> +
>  void
>  th_mempair_order_operands (rtx operands[4], bool load_p, machine_mode mode)
>  {
> --
> 2.40.1
>

Re: [PATCH 04/11] riscv: thead: Adjust constraints of th_addsl INSN

[Kito Cheng]

LGTM, personally I also like this way too.

On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> A recent change adjusted the constraints of ZBA's shNadd INSN.
> Let's mirror this change here as well.
>
> gcc/ChangeLog:
>
>         * config/riscv/thead.md: Adjust constraints of th_addsl.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/thead.md | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 6a06d0dfcf2..aa933960a98 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -22,10 +22,9 @@
>  (define_insn "*th_addsl<mode>4"
>    [(set (match_operand:X 0 "register_operand" "=r")
>         (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> -                         (match_operand 2 "const_int_operand" "n"))
> +                         (match_operand:QI 2 "imm123_operand" "Ds3"))
>                 (match_operand:X 3 "register_operand" "r")))]
> -  "TARGET_XTHEADBA
> -   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
> +  "TARGET_XTHEADBA"
>    "th.addsl\t%0,%3,%1,%2"
>    [(set_attr "type" "bitmanip")
>     (set_attr "mode" "<X:MODE>")])
> --
> 2.40.1
>

Re: [PATCH 05/11] riscv: Simplify output of MEM addresses

[Kito Cheng]

LGTM, thanks :)

On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> We have the following situation for MEM RTX objects:
> * TARGET_PRINT_OPERAND expands to riscv_print_operand()
> * This falls into the default case (unknown or on letter) of the outer
>   switch-case-block and the MEM case of the inner switch-case-block and
>   calls output_address() in final.cc with XEXP (op, 0) (the address)
> * This calls targetm.asm_out.print_operand_address() which is
>   riscv_print_operand_address()
> * riscv_print_operand_address() is targeting the address of a MEM RTX
> * riscv_print_operand_address() calls riscv_print_operand() for the offset
>   and directly prints the register if the address is classified as ADDRESS_REG
> * This falls into the default case (unknown or on letter) of the outer
>   switch-case-block and the default case of the inner switch-case-block and
>   calls output_addr_const().
>
> However, since we know that offset must be a CONST_INT (which will be
> followed by a '(<reg>)' string), there is no need to call
> riscv_print_operand() for the offset.
> Instead we can take the shortcut and use output_addr_const().
>
> This change also brings the code in riscv_print_operand_address()
> in line with the other cases, where output_addr_const() is used
> to print offsets.
>
> Tested with GCC regression test suite and SPEC intrate.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5d2550871c7..92043236b17 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4581,7 +4581,7 @@ riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx
>      switch (addr.type)
>        {
>        case ADDRESS_REG:
> -       riscv_print_operand (file, addr.offset, 0);
> +       output_addr_const (file, riscv_strip_unspec_address (addr.offset));
>         fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
>         return;
>
> --
> 2.40.1
>

Re: [PATCH 06/11] riscv: Define Xmode macro

[Kito Cheng]

My first impression is that it should be the same as Pmode, but I
admit it has more clear semantics, and would be useful when we have
ilp32 on rv64.

So LGTM

On Fri, Apr 28, 2023 at 2:16 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> Define a Xmode macro that specifies the registers size (XLEN)
> similar to Pmode. This allows the backend code to write generic
> RV32/RV64 C code (under certain circumstances).
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.h (Xmode): New macro.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 66fb07d6652..90746fe14e3 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -791,6 +791,10 @@ typedef struct {
>
>  #define Pmode word_mode
>
> +/* Specify the machine mode that registers have.  */
> +
> +#define Xmode (TARGET_64BIT ? DImode : SImode)
> +
>  /* Give call MEMs SImode since it is the "most permissive" mode
>     for both 32-bit and 64-bit targets.  */
>
> --
> 2.40.1
>

Re: [PATCH 07/11] riscv: Move address classification info types to riscv-protos.h

[Kito Cheng]

OK :)

On Fri, Apr 28, 2023 at 2:15 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> enum riscv_address_type and struct riscv_address_info are used
> to store address classification information. Let's move this types
> into our common header file in order to share them with other
> compilation units.
>
> This is a non-functional change without any intendet side-effects.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (enum riscv_address_type):
>         New location of type definition.
>         (struct riscv_address_info): Likewise.
>         * config/riscv/riscv.cc (enum riscv_address_type):
>         Old location of type definition.
>         (struct riscv_address_info): Likewise.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-protos.h | 43 +++++++++++++++++++++++++++++++++
>  gcc/config/riscv/riscv.cc       | 43 ---------------------------------
>  2 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 5244e8dcbf0..628c64cf628 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -35,6 +35,49 @@ enum riscv_symbol_type {
>  };
>  #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
>
> +/* Classifies an address.
> +
> +   ADDRESS_REG
> +       A natural register + offset address.  The register satisfies
> +       riscv_valid_base_register_p and the offset is a const_arith_operand.
> +
> +   ADDRESS_LO_SUM
> +       A LO_SUM rtx.  The first operand is a valid base register and
> +       the second operand is a symbolic address.
> +
> +   ADDRESS_CONST_INT
> +       A signed 16-bit constant address.
> +
> +   ADDRESS_SYMBOLIC:
> +       A constant symbolic address.  */
> +enum riscv_address_type {
> +  ADDRESS_REG,
> +  ADDRESS_LO_SUM,
> +  ADDRESS_CONST_INT,
> +  ADDRESS_SYMBOLIC
> +};
> +
> +/* Information about an address described by riscv_address_type.
> +
> +   ADDRESS_CONST_INT
> +       No fields are used.
> +
> +   ADDRESS_REG
> +       REG is the base register and OFFSET is the constant offset.
> +
> +   ADDRESS_LO_SUM
> +       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
> +       is the type of symbol it references.
> +
> +   ADDRESS_SYMBOLIC
> +       SYMBOL_TYPE is the type of symbol that the address references.  */
> +struct riscv_address_info {
> +  enum riscv_address_type type;
> +  rtx reg;
> +  rtx offset;
> +  enum riscv_symbol_type symbol_type;
> +};
> +
>  /* Routines implemented in riscv.cc.  */
>  extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>  extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 92043236b17..8388235d8cc 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -81,28 +81,6 @@ along with GCC; see the file COPYING3.  If not see
>  /* True if bit BIT is set in VALUE.  */
>  #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
>
> -/* Classifies an address.
> -
> -   ADDRESS_REG
> -       A natural register + offset address.  The register satisfies
> -       riscv_valid_base_register_p and the offset is a const_arith_operand.
> -
> -   ADDRESS_LO_SUM
> -       A LO_SUM rtx.  The first operand is a valid base register and
> -       the second operand is a symbolic address.
> -
> -   ADDRESS_CONST_INT
> -       A signed 16-bit constant address.
> -
> -   ADDRESS_SYMBOLIC:
> -       A constant symbolic address.  */
> -enum riscv_address_type {
> -  ADDRESS_REG,
> -  ADDRESS_LO_SUM,
> -  ADDRESS_CONST_INT,
> -  ADDRESS_SYMBOLIC
> -};
> -
>  /* Information about a function's frame layout.  */
>  struct GTY(())  riscv_frame_info {
>    /* The size of the frame in bytes.  */
> @@ -182,27 +160,6 @@ struct riscv_arg_info {
>    unsigned int fpr_offset;
>  };
>
> -/* Information about an address described by riscv_address_type.
> -
> -   ADDRESS_CONST_INT
> -       No fields are used.
> -
> -   ADDRESS_REG
> -       REG is the base register and OFFSET is the constant offset.
> -
> -   ADDRESS_LO_SUM
> -       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
> -       is the type of symbol it references.
> -
> -   ADDRESS_SYMBOLIC
> -       SYMBOL_TYPE is the type of symbol that the address references.  */
> -struct riscv_address_info {
> -  enum riscv_address_type type;
> -  rtx reg;
> -  rtx offset;
> -  enum riscv_symbol_type symbol_type;
> -};
> -
>  /* One stage in a constant building sequence.  These sequences have
>     the form:
>
> --
> 2.40.1
>

Re: [PATCH 08/11] riscv: Prepare backend for index registers

[Kito Cheng]

OK

On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> RISC-V does currently not support index registers.
> However, there are some vendor extensions that specify them.
> Let's do the necessary changes in the backend so that we can
> add support for such a vendor extension in the future.
>
> This is a non-functional change without any intended side-effects.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (riscv_regno_ok_for_index_p):
>         New prototype.
>         (riscv_index_reg_class): Likewise.
>         * config/riscv/riscv.cc (riscv_regno_ok_for_index_p): New function.
>         (riscv_index_reg_class): New function.
>         * config/riscv/riscv.h (INDEX_REG_CLASS): Call new function
>         riscv_index_reg_class().
>         (REGNO_OK_FOR_INDEX_P): Call new function
>         riscv_regno_ok_for_index_p().
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-protos.h |  2 ++
>  gcc/config/riscv/riscv.cc       | 20 ++++++++++++++++++++
>  gcc/config/riscv/riscv.h        |  6 ++++--
>  3 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 628c64cf628..b7417e97d99 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -82,6 +82,8 @@ struct riscv_address_info {
>  extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>  extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>  extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
> +extern enum reg_class riscv_index_reg_class ();
> +extern int riscv_regno_ok_for_index_p (int);
>  extern int riscv_address_insns (rtx, machine_mode, bool);
>  extern int riscv_const_insns (rtx);
>  extern int riscv_split_const_insns (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 8388235d8cc..a33f0fff8ea 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -827,6 +827,26 @@ riscv_regno_mode_ok_for_base_p (int regno,
>    return GP_REG_P (regno);
>  }
>
> +/* Get valid index register class.
> +   The RISC-V base instructions don't support index registers,
> +   but extensions might support that.  */
> +
> +enum reg_class
> +riscv_index_reg_class ()
> +{
> +  return NO_REGS;
> +}
> +
> +/* Return true if register REGNO is a valid index register.
> +   The RISC-V base instructions don't support index registers,
> +   but extensions might support that.  */
> +
> +int
> +riscv_regno_ok_for_index_p (int regno)
> +{
> +  return 0;
> +}
> +
>  /* Return true if X is a valid base register for mode MODE.
>     STRICT_P is true if REG_OK_STRICT is in effect.  */
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 90746fe14e3..21b81c22dea 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -535,7 +535,7 @@ enum reg_class
>     factor or added to another register (as well as added to a
>     displacement).  */
>
> -#define INDEX_REG_CLASS NO_REGS
> +#define INDEX_REG_CLASS riscv_index_reg_class()
>
>  /* We generally want to put call-clobbered registers ahead of
>     call-saved ones.  (IRA expects this.)  */
> @@ -705,7 +705,9 @@ typedef struct {
>
>  /* Addressing modes, and classification of registers for them.  */
>
> -#define REGNO_OK_FOR_INDEX_P(REGNO) 0
> +#define REGNO_OK_FOR_INDEX_P(REGNO) \
> +  riscv_regno_ok_for_index_p (REGNO)
> +
>  #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
>    riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
>
> --
> 2.40.1
>

Re: [PATCH 00/11] Improvements for XThead* support

[Kito Cheng]

Feel free to just commit those patch got approved, I think last two
patch will take longer time to review than others :P

On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This series improves the support for the XThead* ISA extensions
> which are available e.g. on the T-Head XuanTie C906.
>
> The ISA spec can be found here:
>   https://github.com/T-head-Semi/thead-extension-spec
>
> So far the following extension support has been merged in GCC:
> * XTheadBa
> * XTheadBb
> * XTheadBs
> * XTheadCmo
> * XTheadCondMov
> * XTheadMemPair
>
> This patchset builds upon that and contains the following changes:
> * Fix for sign/zero extension support for th.ext and th.extu
>   This is actually a resend, that has not been merged.
>   Jeff Law acked the patch last Friday.
> * Fix for CFA reg notes creation
> * Small fix for documentation of th_mempair_order_operands()
> * Introduction of Xmode macro
> * Two non-functional preparation commits for additional addressing modes
> * A patch that moves XThead* specific peephole passes in its own file
> * Support for XTheadMemIdx and its addressing modes
> * Support for XTheadFMemIdx, which is similar to XTheadMemIdx
>
> All patches have been tested and don't introduce regressions
> for RV32 or RV64. The patches have also been tested with
> SPEC CPU2017 on QEMU (multiple combinations of extensions).
>
> Support patches of these extensions for Binutils, QEMU, and
> LLVM have already been merged in the corresponding upstream
> projects.
>
> Support patches for XTheadMemIdx and XTheadFMemIdx have been
> submitted in an earlier series as well and received a couple of
> rework-comments from Kito. We rewrote the whole support to
> better meet the (reasonable) goal of keeping vendor extension
> code separated from RISC-V standard code and to address other issues.
> The resulting code is structured much better, which can be seen
> in the small number of changes that are required for the last patch
> (XTheadFMemIdx support).
>
> Christoph Müllner (11):
>   riscv: xtheadbb: Add sign/zero extension support for th.ext and
>     th.extu
>   riscv: xtheadmempair: Fix CFA reg notes
>   riscv: xtheadmempair: Fix doc for th_mempair_order_operands()
>   riscv: thead: Adjust constraints of th_addsl INSN
>   riscv: Simplify output of MEM addresses
>   riscv: Define Xmode macro
>   riscv: Move address classification info types to riscv-protos.h
>   riscv: Prepare backend for index registers
>   riscv: thead: Factor out XThead*-specific peepholes
>   riscv: thead: Add support for the XTheadMemIdx ISA extension
>   riscv: thead: Add support for the XTheadFMemIdx ISA extension
>
>  gcc/config/riscv/constraints.md               |  24 +
>  gcc/config/riscv/peephole.md                  |  56 --
>  gcc/config/riscv/riscv-protos.h               |  74 +++
>  gcc/config/riscv/riscv.cc                     |  87 ++-
>  gcc/config/riscv/riscv.h                      |  13 +-
>  gcc/config/riscv/riscv.md                     |  26 +-
>  gcc/config/riscv/thead-peephole.md            | 292 ++++++++++
>  gcc/config/riscv/thead.cc                     | 506 +++++++++++++++++-
>  gcc/config/riscv/thead.md                     | 240 ++++++++-
>  .../gcc.target/riscv/xtheadbb-ext-1.c         |  67 +++
>  .../gcc.target/riscv/xtheadbb-extu-1.c        |  67 +++
>  .../riscv/xtheadfmemidx-index-update.c        |  20 +
>  .../xtheadfmemidx-index-xtheadbb-update.c     |  20 +
>  .../riscv/xtheadfmemidx-index-xtheadbb.c      |  22 +
>  .../gcc.target/riscv/xtheadfmemidx-index.c    |  22 +
>  .../riscv/xtheadfmemidx-uindex-update.c       |  20 +
>  .../xtheadfmemidx-uindex-xtheadbb-update.c    |  20 +
>  .../riscv/xtheadfmemidx-uindex-xtheadbb.c     |  24 +
>  .../gcc.target/riscv/xtheadfmemidx-uindex.c   |  25 +
>  .../gcc.target/riscv/xtheadmemidx-helpers.h   | 222 ++++++++
>  .../riscv/xtheadmemidx-index-update.c         |  27 +
>  .../xtheadmemidx-index-xtheadbb-update.c      |  27 +
>  .../riscv/xtheadmemidx-index-xtheadbb.c       |  36 ++
>  .../gcc.target/riscv/xtheadmemidx-index.c     |  36 ++
>  .../riscv/xtheadmemidx-modify-xtheadbb.c      |  74 +++
>  .../gcc.target/riscv/xtheadmemidx-modify.c    |  74 +++
>  .../riscv/xtheadmemidx-uindex-update.c        |  27 +
>  .../xtheadmemidx-uindex-xtheadbb-update.c     |  27 +
>  .../riscv/xtheadmemidx-uindex-xtheadbb.c      |  44 ++
>  .../gcc.target/riscv/xtheadmemidx-uindex.c    |  44 ++
>  30 files changed, 2146 insertions(+), 117 deletions(-)
>  create mode 100644 gcc/config/riscv/thead-peephole.md
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c
>
> --
> 2.40.1
>

Re: [PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes

[Kito Cheng]

 LGTM, I like this refactor.

On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This patch moves the XThead*-specific peephole passes
> into thead-peephole.md with the intend to keep vendor-specific
> code separated from RISC-V standard code.
>
> This patch does not contain any functional changes.
>
> gcc/ChangeLog:
>
>         * config/riscv/peephole.md: Remove XThead* peephole passes.
>         * config/riscv/thead.md: Include thead-peephole.md.
>         * config/riscv/thead-peephole.md: New file.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/peephole.md       | 56 ----------------------
>  gcc/config/riscv/thead-peephole.md | 74 ++++++++++++++++++++++++++++++
>  gcc/config/riscv/thead.md          |  2 +
>  3 files changed, 76 insertions(+), 56 deletions(-)
>  create mode 100644 gcc/config/riscv/thead-peephole.md
>
> diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md
> index 67e7046d7e6..0ef0c04410b 100644
> --- a/gcc/config/riscv/peephole.md
> +++ b/gcc/config/riscv/peephole.md
> @@ -38,59 +38,3 @@ (define_peephole2
>  {
>    operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
>  })
> -
> -;; XTheadMemPair: merge two SI or DI loads
> -(define_peephole2
> -  [(set (match_operand:GPR 0 "register_operand" "")
> -       (match_operand:GPR 1 "memory_operand" ""))
> -   (set (match_operand:GPR 2 "register_operand" "")
> -       (match_operand:GPR 3 "memory_operand" ""))]
> -  "TARGET_XTHEADMEMPAIR
> -  && th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
> -  [(parallel [(set (match_dup 0) (match_dup 1))
> -                 (set (match_dup 2) (match_dup 3))])]
> -{
> -  th_mempair_order_operands (operands, true, <GPR:MODE>mode);
> -})
> -
> -;; XTheadMemPair: merge two SI or DI stores
> -(define_peephole2
> -  [(set (match_operand:GPR 0 "memory_operand" "")
> -       (match_operand:GPR 1 "register_operand" ""))
> -   (set (match_operand:GPR 2 "memory_operand" "")
> -       (match_operand:GPR 3 "register_operand" ""))]
> -  "TARGET_XTHEADMEMPAIR
> -  && th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
> -  [(parallel [(set (match_dup 0) (match_dup 1))
> -              (set (match_dup 2) (match_dup 3))])]
> -{
> -  th_mempair_order_operands (operands, false, <GPR:MODE>mode);
> -})
> -
> -;; XTheadMemPair: merge two SI loads with sign-extension
> -(define_peephole2
> -  [(set (match_operand:DI 0 "register_operand" "")
> -       (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
> -   (set (match_operand:DI 2 "register_operand" "")
> -       (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
> -  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
> -  && th_mempair_operands_p (operands, true, SImode)"
> -  [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))
> -              (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]
> -{
> -  th_mempair_order_operands (operands, true, SImode);
> -})
> -
> -;; XTheadMemPair: merge two SI loads with zero-extension
> -(define_peephole2
> -  [(set (match_operand:DI 0 "register_operand" "")
> -       (zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
> -   (set (match_operand:DI 2 "register_operand" "")
> -       (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
> -  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
> -  && th_mempair_operands_p (operands, true, SImode)"
> -  [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
> -              (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]
> -{
> -  th_mempair_order_operands (operands, true, SImode);
> -})
> diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md
> new file mode 100644
> index 00000000000..5b829b5b968
> --- /dev/null
> +++ b/gcc/config/riscv/thead-peephole.md
> @@ -0,0 +1,74 @@
> +;; Machine description for T-Head vendor extensions
> +;; Copyright (C) 2023 Free Software Foundation, Inc.
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +;; XTheadMemPair: merge two SI or DI loads
> +(define_peephole2
> +  [(set (match_operand:GPR 0 "register_operand" "")
> +       (match_operand:GPR 1 "memory_operand" ""))
> +   (set (match_operand:GPR 2 "register_operand" "")
> +       (match_operand:GPR 3 "memory_operand" ""))]
> +  "TARGET_XTHEADMEMPAIR
> +  && th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
> +  [(parallel [(set (match_dup 0) (match_dup 1))
> +                 (set (match_dup 2) (match_dup 3))])]
> +{
> +  th_mempair_order_operands (operands, true, <GPR:MODE>mode);
> +})
> +
> +;; XTheadMemPair: merge two SI or DI stores
> +(define_peephole2
> +  [(set (match_operand:GPR 0 "memory_operand" "")
> +       (match_operand:GPR 1 "register_operand" ""))
> +   (set (match_operand:GPR 2 "memory_operand" "")
> +       (match_operand:GPR 3 "register_operand" ""))]
> +  "TARGET_XTHEADMEMPAIR
> +  && th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
> +  [(parallel [(set (match_dup 0) (match_dup 1))
> +              (set (match_dup 2) (match_dup 3))])]
> +{
> +  th_mempair_order_operands (operands, false, <GPR:MODE>mode);
> +})
> +
> +;; XTheadMemPair: merge two SI loads with sign-extension
> +(define_peephole2
> +  [(set (match_operand:DI 0 "register_operand" "")
> +       (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
> +   (set (match_operand:DI 2 "register_operand" "")
> +       (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
> +  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
> +  && th_mempair_operands_p (operands, true, SImode)"
> +  [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))
> +              (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]
> +{
> +  th_mempair_order_operands (operands, true, SImode);
> +})
> +
> +;; XTheadMemPair: merge two SI loads with zero-extension
> +(define_peephole2
> +  [(set (match_operand:DI 0 "register_operand" "")
> +       (zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
> +   (set (match_operand:DI 2 "register_operand" "")
> +       (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
> +  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
> +  && th_mempair_operands_p (operands, true, SImode)"
> +  [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
> +              (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]
> +{
> +  th_mempair_order_operands (operands, true, SImode);
> +})
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index aa933960a98..1ac4dd9b462 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -374,3 +374,5 @@ (define_insn "*th_mempair_load_zero_extendsidi2"
>    [(set_attr "move_type" "load")
>     (set_attr "mode" "DI")
>     (set_attr "length" "8")])
> +
> +(include "thead-peephole.md")
> --
> 2.40.1
>

Re: [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes

[Christoph Müllner]

On Fri, Apr 28, 2023 at 8:12 AM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The current implementation triggers an assertion in
> dwarf2out_frame_debug_cfa_offset() under certain circumstances.
> The standard code uses REG_FRAME_RELATED_EXPR notes instead
> of REG_CFA_OFFSET notes when saving registers on the stack.
> So let's do this as well.
>
> gcc/ChangeLog:
>
>         * config/riscv/thead.cc (th_mempair_save_regs):
>         Emit REG_FRAME_RELATED_EXPR notes in prologue.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This patch applies cleanly on GCC 13.
Ok to backport to GCC 13 (fixing PR114160)?

> ---
>  gcc/config/riscv/thead.cc | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
> index 75203805310..d7e3cf80d9b 100644
> --- a/gcc/config/riscv/thead.cc
> +++ b/gcc/config/riscv/thead.cc
> @@ -368,8 +368,12 @@ th_mempair_save_regs (rtx operands[4])
>    rtx set2 = gen_rtx_SET (operands[2], operands[3]);
>    rtx insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2)));
>    RTX_FRAME_RELATED_P (insn) = 1;
> -  add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set1));
> -  add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set2));
> +
> +  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
> +                                     copy_rtx (set1), REG_NOTES (insn));
> +
> +  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
> +                                     copy_rtx (set2), REG_NOTES (insn));
>  }
>
>  /* Similar like riscv_restore_reg, but restores two registers from memory
> --
> 2.40.1
>

Re: [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes

[Jeff Law]

On 3/17/24 2:22 PM, Christoph Müllner wrote:
> On Fri, Apr 28, 2023 at 8:12 AM Christoph Muellner
> <christoph.muellner@vrull.eu> wrote:
>>
>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>
>> The current implementation triggers an assertion in
>> dwarf2out_frame_debug_cfa_offset() under certain circumstances.
>> The standard code uses REG_FRAME_RELATED_EXPR notes instead
>> of REG_CFA_OFFSET notes when saving registers on the stack.
>> So let's do this as well.
>>
>> gcc/ChangeLog:
>>
>>          * config/riscv/thead.cc (th_mempair_save_regs):
>>          Emit REG_FRAME_RELATED_EXPR notes in prologue.
>>
>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> This patch applies cleanly on GCC 13.
> Ok to backport to GCC 13 (fixing PR114160)?
Yes.  Please go ahead.

Thanks,
jeff