* [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1
@ 2022-02-01 13:49 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
` (8 more replies)
0 siblings, 9 replies; 39+ messages in thread
From: Tsukasa OI @ 2022-02-01 13:49 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
*** PLEASE READ THIS FIRST ***
- My (Tsukasa OI's) copyright assignment to FSF is complete. So,
applying my other patchsets including previous ones should be safe
now. However, there are conflicts and considerations. See
"Conflicts with other my pending patchsets" below.
- This part (PATCH 4) contains small but new proposal (relaxing
fmv.[sdq] requirements). Note that before merging.
[About this patchset]
This is the first part (Part 1) of my Z[fdq]inx fixes/enhancements.
I have two options for the second half (Part 2 and 3, an important fix
but require major changes) and will be separated to Part 2A and 2B.
- Part 1 (you are here)
Relatively minor Zfinx-related fixes.
- Part 2 (2A and 2B)
Fixes an issue that GNU Binutils allows to emit/disassemble illegal
Zdinx/Zqinx instructions. We have multiple ways to fix this issue
but all of them have drawbacks. So, this part is going to be RFC
PATCH (mutually exclusive Part 2A and 2B).
- Part 3
Test cases for Part 2 (common). This test is independent from how
we fix the issue and separated to Part 3.
[Conflicts with other my pending patchsets]
This patchset **conflicts** with my Zfh/Zfhmin patchset (RFC PATCH) as
it lacks new instruction flags I added in Part 2B.
<https://sourceware.org/pipermail/binutils/2022-January/119276.html>
This patchset is a superset of following patchset (included in Part 2),
so after this patchset is merged, fcvt fix patch below is
no longer required (may be merged before this patchset, though):
<https://sourceware.org/pipermail/binutils/2022-January/119239.html>
This patchset is compatible (should not conflict) with patchsets below:
<https://sourceware.org/pipermail/binutils/2022-January/119270.html>
<https://sourceware.org/pipermail/binutils/2022-January/119282.html>
<https://sourceware.org/pipermail/binutils/2022-January/119545.html>
[Patches in Part 1]
DESIGN CHOICE (may be debatable):
1. Relax `fmv.[sdq]' instruction requirements (PATCH 4).
BUG FIXES:
1. Disassembling Zfinx/Zdinx/Zqinx instruction with -M numeric does not
make "floating point" registers numeric.
[Fixed in PATCH 1]
2. Zqinx testcases use (possibly) invalid odd-numbered registers
[Fixed in PATCH 5]
OTHER EDITORIAL CHANGES (in PATCH 2 and 3)...
[PATCH 1: Fix disassembling Zfinx instructions with -M numeric]
The problem is simple. If you disassemble a Zfinx instruction
`feq.s a0,a1,a2', we get something like this:
80000028 <_start>:
80000028: a0c5a553 feq.s x10,a1,a2
Note that integer operand (a0) is replaced with numeric representaion
(x10) but two floating operands (a1 and a2) are not.
This commit substitutes "replaced FP-GPRs" from ABI names to dynamically
set names (set according to -M numeric option). After this commit,
we get something like this:
80000028 <_start>:
80000028: a0c5a553 feq.s x10,x11,x12
[PATCH 2 and 3: Editorial changes]
PATCH 2 makes indentation on testcases consistent (by replacing two
spaces with a tab).
PATCH 3 replaces "a0,a0" with "a0,a1" whenever possible for better
encoding space checking.
[PATCH 4: Relax fmv.[sdq] requirements]
For simplicity, I will talk about fmv.d (the same almost applies to
others).
Current GNU Binutils handles `fmv.d' as a part `D' extension but NOT
`Zdinx' extension. On the other hand, `fmv.d' is an alias of `fsgnj.d'
instruction, which is a part of both `D' and `Zdinx' (correct).
If `fmv.d' is just a register move between general purpose registers,
`mv' pseudoinstruction is probably simpler.
However, this is not the end. Let's think about `fmv.d a0, a2'.
This is effectively equivalent to following instruction on RV64_Zdinx:
mv a0, a2
On Zdinx, we handle floating point numbers using general purpose
registers so it seems using `fmv.d' has no point.
However, this is different on RV32_Zdinx:
(Execute two instructions atomically)
mv a0, a2
mv a1, a3
Yes, the register pairs (a0:a1 <- a2:a3). Because of this, defining
`fmv.d' on RV32_Zdinx enables developers reflect their intent (because
intent of `fsgnj.d' is not clear enough at first glance).
I propose to make `fmv.[sdq]' available to Zfinx/Zdinx/Zqinx extensions.
[PATCH 5: Fix Zqinx tests to use even-numbered registers]
As I later explain in the Part 2A, RV64_Zqinx would require
even-numbered registers (uses register pairs). This is closely related
to Part 2 (which fixes the issue which allows to emit/disassemble
illegal Zdinx/Zqinx instructions) but can be fixed independently.
Tsukasa OI (5):
RISC-V: Fix disassembling Zfinx with -M numeric
RISC-V: Make indentation consistent
RISC-V: Use different registers for testing
RISC-V: Relax `fmv.[sdq]' requirements
RISC-V: Fix RV64_Zqinx to use register pairs
gas/testsuite/gas/riscv/zdinx.d | 7 ++-
gas/testsuite/gas/riscv/zdinx.s | 7 ++-
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 +++
gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 +
gas/testsuite/gas/riscv/zfinx.d | 7 ++-
gas/testsuite/gas/riscv/zfinx.s | 7 ++-
gas/testsuite/gas/riscv/zqinx.d | 69 +++++++++++----------
gas/testsuite/gas/riscv/zqinx.s | 69 +++++++++++----------
opcodes/riscv-dis.c | 2 +-
opcodes/riscv-opc.c | 6 +-
10 files changed, 102 insertions(+), 84 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
base-commit: e327c35ef5768789d3ba41a629f178f5eec32790
--
2.32.0
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI @ 2022-02-01 13:49 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI ` (7 subsequent siblings) 8 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:49 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions. --- gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++ gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++ opcodes/riscv-dis.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d new file mode 100644 index 00000000000..ba3f62295eb --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d @@ -0,0 +1,10 @@ +#as: -march=rv64ima_zfinx +#source: zfinx-dis-numeric.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s new file mode 100644 index 00000000000..b55cbd56b21 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s @@ -0,0 +1,2 @@ +target: + feq.s a0, a1, a2 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 34724d4aec5..07de1ce080a 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -605,7 +605,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) /* If arch has ZFINX flags, use gpr for disassemble. */ if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) { -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric 2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:49:02 PST (-0800), binutils@sourceware.org wrote: > This commit fixes floating point operand register names from ABI ones > to dynamically set ones. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of > Zfinx extension and -M numeric disassembler option. > * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. > > opcodes/ChangeLog: > > * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR > names to disassemble Zfinx instructions. > --- > gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++ > gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++ > opcodes/riscv-dis.c | 2 +- > 3 files changed, 13 insertions(+), 1 deletion(-) > create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d > create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s > > diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d > new file mode 100644 > index 00000000000..ba3f62295eb > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d > @@ -0,0 +1,10 @@ > +#as: -march=rv64ima_zfinx > +#source: zfinx-dis-numeric.s > +#objdump: -dr -Mnumeric > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 > diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s > new file mode 100644 > index 00000000000..b55cbd56b21 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s > @@ -0,0 +1,2 @@ > +target: > + feq.s a0, a1, a2 > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index 34724d4aec5..07de1ce080a 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -605,7 +605,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) > > /* If arch has ZFINX flags, use gpr for disassemble. */ > if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) > - riscv_fpr_names = riscv_gpr_names_abi; > + riscv_fpr_names = riscv_gpr_names; > > for (; op->name; op++) > { Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/5] RISC-V: Make indentation consistent 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI 2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI @ 2022-02-01 13:49 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI ` (6 subsequent siblings) 8 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:49 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit makes indentation consistent (replaces two spaces to a tab) on Zfinx / Zdinx / Zqinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Make indentation consistent. * testsuite/gas/riscv/zdinx.s: Likewise. * testsuite/gas/riscv/zqinx.s: Likewise. --- gas/testsuite/gas/riscv/zdinx.s | 2 +- gas/testsuite/gas/riscv/zfinx.s | 2 +- gas/testsuite/gas/riscv/zqinx.s | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..d8d13c88046 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -28,6 +28,6 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 - fneg.d a0, a0 + fneg.d a0, a0 fabs.d a0, a0 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..37a2aa75992 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -26,6 +26,6 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 - fneg.s a0, a0 + fneg.s a0, a0 fabs.s a0, a0 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..4b83552aced 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -30,6 +30,6 @@ target: fle.q a0, a1, a2 fgt.q a0, a1, a2 fge.q a0, a1, a2 - fneg.q a0, a0 + fneg.q a0, a0 fabs.q a0, a0 fclass.q a0, a1 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/5] RISC-V: Make indentation consistent 2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:49:03 PST (-0800), binutils@sourceware.org wrote: > This commit makes indentation consistent (replaces two spaces to a tab) > on Zfinx / Zdinx / Zqinx testcases. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx.s: Make indentation consistent. > * testsuite/gas/riscv/zdinx.s: Likewise. > * testsuite/gas/riscv/zqinx.s: Likewise. > --- > gas/testsuite/gas/riscv/zdinx.s | 2 +- > gas/testsuite/gas/riscv/zfinx.s | 2 +- > gas/testsuite/gas/riscv/zqinx.s | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s > index c427d982aaf..d8d13c88046 100644 > --- a/gas/testsuite/gas/riscv/zdinx.s > +++ b/gas/testsuite/gas/riscv/zdinx.s > @@ -28,6 +28,6 @@ target: > fle.d a0, a1, a2 > fgt.d a0, a1, a2 > fge.d a0, a1, a2 > - fneg.d a0, a0 > + fneg.d a0, a0 > fabs.d a0, a0 > fclass.d a0, a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s > index af50490fadf..37a2aa75992 100644 > --- a/gas/testsuite/gas/riscv/zfinx.s > +++ b/gas/testsuite/gas/riscv/zfinx.s > @@ -26,6 +26,6 @@ target: > fle.s a0, a1, a2 > fgt.s a0, a1, a2 > fge.s a0, a1, a2 > - fneg.s a0, a0 > + fneg.s a0, a0 > fabs.s a0, a0 > fclass.s a0, a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index ba5179dc727..4b83552aced 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -30,6 +30,6 @@ target: > fle.q a0, a1, a2 > fgt.q a0, a1, a2 > fge.q a0, a1, a2 > - fneg.q a0, a0 > + fneg.q a0, a0 > fabs.q a0, a0 > fclass.q a0, a1 Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/5] RISC-V: Use different registers for testing 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI 2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI 2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI @ 2022-02-01 13:49 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI ` (5 subsequent siblings) 8 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:49 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit ensures that different registers are used when testing. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers. * testsuite/gas/riscv/zqinx.d: Likewise. --- gas/testsuite/gas/riscv/zdinx.d | 6 +++--- gas/testsuite/gas/riscv/zdinx.s | 6 +++--- gas/testsuite/gas/riscv/zfinx.d | 6 +++--- gas/testsuite/gas/riscv/zfinx.s | 6 +++--- gas/testsuite/gas/riscv/zqinx.d | 6 +++--- gas/testsuite/gas/riscv/zqinx.s | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..cb465bfbef4 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -11,7 +11,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 @@ -36,6 +36,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index d8d13c88046..f44358111de 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -3,7 +3,7 @@ target: fsub.d a0, a1, a2 fmul.d a0, a1, a2 fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fsqrt.d a0, a1 fmin.d a0, a1, a2 fmax.d a0, a1, a2 fmadd.d a0, a1, a2, a3 @@ -28,6 +28,6 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..6465c08ea9a 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -11,7 +11,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 @@ -34,6 +34,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 37a2aa75992..41ae0e38ad4 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -3,7 +3,7 @@ target: fsub.s a0, a1, a2 fmul.s a0, a1, a2 fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fsqrt.s a0, a1 fmin.s a0, a1, a2 fmax.s a0, a1, a2 fmadd.s a0, a1, a2, a3 @@ -26,6 +26,6 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index 5c2202d21b6..e8d2b7ba4c5 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -11,7 +11,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 @@ -38,6 +38,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 4b83552aced..ecfa509b98c 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -3,7 +3,7 @@ target: fsub.q a0, a1, a2 fmul.q a0, a1, a2 fdiv.q a0, a1, a2 - fsqrt.q a0, a0 + fsqrt.q a0, a1 fmin.q a0, a1, a2 fmax.q a0, a1, a2 fmadd.q a0, a1, a2, a3 @@ -30,6 +30,6 @@ target: fle.q a0, a1, a2 fgt.q a0, a1, a2 fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 + fneg.q a0, a1 + fabs.q a0, a1 fclass.q a0, a1 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] RISC-V: Use different registers for testing 2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:49:04 PST (-0800), binutils@sourceware.org wrote: > This commit ensures that different registers are used when testing. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx.s: Use different registers. > * testsuite/gas/riscv/zfinx.d: Likewise. > * testsuite/gas/riscv/zdinx.s: Use different registers. > * testsuite/gas/riscv/zdinx.d: Likewise. > * testsuite/gas/riscv/zqinx.s: Use different registers. > * testsuite/gas/riscv/zqinx.d: Likewise. > --- > gas/testsuite/gas/riscv/zdinx.d | 6 +++--- > gas/testsuite/gas/riscv/zdinx.s | 6 +++--- > gas/testsuite/gas/riscv/zfinx.d | 6 +++--- > gas/testsuite/gas/riscv/zfinx.s | 6 +++--- > gas/testsuite/gas/riscv/zqinx.d | 6 +++--- > gas/testsuite/gas/riscv/zqinx.s | 6 +++--- > 6 files changed, 18 insertions(+), 18 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d > index 3e4c1a73388..cb465bfbef4 100644 > --- a/gas/testsuite/gas/riscv/zdinx.d > +++ b/gas/testsuite/gas/riscv/zdinx.d > @@ -11,7 +11,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 > @@ -36,6 +36,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s > index d8d13c88046..f44358111de 100644 > --- a/gas/testsuite/gas/riscv/zdinx.s > +++ b/gas/testsuite/gas/riscv/zdinx.s > @@ -3,7 +3,7 @@ target: > fsub.d a0, a1, a2 > fmul.d a0, a1, a2 > fdiv.d a0, a1, a2 > - fsqrt.d a0, a0 > + fsqrt.d a0, a1 > fmin.d a0, a1, a2 > fmax.d a0, a1, a2 > fmadd.d a0, a1, a2, a3 > @@ -28,6 +28,6 @@ target: > fle.d a0, a1, a2 > fgt.d a0, a1, a2 > fge.d a0, a1, a2 > - fneg.d a0, a0 > - fabs.d a0, a0 > + fneg.d a0, a1 > + fabs.d a0, a1 > fclass.d a0, a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d > index d5499aa9131..6465c08ea9a 100644 > --- a/gas/testsuite/gas/riscv/zfinx.d > +++ b/gas/testsuite/gas/riscv/zfinx.d > @@ -11,7 +11,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 > @@ -34,6 +34,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s > index 37a2aa75992..41ae0e38ad4 100644 > --- a/gas/testsuite/gas/riscv/zfinx.s > +++ b/gas/testsuite/gas/riscv/zfinx.s > @@ -3,7 +3,7 @@ target: > fsub.s a0, a1, a2 > fmul.s a0, a1, a2 > fdiv.s a0, a1, a2 > - fsqrt.s a0, a0 > + fsqrt.s a0, a1 > fmin.s a0, a1, a2 > fmax.s a0, a1, a2 > fmadd.s a0, a1, a2, a3 > @@ -26,6 +26,6 @@ target: > fle.s a0, a1, a2 > fgt.s a0, a1, a2 > fge.s a0, a1, a2 > - fneg.s a0, a0 > - fabs.s a0, a0 > + fneg.s a0, a1 > + fabs.s a0, a1 > fclass.s a0, a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d > index 5c2202d21b6..e8d2b7ba4c5 100644 > --- a/gas/testsuite/gas/riscv/zqinx.d > +++ b/gas/testsuite/gas/riscv/zqinx.d > @@ -11,7 +11,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 > @@ -38,6 +38,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 > -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 > +[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index 4b83552aced..ecfa509b98c 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -3,7 +3,7 @@ target: > fsub.q a0, a1, a2 > fmul.q a0, a1, a2 > fdiv.q a0, a1, a2 > - fsqrt.q a0, a0 > + fsqrt.q a0, a1 > fmin.q a0, a1, a2 > fmax.q a0, a1, a2 > fmadd.q a0, a1, a2, a3 > @@ -30,6 +30,6 @@ target: > fle.q a0, a1, a2 > fgt.q a0, a1, a2 > fge.q a0, a1, a2 > - fneg.q a0, a0 > - fabs.q a0, a0 > + fneg.q a0, a1 > + fabs.q a0, a1 > fclass.q a0, a1 Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI ` (2 preceding siblings ...) 2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI @ 2022-02-01 13:49 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI ` (4 subsequent siblings) 8 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:49 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit relaxes requirements to `fmv.s' instructions from F to (F or Zfinx). The same applies to `fmv.d' and `fmv.q'. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index cb465bfbef4..3db2cb56f1a 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -36,6 +36,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index f44358111de..cdf5f3c2e7e 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -28,6 +28,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 6465c08ea9a..6fc4491fbc0 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -34,6 +34,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 41ae0e38ad4..d63c0c37570 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -26,6 +26,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index e8d2b7ba4c5..c704241bc90 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -38,6 +38,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ecfa509b98c..02147b1919c 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -30,6 +30,7 @@ target: fle.q a0, a1, a2 fgt.q a0, a1, a2 fge.q a0, a1, a2 + fmv.q a0, a1 fneg.q a0, a1 fabs.q a0, a1 fclass.q a0, a1 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 2da0f7cf0a4..991d4d7a0aa 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -598,7 +598,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -656,7 +656,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -713,7 +713,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements 2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-08 9:51 ` Tsukasa OI 0 siblings, 1 reply; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:49:05 PST (-0800), binutils@sourceware.org wrote: > This commit relaxes requirements to `fmv.s' instructions from F to (F or > Zfinx). The same applies to `fmv.d' and `fmv.q'. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. > * testsuite/gas/riscv/zfinx.d: Likewise. > * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. > * testsuite/gas/riscv/zdinx.d: Likewise. > * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. > * testsuite/gas/riscv/zqinx.s: Likewise. > > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Relax requirements to > `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. > --- > gas/testsuite/gas/riscv/zdinx.d | 1 + > gas/testsuite/gas/riscv/zdinx.s | 1 + > gas/testsuite/gas/riscv/zfinx.d | 1 + > gas/testsuite/gas/riscv/zfinx.s | 1 + > gas/testsuite/gas/riscv/zqinx.d | 1 + > gas/testsuite/gas/riscv/zqinx.s | 1 + > opcodes/riscv-opc.c | 6 +++--- > 7 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d > index cb465bfbef4..3db2cb56f1a 100644 > --- a/gas/testsuite/gas/riscv/zdinx.d > +++ b/gas/testsuite/gas/riscv/zdinx.d > @@ -36,6 +36,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 > +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s > index f44358111de..cdf5f3c2e7e 100644 > --- a/gas/testsuite/gas/riscv/zdinx.s > +++ b/gas/testsuite/gas/riscv/zdinx.s > @@ -28,6 +28,7 @@ target: > fle.d a0, a1, a2 > fgt.d a0, a1, a2 > fge.d a0, a1, a2 > + fmv.d a0, a1 > fneg.d a0, a1 > fabs.d a0, a1 > fclass.d a0, a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d > index 6465c08ea9a..6fc4491fbc0 100644 > --- a/gas/testsuite/gas/riscv/zfinx.d > +++ b/gas/testsuite/gas/riscv/zfinx.d > @@ -34,6 +34,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 > +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s > index 41ae0e38ad4..d63c0c37570 100644 > --- a/gas/testsuite/gas/riscv/zfinx.s > +++ b/gas/testsuite/gas/riscv/zfinx.s > @@ -26,6 +26,7 @@ target: > fle.s a0, a1, a2 > fgt.s a0, a1, a2 > fge.s a0, a1, a2 > + fmv.s a0, a1 > fneg.s a0, a1 > fabs.s a0, a1 > fclass.s a0, a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d > index e8d2b7ba4c5..c704241bc90 100644 > --- a/gas/testsuite/gas/riscv/zqinx.d > +++ b/gas/testsuite/gas/riscv/zqinx.d > @@ -38,6 +38,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 > [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 > +[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 > [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index ecfa509b98c..02147b1919c 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -30,6 +30,7 @@ target: > fle.q a0, a1, a2 > fgt.q a0, a1, a2 > fge.q a0, a1, a2 > + fmv.q a0, a1 > fneg.q a0, a1 > fabs.q a0, a1 > fclass.q a0, a1 Looking at the ISA manual, I'm not actually seeing Zqinx defined. Specifically \begin{commentary} In the future, an RV64Zqinx quad-precision extension could be defined analogously to RV32Zdinx. An RV32Zqinx extension could also be defined but would require quad-register groups. \end{commentary} Looks like it was removed from the ISA manual here 9025a7f Remove Zqinx (for now, at least) I must have missed that when reviewing the patches last time, but not entirely sure what to do as we're about to release it. None of that shouldn't block this patch set, though. > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 2da0f7cf0a4..991d4d7a0aa 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -598,7 +598,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, > {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, > {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, > -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, > +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, > {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, > {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, > {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, > @@ -656,7 +656,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, > {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, > {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, > -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, > +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, > {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, > {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, > {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, > @@ -713,7 +713,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, > {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, > {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, > -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, > +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, > {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, > {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, > {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, Presumably whomever wrote this assumed these were flavors of move, but the ISA manual is pretty clear that they're not Note, FSGNJ.S {\em rx, ry, ry} moves {\em ry} to {\em rx} (assembler pseudoinstruction FMV.S {\em rx, ry}); Thus they're in Zfinx, as they're not explicitly omitted. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Thanks! ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements 2022-02-08 2:00 ` Palmer Dabbelt @ 2022-02-08 9:51 ` Tsukasa OI 0 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-08 9:51 UTC (permalink / raw) To: Palmer Dabbelt; +Cc: Binutils On 2022/02/08 11:00, Palmer Dabbelt wrote: > On Tue, 01 Feb 2022 05:49:05 PST (-0800), binutils@sourceware.org wrote: >> This commit relaxes requirements to `fmv.s' instructions from F to (F or >> Zfinx). The same applies to `fmv.d' and `fmv.q'. >> >> gas/ChangeLog: >> >> * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. >> * testsuite/gas/riscv/zfinx.d: Likewise. >> * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. >> * testsuite/gas/riscv/zdinx.d: Likewise. >> * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. >> * testsuite/gas/riscv/zqinx.s: Likewise. >> >> opcodes/ChangeLog: >> >> * riscv-opc.c (riscv_opcodes): Relax requirements to >> `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. >> --- >> gas/testsuite/gas/riscv/zdinx.d | 1 + >> gas/testsuite/gas/riscv/zdinx.s | 1 + >> gas/testsuite/gas/riscv/zfinx.d | 1 + >> gas/testsuite/gas/riscv/zfinx.s | 1 + >> gas/testsuite/gas/riscv/zqinx.d | 1 + >> gas/testsuite/gas/riscv/zqinx.s | 1 + >> opcodes/riscv-opc.c | 6 +++--- >> 7 files changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d >> index cb465bfbef4..3db2cb56f1a 100644 >> --- a/gas/testsuite/gas/riscv/zdinx.d >> +++ b/gas/testsuite/gas/riscv/zdinx.d >> @@ -36,6 +36,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 >> [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 >> [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 >> +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 >> diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s >> index f44358111de..cdf5f3c2e7e 100644 >> --- a/gas/testsuite/gas/riscv/zdinx.s >> +++ b/gas/testsuite/gas/riscv/zdinx.s >> @@ -28,6 +28,7 @@ target: >> fle.d a0, a1, a2 >> fgt.d a0, a1, a2 >> fge.d a0, a1, a2 >> + fmv.d a0, a1 >> fneg.d a0, a1 >> fabs.d a0, a1 >> fclass.d a0, a1 >> diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d >> index 6465c08ea9a..6fc4491fbc0 100644 >> --- a/gas/testsuite/gas/riscv/zfinx.d >> +++ b/gas/testsuite/gas/riscv/zfinx.d >> @@ -34,6 +34,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 >> [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 >> [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 >> +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 >> diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s >> index 41ae0e38ad4..d63c0c37570 100644 >> --- a/gas/testsuite/gas/riscv/zfinx.s >> +++ b/gas/testsuite/gas/riscv/zfinx.s >> @@ -26,6 +26,7 @@ target: >> fle.s a0, a1, a2 >> fgt.s a0, a1, a2 >> fge.s a0, a1, a2 >> + fmv.s a0, a1 >> fneg.s a0, a1 >> fabs.s a0, a1 >> fclass.s a0, a1 >> diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d >> index e8d2b7ba4c5..c704241bc90 100644 >> --- a/gas/testsuite/gas/riscv/zqinx.d >> +++ b/gas/testsuite/gas/riscv/zqinx.d >> @@ -38,6 +38,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 >> [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 >> [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 >> +[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 >> [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 >> diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s >> index ecfa509b98c..02147b1919c 100644 >> --- a/gas/testsuite/gas/riscv/zqinx.s >> +++ b/gas/testsuite/gas/riscv/zqinx.s >> @@ -30,6 +30,7 @@ target: >> fle.q a0, a1, a2 >> fgt.q a0, a1, a2 >> fge.q a0, a1, a2 >> + fmv.q a0, a1 >> fneg.q a0, a1 >> fabs.q a0, a1 >> fclass.q a0, a1 > > Looking at the ISA manual, I'm not actually seeing Zqinx defined. Specifically > > \begin{commentary} > In the future, an RV64Zqinx quad-precision extension could be defined analogously > to RV32Zdinx. > An RV32Zqinx extension could also be defined but would require > quad-register groups. > \end{commentary} > > Looks like it was removed from the ISA manual here > > 9025a7f Remove Zqinx (for now, at least) > > I must have missed that when reviewing the patches last time, but not entirely sure what to do as we're about to release it. None of that shouldn't block this patch set, though. I'm aware of the status of Zqinx. Still, if Zqinx is going to be ratified, its encoding will be likely the same as the one implemented in GNU Binutils. So my idea for Zqinx is: "fix, then remove temporarily". If we remove Zqinx extension with a single commit, it will be a lot easier to restore once that extension is ratified. Removing Zqinx without destroying current implementation is easy. It's just simple diff as follows: diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 142cd1f0d1f..19649429d01 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1186,7 +1186,6 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, (also, we will also need to remove Zqinx-related testcases) I think we can *cleanly* remove Zqinx extension after we resolve Zfinx issues. I have no objection about removing Zqinx *in the process* resolving Zfinx issues, though. Thanks, Tsukasa > >> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c >> index 2da0f7cf0a4..991d4d7a0aa 100644 >> --- a/opcodes/riscv-opc.c >> +++ b/opcodes/riscv-opc.c >> @@ -598,7 +598,7 @@ const struct riscv_opcode riscv_opcodes[] = >> {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, >> {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, >> {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, >> -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, >> +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, >> @@ -656,7 +656,7 @@ const struct riscv_opcode riscv_opcodes[] = >> {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, >> {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, >> {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, >> -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, >> +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, >> @@ -713,7 +713,7 @@ const struct riscv_opcode riscv_opcodes[] = >> {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, >> {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, >> {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, >> -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, >> {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, > > Presumably whomever wrote this assumed these were flavors of move, but the ISA manual is pretty clear that they're not > > Note, FSGNJ.S {\em rx, ry, ry} moves {\em ry} to {\em rx} (assembler pseudoinstruction FMV.S {\em rx, ry}); > > Thus they're in Zfinx, as they're not explicitly omitted. > > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> > > Thanks! > ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI ` (3 preceding siblings ...) 2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI @ 2022-02-01 13:49 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI ` (3 subsequent siblings) 8 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:49 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit ensures that all FP128 register numbers to be even because RV64_Zqinx would require it. gas/ChangeLog: * testsuite/gas/riscv/zqinx.s: Make register numbers even. * testsuite/gas/riscv/zqinx.d: Likewise. --- gas/testsuite/gas/riscv/zqinx.d | 70 ++++++++++++++++----------------- gas/testsuite/gas/riscv/zqinx.s | 70 ++++++++++++++++----------------- 2 files changed, 70 insertions(+), 70 deletions(-) diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c704241bc90..52b5445d010 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,38 +7,38 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 02147b1919c..2dc2a7c1483 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,36 +1,36 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a1 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fmv.q a0, a1 - fneg.q a0, a1 - fabs.q a0, a1 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fsub.q a0, a2, a4 + fmul.q a0, a2, a4 + fdiv.q a0, a2, a4 + fsqrt.q a0, a2 + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6 + fcvt.w.q a0, a2 + fcvt.wu.q a0, a2 + fcvt.l.q a0, a2 + fcvt.lu.q a0, a2 + fcvt.s.q a0, a2 + fcvt.d.q a0, a2 + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.lu a0, a2 + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs 2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:49:06 PST (-0800), binutils@sourceware.org wrote: > This commit ensures that all FP128 register numbers to be even because > RV64_Zqinx would require it. > > gas/ChangeLog: > > * testsuite/gas/riscv/zqinx.s: Make register numbers even. > * testsuite/gas/riscv/zqinx.d: Likewise. > --- > gas/testsuite/gas/riscv/zqinx.d | 70 ++++++++++++++++----------------- > gas/testsuite/gas/riscv/zqinx.s | 70 ++++++++++++++++----------------- > 2 files changed, 70 insertions(+), 70 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d > index c704241bc90..52b5445d010 100644 > --- a/gas/testsuite/gas/riscv/zqinx.d > +++ b/gas/testsuite/gas/riscv/zqinx.d > @@ -7,38 +7,38 @@ > Disassembly of section .text: > > 0+000 <target>: > -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 > -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 > -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 > -[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 > -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 > diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s > index 02147b1919c..2dc2a7c1483 100644 > --- a/gas/testsuite/gas/riscv/zqinx.s > +++ b/gas/testsuite/gas/riscv/zqinx.s > @@ -1,36 +1,36 @@ > target: > - fadd.q a0, a1, a2 > - fsub.q a0, a1, a2 > - fmul.q a0, a1, a2 > - fdiv.q a0, a1, a2 > - fsqrt.q a0, a1 > - fmin.q a0, a1, a2 > - fmax.q a0, a1, a2 > - fmadd.q a0, a1, a2, a3 > - fnmadd.q a0, a1, a2, a3 > - fmsub.q a0, a1, a2, a3 > - fnmsub.q a0, a1, a2, a3 > - fcvt.w.q a0, a1 > - fcvt.wu.q a0, a1 > - fcvt.l.q a0, a1 > - fcvt.lu.q a0, a1 > - fcvt.s.q a0, a1 > - fcvt.d.q a0, a1 > - fcvt.q.s a0, a1 > - fcvt.q.d a0, a1 > - fcvt.q.w a0, a1 > - fcvt.q.wu a0, a1 > - fcvt.q.l a0, a1 > - fcvt.q.lu a0, a1 > - fsgnj.q a0, a1, a2 > - fsgnjn.q a0, a1, a2 > - fsgnjx.q a0, a1, a2 > - feq.q a0, a1, a2 > - flt.q a0, a1, a2 > - fle.q a0, a1, a2 > - fgt.q a0, a1, a2 > - fge.q a0, a1, a2 > - fmv.q a0, a1 > - fneg.q a0, a1 > - fabs.q a0, a1 > - fclass.q a0, a1 > + fadd.q a0, a2, a4 > + fsub.q a0, a2, a4 > + fmul.q a0, a2, a4 > + fdiv.q a0, a2, a4 > + fsqrt.q a0, a2 > + fmin.q a0, a2, a4 > + fmax.q a0, a2, a4 > + fmadd.q a0, a2, a4, a6 > + fnmadd.q a0, a2, a4, a6 > + fmsub.q a0, a2, a4, a6 > + fnmsub.q a0, a2, a4, a6 > + fcvt.w.q a0, a2 > + fcvt.wu.q a0, a2 > + fcvt.l.q a0, a2 > + fcvt.lu.q a0, a2 > + fcvt.s.q a0, a2 > + fcvt.d.q a0, a2 > + fcvt.q.s a0, a2 > + fcvt.q.d a0, a2 > + fcvt.q.w a0, a2 > + fcvt.q.wu a0, a2 > + fcvt.q.l a0, a2 > + fcvt.q.lu a0, a2 > + fsgnj.q a0, a2, a4 > + fsgnjn.q a0, a2, a4 > + fsgnjx.q a0, a2, a4 > + feq.q a0, a2, a4 > + flt.q a0, a2, a4 > + fle.q a0, a2, a4 > + fgt.q a0, a2, a4 > + fge.q a0, a2, a4 > + fmv.q a0, a2 > + fneg.q a0, a2 > + fabs.q a0, a2 > + fclass.q a0, a2 Aside from the previous Zqinx issues Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Thanks! ^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI ` (4 preceding siblings ...) 2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI @ 2022-02-01 13:51 ` Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI ` (2 more replies) 2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI ` (2 subsequent siblings) 8 siblings, 3 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:51 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils [About this patchset] This is the Part 2A (part 2 option A) of my Z[fdq]inx fixes and enhancements. See Part 1 for general background. <https://sourceware.org/pipermail/binutils/2022-February/119570.html> There is also Part 2B (part 2 option B) I will submit later to fix the same bug but I prefer option A. See below for details. [Bugfix in Part 2] On RV32_Zdinx and RV[32|64]_Zqinx, there is a bug that allows invalid Zdinx/Zqinx instructions to be emitted and/or disassembled. GNU Assembler accepts all register index (as long as encodable) but on Zdinx extension + RV32, all FP64 register numbers must be even (encoding with odd register numbers is reserved). For instance, this is valid on RV64_Zdinx but not on RV32_Zdinx. fadd.d a1, a3, a5 On the other hand, this is valid both on RV[32|64]_Zdinx. fadd.d a0, a2, a4 Although not ratified, Zqinx would require similar constraints (register pairs and quad-register groups) as the ISA Manual draft, section 24.5 says: > In the future, an RV64Zqinx quad-precision extension could be defined > analogously to RV32Zdinx. An RV32Zqinx extension could also be > defined but would require quad-register groups. [Option A and B] To address this issue (at least in the disassembler), we need to modify instruction match functions to reject invalid encodings. However, because whether given Zdinx/Zqinx instruction is valid depends on XLEN and matching extension (D/Q or Zdinx/Zqinx), current `match_func' with current instruction list cannot handle this situation. We have two options (as I came up with): ** PART 2A (OPTION A) ** 1. Separate D/Q and Zdinx/Zqinx completely and split Zdinx/Zqinx per XLEN (because whether given Zdinx/Zqinx instruction is valid depends on the XLEN). For instance, {"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, ... , 0 }, in riscv_opcodes may be splitted to: {"fadd.d", 0, INSN_CLASS_D, ... , 0 }, {"fadd.d", 32, INSN_CLASS_ZDINX, ... , 0 }, {"fadd.d", 64, INSN_CLASS_ZDINX, ... , 0 }, to preserve current `match_func' interface simplicity. We also need 16 new matching functions: - match_opcode_zdinx_rtype_g2 - match_opcode_zdinx_rtype_g4 For regular arithmetic instructions (rd, rs1 and rs2 are checked) - match_rs1_eq_rs2_zdinx_rtype_g2 - match_rs1_eq_rs2_zdinx_rtype_g4 For fmv, fneg and fabs pseudoinstructions (rd and rs1[==rs2] are checked). - match_opcode_zdinx_r4type_g2 - match_opcode_zdinx_r4type_g4 For FMA instructions (rd and rs1..3 are checked) - match_opcode_zdinx_itype_g1_2 - match_opcode_zdinx_itype_g1_4 - match_opcode_zdinx_itype_g2_1 - match_opcode_zdinx_itype_g2_4 - match_opcode_zdinx_itype_g4_1 - match_opcode_zdinx_itype_g4_2 Mainly for fcvt instructions (rd and rs1 are checked). - match_opcode_zdinx_itype_g2_2 - match_opcode_zdinx_itype_g4_4 For fsqrt instructions (rd and rs1 are checked). - match_opcode_zdinx_cmp_g2 - match_opcode_zdinx_cmp_g4 For compare instructions (rs1 and rs2 are checked) Downside of this is: - It almost triples D/Q riscv_opcodes entries. This is bloat. - We need separate Zdinx/Zqinx entries per XLEN (new riscv_opcodes entries will be required for RV128_Z[dq]inx). - We cannot give proper diagnostics as an assembler error (other than simple "illegal operands") because we purely handle this issue with general-purpose matching functions. ** PART 2B (OPTION B) ** 2. Pass additional information If we prefer to give proper diagnostics in the assembler, we definitely need additional flags holding floating type information on each instruction and we need to validate all floating point register operands using those information. For assembler part, this is done in the Part 2B but... this part doesn't handle disassembler issue (unlike Part 2A). To address disassembler issue, we ADDITIONALLY need to add some arguments to `match_func' (RISC-V subset [riscv_parse_subset_t] and XLEN) and add some matching functions (like Part 2A but the number of new matching functions would be less) for Zdinx/Zqinx instructions. The big problem of this approach is bloat (in an other way than Part 2A) and redundant design. Why do we need to pass riscv_rps_dis/riscv_rps_as just for Zdinx/Zqinx instructions? Why do we need to check xlen twice? That's why I stopped before tackling with the disassembler issue. [Opinion (submitter prefers option A)] So my opinion is..., unless RISC-V maintainers prefer option B, option A would be better and complete. I would like to hear thoughts of RISC-V people. Tsukasa OI (2): RISC-V: Prepare D/Q and Zdinx/Zqinx separation RISC-V: Validate Zdinx/Zqinx register pairs bfd/elfxx-riscv.c | 10 +- include/opcode/riscv.h | 4 +- opcodes/riscv-opc.c | 541 +++++++++++++++++++++++++++++++++-------- 3 files changed, 441 insertions(+), 114 deletions(-) base-commit: e327c35ef5768789d3ba41a629f178f5eec32790 prerequisite-patch-id: 9e408f2e6186c8956aae077daf95f38b9ad98675 prerequisite-patch-id: 32ea143f7662a3297a7cf809cec6454e788f2916 prerequisite-patch-id: 25d5aa65f72b1b4f1f52c92aa0f8ac30d218cc9c prerequisite-patch-id: 6599ccdcc15585db285c30e14528f905327fd638 prerequisite-patch-id: a5f3689afda87a68d4faae698c438aa3211521e0 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation 2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI @ 2022-02-01 13:51 ` Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt 2 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:51 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit renames instruction class names for Zdinx/Zqinx to prepare separation between D/Q and Zdinx/Zqinx. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect renamed instruction classes. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Rename INSN_CLASS_D_OR_ZDINX to INSN_CLASS_ZDINX, INSN_CLASS_Q_OR_ZQINX to INSN_CLASS_ZQINX. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Reflect renamed instruction classes. --- bfd/elfxx-riscv.c | 4 +- include/opcode/riscv.h | 4 +- opcodes/riscv-opc.c | 202 ++++++++++++++++++++--------------------- 3 files changed, 105 insertions(+), 105 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 9f52bb545ac..190908d6f86 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2358,10 +2358,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_F_OR_ZFINX: return (riscv_subset_supports (rps, "f") || riscv_subset_supports (rps, "zfinx")); - case INSN_CLASS_D_OR_ZDINX: + case INSN_CLASS_ZDINX: return (riscv_subset_supports (rps, "d") || riscv_subset_supports (rps, "zdinx")); - case INSN_CLASS_Q_OR_ZQINX: + case INSN_CLASS_ZQINX: return (riscv_subset_supports (rps, "q") || riscv_subset_supports (rps, "zqinx")); case INSN_CLASS_ZBA: diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 048ab0a5d68..f44987d8c10 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,8 +368,8 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 991d4d7a0aa..6c738ddb5df 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -656,117 +656,117 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{"fsgnjn.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{"fsgnjx.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fmin.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{"fmax.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fcvt.d.w", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fclass.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{"feq.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{"flt.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fle.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fgt.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fge.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, /* Quad-precision floating-point instruction subset. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, +{"fsgnjn.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, +{"fsgnjx.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, +{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, +{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, +{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, +{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, +{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, +{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, +{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, +{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, +{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, +{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, +{"fmin.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, +{"fmax.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, +{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, +{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, +{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, +{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, +{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, +{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, +{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, +{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, +{"fcvt.q.w", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, +{"fcvt.q.wu", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.q.s", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, +{"fcvt.q.d", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, +{"fclass.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, +{"feq.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, +{"flt.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{"fle.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fgt.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{"fge.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, {"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, {"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs 2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI @ 2022-02-01 13:51 ` Tsukasa OI 2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt 2 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:51 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds floating point register number validation on Zdinx/Zqinx extensions by separating handling on D/Q and Zdinx/Zqinx extensions (per-xlen on Zdinx/Zqinx). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Change meanings of renamed instruction classes. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new matching functions. --- bfd/elfxx-riscv.c | 6 +- opcodes/riscv-opc.c | 525 +++++++++++++++++++++++++++++++++++--------- 2 files changed, 429 insertions(+), 102 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 190908d6f86..142cd1f0d1f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2359,11 +2359,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return (riscv_subset_supports (rps, "f") || riscv_subset_supports (rps, "zfinx")); case INSN_CLASS_ZDINX: - return (riscv_subset_supports (rps, "d") - || riscv_subset_supports (rps, "zdinx")); + return riscv_subset_supports (rps, "zdinx"); case INSN_CLASS_ZQINX: - return (riscv_subset_supports (rps, "q") - || riscv_subset_supports (rps, "zqinx")); + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6c738ddb5df..418357dedc9 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -630,7 +771,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, {"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, {"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, +{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 }, {"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, {"fclass.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, {"feq.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, @@ -644,10 +785,11 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -656,117 +798,304 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, 0 }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, 0 }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, 0 }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, 0 }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, 0 }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, 0 }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, 0 }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, 0 }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, 0 }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, 0 }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, 0 }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, {"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, {"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, {"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, {"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, {"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, {"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, {"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, -/* Quad-precision floating-point instruction subset. */ +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, 0 }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, 0 }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, 0 }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, 0 }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, 0 }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, 0 }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, 0 }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, 0 }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, 0 }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, 0 }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, 0 }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, 0 }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, 0 }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, 0 }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, 0 }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, 0 }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, 0 }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, 0 }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, 0 }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, 0 }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, 0 }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, 0 }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, 0 }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, 0 }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, 0 }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, 0 }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, 0 }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, 0 }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, 0 }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, 0 }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, 0 }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, 0 }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, 0 }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, 0 }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, 0 }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, 0 }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, 0 }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, 0 }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, 0 }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, 0 }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, 0 }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, 0 }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, 0 }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, 0 }, {"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, {"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, 0 }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A 2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 2 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:51:12 PST (-0800), binutils@sourceware.org wrote: > [About this patchset] > > This is the Part 2A (part 2 option A) of my Z[fdq]inx fixes and > enhancements. See Part 1 for general background. > > <https://sourceware.org/pipermail/binutils/2022-February/119570.html> > > There is also Part 2B (part 2 option B) I will submit later to fix the > same bug but I prefer option A. See below for details. > > > > > [Bugfix in Part 2] > > On RV32_Zdinx and RV[32|64]_Zqinx, there is a bug that allows invalid > Zdinx/Zqinx instructions to be emitted and/or disassembled. > > GNU Assembler accepts all register index (as long as encodable) but > on Zdinx extension + RV32, all FP64 register numbers must be even > (encoding with odd register numbers is reserved). > > For instance, this is valid on RV64_Zdinx but not on RV32_Zdinx. > > fadd.d a1, a3, a5 > > On the other hand, this is valid both on RV[32|64]_Zdinx. > > fadd.d a0, a2, a4 > > Although not ratified, Zqinx would require similar constraints (register > pairs and quad-register groups) as the ISA Manual draft, > section 24.5 says: > >> In the future, an RV64Zqinx quad-precision extension could be defined >> analogously to RV32Zdinx. An RV32Zqinx extension could also be >> defined but would require quad-register groups. > > > > > [Option A and B] > > To address this issue (at least in the disassembler), we need to modify > instruction match functions to reject invalid encodings. However, > because whether given Zdinx/Zqinx instruction is valid depends on XLEN > and matching extension (D/Q or Zdinx/Zqinx), current `match_func' with > current instruction list cannot handle this situation. > > We have two options (as I came up with): > > > ** PART 2A (OPTION A) ** > 1. Separate D/Q and Zdinx/Zqinx completely and split Zdinx/Zqinx per > XLEN (because whether given Zdinx/Zqinx instruction is valid depends > on the XLEN). > > For instance, > > {"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, ... , 0 }, > > in riscv_opcodes may be splitted to: > > {"fadd.d", 0, INSN_CLASS_D, ... , 0 }, > {"fadd.d", 32, INSN_CLASS_ZDINX, ... , 0 }, > {"fadd.d", 64, INSN_CLASS_ZDINX, ... , 0 }, > > to preserve current `match_func' interface simplicity. > > We also need 16 new matching functions: > > - match_opcode_zdinx_rtype_g2 > - match_opcode_zdinx_rtype_g4 > For regular arithmetic instructions (rd, rs1 and rs2 are checked) > - match_rs1_eq_rs2_zdinx_rtype_g2 > - match_rs1_eq_rs2_zdinx_rtype_g4 > For fmv, fneg and fabs pseudoinstructions > (rd and rs1[==rs2] are checked). > - match_opcode_zdinx_r4type_g2 > - match_opcode_zdinx_r4type_g4 > For FMA instructions (rd and rs1..3 are checked) > - match_opcode_zdinx_itype_g1_2 > - match_opcode_zdinx_itype_g1_4 > - match_opcode_zdinx_itype_g2_1 > - match_opcode_zdinx_itype_g2_4 > - match_opcode_zdinx_itype_g4_1 > - match_opcode_zdinx_itype_g4_2 > Mainly for fcvt instructions (rd and rs1 are checked). > - match_opcode_zdinx_itype_g2_2 > - match_opcode_zdinx_itype_g4_4 > For fsqrt instructions (rd and rs1 are checked). > - match_opcode_zdinx_cmp_g2 > - match_opcode_zdinx_cmp_g4 > For compare instructions (rs1 and rs2 are checked) > > Downside of this is: > > - It almost triples D/Q riscv_opcodes entries. This is bloat. > - We need separate Zdinx/Zqinx entries per XLEN (new riscv_opcodes > entries will be required for RV128_Z[dq]inx). > - We cannot give proper diagnostics as an assembler error > (other than simple "illegal operands") because we purely handle this > issue with general-purpose matching functions. > > > ** PART 2B (OPTION B) ** > 2. Pass additional information > > If we prefer to give proper diagnostics in the assembler, we definitely > need additional flags holding floating type information on each > instruction and we need to validate all floating point register operands > using those information. > > For assembler part, this is done in the Part 2B but... this part doesn't > handle disassembler issue (unlike Part 2A). > > To address disassembler issue, we ADDITIONALLY need to add some > arguments to `match_func' (RISC-V subset [riscv_parse_subset_t] and > XLEN) and add some matching functions (like Part 2A but the number of > new matching functions would be less) for Zdinx/Zqinx instructions. > > The big problem of this approach is bloat (in an other way than Part 2A) > and redundant design. > > Why do we need to pass riscv_rps_dis/riscv_rps_as just for Zdinx/Zqinx > instructions? Why do we need to check xlen twice? That's why I stopped > before tackling with the disassembler issue. > > > > > [Opinion (submitter prefers option A)] > > So my opinion is..., unless RISC-V maintainers prefer option B, option A > would be better and complete. I would like to hear thoughts of RISC-V > people. I'm fine with the version you have here. At least a bit of the complexity could be removed by dropping Zqinx, but given that it's been written it doesn't seem so bad to me if we decide to keep it around. > > > > > Tsukasa OI (2): > RISC-V: Prepare D/Q and Zdinx/Zqinx separation > RISC-V: Validate Zdinx/Zqinx register pairs > > bfd/elfxx-riscv.c | 10 +- > include/opcode/riscv.h | 4 +- > opcodes/riscv-opc.c | 541 +++++++++++++++++++++++++++++++++-------- > 3 files changed, 441 insertions(+), 114 deletions(-) > > > base-commit: e327c35ef5768789d3ba41a629f178f5eec32790 > prerequisite-patch-id: 9e408f2e6186c8956aae077daf95f38b9ad98675 > prerequisite-patch-id: 32ea143f7662a3297a7cf809cec6454e788f2916 > prerequisite-patch-id: 25d5aa65f72b1b4f1f52c92aa0f8ac30d218cc9c > prerequisite-patch-id: 6599ccdcc15585db285c30e14528f905327fd638 > prerequisite-patch-id: a5f3689afda87a68d4faae698c438aa3211521e0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI ` (5 preceding siblings ...) 2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI @ 2022-02-01 13:52 ` Tsukasa OI 2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI 2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI 8 siblings, 2 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:52 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils [About this patchset] This is the Part 2B (part 2 option B) of my Z[fdq]inx fixes and enhancements. See Part 1 for general background and Part 2A for the issue this patchset tries to fix. <https://sourceware.org/pipermail/binutils/2022-February/119570.html> (Part 1) <https://sourceware.org/pipermail/binutils/2022-February/119576.html> (Part 2A) Tsukasa OI (2): RISC-V: Add floating point instruction metadata RISC-V: Validate Zdinx/Zqinx register pairs gas/config/tc-riscv.c | 65 ++++- include/opcode/riscv.h | 19 ++ opcodes/riscv-opc.c | 522 ++++++++++++++++++++--------------------- 3 files changed, 339 insertions(+), 267 deletions(-) base-commit: e327c35ef5768789d3ba41a629f178f5eec32790 prerequisite-patch-id: 9e408f2e6186c8956aae077daf95f38b9ad98675 prerequisite-patch-id: 32ea143f7662a3297a7cf809cec6454e788f2916 prerequisite-patch-id: 25d5aa65f72b1b4f1f52c92aa0f8ac30d218cc9c prerequisite-patch-id: 6599ccdcc15585db285c30e14528f905327fd638 prerequisite-patch-id: a5f3689afda87a68d4faae698c438aa3211521e0 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata 2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI @ 2022-02-01 13:52 ` Tsukasa OI 2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 1 sibling, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:52 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils To validate register numbers on RV32_Zdinx, we need new flags to represent floating point operand types. include/ChangeLog: * opcode/riscv.h (INSN_FLOAT, INSN_FLOAT_S, INSN_FLOAT_D, INSN_FLOAT_Q, INSN_FLOAT_VAR, INSN_FCVT_DST, INSN_FCVT_DST_S, INSN_FCVT_DST_D, INSN_FCVT_DST_Q, INSN_FCVT_SRC, INSN_FCVT_SRC_S, INSN_FCVT_SRC_D, INSN_FCVT_SRC_Q, INSN_FCVT_SRC_SHIFT, INSN_FCVT_F_F): New macros for floating point operand types. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add floating point operand types. --- include/opcode/riscv.h | 19 ++ opcodes/riscv-opc.c | 522 ++++++++++++++++++++--------------------- 2 files changed, 280 insertions(+), 261 deletions(-) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 048ab0a5d68..0154f78fa8d 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -458,6 +458,25 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has floating type operand(s). */ +#define INSN_FLOAT 0x00000180 +#define INSN_FLOAT_S 0x00000080 +#define INSN_FLOAT_D 0x00000100 +#define INSN_FLOAT_Q 0x00000180 +#define INSN_FLOAT_VAR 0x00000800 /* variable (vector or custom) */ + +/* Instruction is a floating to floating type conversion. */ +#define INSN_FCVT_DST INSN_FLOAT +#define INSN_FCVT_DST_S INSN_FLOAT_S +#define INSN_FCVT_DST_D INSN_FLOAT_D +#define INSN_FCVT_DST_Q INSN_FLOAT_Q +#define INSN_FCVT_SRC 0x00000600 +#define INSN_FCVT_SRC_S 0x00000200 +#define INSN_FCVT_SRC_D 0x00000400 +#define INSN_FCVT_SRC_Q 0x00000600 +#define INSN_FCVT_SRC_SHIFT 2 +#define INSN_FCVT_F_F 0x00001000 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 991d4d7a0aa..445da6d7077 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -586,187 +586,187 @@ const struct riscv_opcode riscv_opcodes[] = {"fsflags", 0, INSN_CLASS_F, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, {"fsflagsi", 0, INSN_CLASS_F, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, {"fsflagsi", 0, INSN_CLASS_F, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, -{"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, {"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, -{"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, -{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, -{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, -{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, -{"fsgnjn.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, -{"fsgnjx.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, -{"fadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 }, -{"fadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, -{"fsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 }, -{"fsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, -{"fmul.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 }, -{"fmul.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, -{"fdiv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 }, -{"fdiv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, -{"fsqrt.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 }, -{"fsqrt.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, -{"fmin.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, -{"fmax.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, -{"fmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 }, -{"fmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, -{"fnmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 }, -{"fnmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, -{"fmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 }, -{"fmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, -{"fnmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 }, -{"fnmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, -{"fcvt.w.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 }, -{"fcvt.w.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, -{"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, -{"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, -{"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, -{"fclass.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, -{"feq.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, -{"flt.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, -{"fle.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, -{"fgt.s", 0, INSN_CLASS_F_OR_ZFINX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, -{"fge.s", 0, INSN_CLASS_F_OR_ZFINX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, -{"fcvt.l.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 }, -{"fcvt.l.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, -{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, -{"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, -{"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, +{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, INSN_FLOAT_S }, +{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, INSN_FLOAT_S }, +{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, INSN_FLOAT_S }, +{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, INSN_FLOAT_S }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_S }, +{"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_S }, +{"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_S }, +{"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, INSN_FLOAT_S }, +{"fsgnjn.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, INSN_FLOAT_S }, +{"fsgnjx.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, INSN_FLOAT_S }, +{"fadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, INSN_FLOAT_S }, +{"fsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, INSN_FLOAT_S }, +{"fmul.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fmul.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, INSN_FLOAT_S }, +{"fdiv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fdiv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, INSN_FLOAT_S }, +{"fsqrt.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fsqrt.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, INSN_FLOAT_S }, +{"fmin.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, INSN_FLOAT_S }, +{"fmax.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, INSN_FLOAT_S }, +{"fmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, INSN_FLOAT_S }, +{"fnmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fnmadd.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, INSN_FLOAT_S }, +{"fmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, INSN_FLOAT_S }, +{"fnmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fnmsub.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, INSN_FLOAT_S }, +{"fcvt.w.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.w.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, INSN_FLOAT_S }, +{"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, INSN_FLOAT_S }, +{"fclass.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, INSN_FLOAT_S }, +{"feq.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, INSN_FLOAT_S }, +{"flt.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, INSN_FLOAT_S }, +{"fle.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, INSN_FLOAT_S }, +{"fgt.s", 0, INSN_CLASS_F_OR_ZFINX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, INSN_FLOAT_S }, +{"fge.s", 0, INSN_CLASS_F_OR_ZFINX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, INSN_FLOAT_S }, +{"fcvt.l.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.l.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, INSN_FLOAT_S }, +{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, INSN_FLOAT_S }, +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, INSN_FLOAT_S }, /* Double-precision floating-point instruction subset. */ -{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, {"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, -{"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, -{"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_D }, +{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_D }, +{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_D }, +{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_FLOAT_D }, +{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_FLOAT_D }, +{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_FLOAT_D }, +{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_FLOAT_D }, +{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_FLOAT_D }, +{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_FLOAT_D }, +{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_FLOAT_D }, +{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_FLOAT_D }, +{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_FLOAT_D }, +{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_FLOAT_D }, +{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_FLOAT_D }, +{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_FLOAT_D }, +{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_FLOAT_D }, +{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_FLOAT_D }, +{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_FLOAT_D }, +{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_D|INSN_FCVT_SRC_S }, +{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_S|INSN_FCVT_SRC_D }, +{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_S|INSN_FCVT_SRC_D }, +{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_FLOAT_D }, +{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_FLOAT_D }, +{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_FLOAT_D }, +{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_FLOAT_D }, +{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_FLOAT_D }, +{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_FLOAT_D }, +{"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, INSN_FLOAT_D }, +{"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, INSN_FLOAT_D }, +{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_FLOAT_D }, +{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_FLOAT_D }, +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_FLOAT_D }, /* Quad-precision floating-point instruction subset. */ -{"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE|INSN_FLOAT_Q }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, -{"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE|INSN_FLOAT_Q }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, -{"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_Q }, +{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_Q }, +{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_FLOAT_Q }, +{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_FLOAT_Q }, +{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_FLOAT_Q }, +{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_FLOAT_Q }, +{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_FLOAT_Q }, +{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_FLOAT_Q }, +{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_FLOAT_Q }, +{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_FLOAT_Q }, +{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_FLOAT_Q }, +{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_FLOAT_Q }, +{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_FLOAT_Q }, +{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_FLOAT_Q }, +{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_FLOAT_Q }, +{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_FLOAT_Q }, +{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_FLOAT_Q }, +{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_FLOAT_Q }, +{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_Q|INSN_FCVT_SRC_S }, +{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_Q|INSN_FCVT_SRC_D }, +{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_S|INSN_FCVT_SRC_Q }, +{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_S|INSN_FCVT_SRC_Q }, +{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_D|INSN_FCVT_SRC_Q }, +{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_FCVT_F_F|INSN_FCVT_DST_D|INSN_FCVT_SRC_Q }, +{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_FLOAT_Q }, +{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_FLOAT_Q }, +{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_FLOAT_Q }, +{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_FLOAT_Q }, +{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_FLOAT_Q }, +{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_FLOAT_Q }, +{"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, INSN_FLOAT_Q }, +{"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, INSN_FLOAT_Q }, +{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_FLOAT_Q }, +{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_FLOAT_Q }, +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_FLOAT_Q }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, @@ -808,14 +808,14 @@ const struct riscv_opcode riscv_opcodes[] = {"c.ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"c.sdsp", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, {"c.sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fldsp", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fsdsp", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.flwsp", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.fldsp", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"c.fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"c.fsdsp", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"c.fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE|INSN_FLOAT_D }, +{"c.flwsp", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"c.flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, +{"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE|INSN_FLOAT_S }, /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR,"d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, @@ -1560,30 +1560,30 @@ const struct riscv_opcode riscv_opcodes[] = {"vfwmul.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0}, {"vfmadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0}, -{"vfmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0}, +{"vfmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, INSN_FLOAT_VAR}, {"vfnmadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0}, -{"vfnmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0}, +{"vfnmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, INSN_FLOAT_VAR}, {"vfmsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0}, -{"vfmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0}, +{"vfmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, INSN_FLOAT_VAR}, {"vfnmsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0}, -{"vfnmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0}, +{"vfnmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, INSN_FLOAT_VAR}, {"vfmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0}, -{"vfmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0}, +{"vfmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, INSN_FLOAT_VAR}, {"vfnmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0}, -{"vfnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0}, +{"vfnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, INSN_FLOAT_VAR}, {"vfmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0}, -{"vfmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0}, +{"vfmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, INSN_FLOAT_VAR}, {"vfnmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0}, -{"vfnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0}, +{"vfnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, INSN_FLOAT_VAR}, {"vfwmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0}, -{"vfwmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0}, +{"vfwmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, INSN_FLOAT_VAR}, {"vfwnmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0}, -{"vfwnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0}, +{"vfwnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, INSN_FLOAT_VAR}, {"vfwmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0}, -{"vfwmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0}, +{"vfwmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, INSN_FLOAT_VAR}, {"vfwnmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0}, -{"vfwnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0}, +{"vfwnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, INSN_FLOAT_VAR}, {"vfsqrt.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0}, {"vfrsqrt7.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_opcode, 0}, @@ -1622,8 +1622,8 @@ const struct riscv_opcode riscv_opcodes[] = {"vmfgt.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS}, {"vmfge.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS}, -{"vfmerge.vfm",0, INSN_CLASS_ZVEF, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0}, -{"vfmv.v.f", 0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 }, +{"vfmerge.vfm",0, INSN_CLASS_ZVEF, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, INSN_FLOAT_VAR}, +{"vfmv.v.f", 0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, INSN_FLOAT_VAR }, {"vfcvt.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0}, {"vfcvt.x.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0}, @@ -1700,8 +1700,8 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0}, {"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0}, -{"vfmv.f.s", 0, INSN_CLASS_ZVEF, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0}, -{"vfmv.s.f", 0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0}, +{"vfmv.f.s", 0, INSN_CLASS_ZVEF, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, INSN_FLOAT_VAR}, +{"vfmv.s.f", 0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, INSN_FLOAT_VAR}, {"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0}, {"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0}, @@ -1762,105 +1762,105 @@ const struct riscv_opcode riscv_insn_types[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ {"r", 0, INSN_CLASS_I, "O4,F3,F7,d,s,t", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,t", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,t", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,t", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,s,T", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,t", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,t", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,t", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,s,T", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,T", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, -{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"r4", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, -{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"i", 0, INSN_CLASS_I, "O4,F3,d,s,j", 0, 0, match_opcode, 0 }, -{"i", 0, INSN_CLASS_F, "O4,F3,D,s,j", 0, 0, match_opcode, 0 }, -{"i", 0, INSN_CLASS_F, "O4,F3,d,S,j", 0, 0, match_opcode, 0 }, -{"i", 0, INSN_CLASS_F, "O4,F3,D,S,j", 0, 0, match_opcode, 0 }, +{"i", 0, INSN_CLASS_F, "O4,F3,D,s,j", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"i", 0, INSN_CLASS_F, "O4,F3,d,S,j", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"i", 0, INSN_CLASS_F, "O4,F3,D,S,j", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"i", 0, INSN_CLASS_I, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 }, -{"i", 0, INSN_CLASS_F, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 }, +{"i", 0, INSN_CLASS_F, "O4,F3,D,o(s)", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"s", 0, INSN_CLASS_I, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 }, -{"s", 0, INSN_CLASS_F, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 }, +{"s", 0, INSN_CLASS_F, "O4,F3,T,q(s)", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"sb", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, -{"sb", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, -{"sb", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, -{"sb", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, +{"sb", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"sb", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"sb", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"b", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, -{"b", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, -{"b", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, -{"b", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, +{"b", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"b", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"b", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"u", 0, INSN_CLASS_I, "O4,d,u", 0, 0, match_opcode, 0 }, -{"u", 0, INSN_CLASS_F, "O4,D,u", 0, 0, match_opcode, 0 }, +{"u", 0, INSN_CLASS_F, "O4,D,u", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"uj", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 }, -{"uj", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 }, +{"uj", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"j", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 }, -{"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 }, +{"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"cr", 0, INSN_CLASS_C, "O2,CF4,d,CV", 0, 0, match_opcode, 0 }, -{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CV", 0, 0, match_opcode, 0 }, +{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CV", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,d,CT", 0, 0, match_opcode, 0 }, -{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CT", 0, 0, match_opcode, 0 }, +{"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CT", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"ci", 0, INSN_CLASS_C, "O2,CF3,d,Co", 0, 0, match_opcode, 0 }, -{"ci", 0, INSN_CLASS_F_AND_C, "O2,CF3,D,Co", 0, 0, match_opcode, 0 }, +{"ci", 0, INSN_CLASS_F_AND_C, "O2,CF3,D,Co", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"ciw", 0, INSN_CLASS_C, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 }, -{"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 }, +{"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"css", 0, INSN_CLASS_C, "O2,CF3,CV,C6", 0, 0, match_opcode, 0 }, -{"css", 0, INSN_CLASS_F_AND_C, "O2,CF3,CT,C6", 0, 0, match_opcode, 0 }, +{"css", 0, INSN_CLASS_F_AND_C, "O2,CF3,CT,C6", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"cl", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 }, -{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 }, -{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 }, -{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 }, +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"cs", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 }, -{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 }, -{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 }, -{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 }, +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"ca", 0, INSN_CLASS_C, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 }, -{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 }, -{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 }, -{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode, 0 }, +{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, INSN_FLOAT_VAR }, +{"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"cb", 0, INSN_CLASS_C, "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 }, -{"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 }, +{"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, INSN_FLOAT_VAR }, {"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, match_opcode, 0 }, -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs 2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI 2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI @ 2022-02-01 13:52 ` Tsukasa OI 1 sibling, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:52 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds floating point register validation on Zdinx/Zqinx extensions enabled. Assembler only. gas/ChangeLog: * config/tc-riscv.c (reg_lookup_fp): New function to look up and validate floating point register operands. (riscv_ip): Use `reg_lookup_fp' to look up FPRs. --- gas/config/tc-riscv.c | 65 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 59 insertions(+), 6 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 25908597436..bfb2f94b061 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2137,6 +2137,61 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) return false; } +/* Look up floating point register and validate against operand type. + This function checks invalid register such as "x1" on a FP64 operand + in RV32_Zdinx. */ + +static bool +reg_lookup_fp (char operand, char **str, + struct riscv_opcode *insn, unsigned int *regno) +{ + bool is_zfinx = riscv_subset_supports (&riscv_rps_as, "zfinx"); + unsigned int float_size = insn->pinfo & INSN_FLOAT; + if (!reg_lookup (str, (is_zfinx ? RCLASS_GPR : RCLASS_FPR), regno)) + return false; + if (!is_zfinx || (insn->pinfo & INSN_FLOAT_VAR)) + return true; + /* Source operand for fcvt.[FLOAT].[FLOAT] instructions requires + different float_size than the destination. */ + if ((insn->pinfo & INSN_FCVT_F_F) && operand == 'S') + float_size = (insn->pinfo & INSN_FCVT_SRC) >> INSN_FCVT_SRC_SHIFT; + /* Check register index for Zdinx/Zqinx. */ + switch (float_size) + { + case INSN_FLOAT_S: + return true; + case INSN_FLOAT_D: + switch (xlen) + { + case 32: + if (*regno & 0x01) + break; + return true; + default: + return true; + } + break; + case INSN_FLOAT_Q: + switch (xlen) + { + case 32: + if (*regno & 0x03) + break; + return true; + case 64: + if (*regno & 0x01) + break; + return true; + default: + return true; + } + break; + default: + return false; + } + return false; +} + /* All RISC-V CSR instructions belong to one of these classes. */ enum csr_insn_type { @@ -2518,19 +2573,19 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case 'a': goto jump; case 'S': /* Floating-point RS1 x8-x15. */ - if (!reg_lookup (&asarg, RCLASS_FPR, ®no) + if (!reg_lookup_fp(*oparg, &asarg, insn, ®no) || !(regno >= 8 && regno <= 15)) break; INSERT_OPERAND (CRS1S, *ip, regno % 8); continue; case 'D': /* Floating-point RS2 x8-x15. */ - if (!reg_lookup (&asarg, RCLASS_FPR, ®no) + if (!reg_lookup_fp(*oparg, &asarg, insn, ®no) || !(regno >= 8 && regno <= 15)) break; INSERT_OPERAND (CRS2S, *ip, regno % 8); continue; case 'T': /* Floating-point RS2. */ - if (!reg_lookup (&asarg, RCLASS_FPR, ®no)) + if (!reg_lookup_fp(*oparg, &asarg, insn, ®no)) break; INSERT_OPERAND (CRS2, *ip, regno); continue; @@ -2897,9 +2952,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case 'T': /* Floating point RS2. */ case 'U': /* Floating point RS1 and RS2. */ case 'R': /* Floating point RS3. */ - if (reg_lookup (&asarg, - (riscv_subset_supports (&riscv_rps_as, "zfinx") - ? RCLASS_GPR : RCLASS_FPR), ®no)) + if (reg_lookup_fp(*oparg, &asarg, insn, ®no)) { char c = *oparg; if (*asarg == ' ') -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI ` (6 preceding siblings ...) 2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI @ 2022-02-01 13:53 ` Tsukasa OI 2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI ` (3 more replies) 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI 8 siblings, 4 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:53 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils [About this patchset] This is the Part 3 of my Z[fdq]inx fixes and enhancements. See Part 1 for general background and Part 2A for the bug which this Part 3 tests. <https://sourceware.org/pipermail/binutils/2022-February/119570.html> (Part 1) <https://sourceware.org/pipermail/binutils/2022-February/119576.html> (Part 2A) [About this Part] Part 3 contains common testcases to make sure that the issue I described on Part 2A is fixed. As I described earlier, Zdinx/Zqinx has register number constraints and GNU Binutils allows emitting invalid Zdinx/Zqinx instructions (before patchset Part 2 is applied). This constraint is dependent on the instruction so all Zdinx/Zqinx instructions are tested for assembler. PATCH 1: Zdinx, assembler PATCH 2: Zdinx, disassembler PATCH 3: Zqinx, assembler PATCH 4: Zqinx, disassembler Note that applying Part 2B will generate failure on disassembler tests (I added on PATCH 2 and 4). This is because I stopped before tackling with disassembler issue with this option. Tsukasa OI (4): RISC-V: Add assembler testcases for Zdinx regs RISC-V: Add disassembler tests for Zdinx regs RISC-V: Add assembler testcases for Zqinx regs RISC-V: Add disassembler tests for Zqinx regs .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 +++++ .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 21 files changed, 1416 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s base-commit: e327c35ef5768789d3ba41a629f178f5eec32790 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI @ 2022-02-01 13:53 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI ` (2 subsequent siblings) 3 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:53 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds several assembler tests for Zdinx register pairs. gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++++++++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++++++++++ 5 files changed, 357 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..62451c74d80 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rtz' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rtz' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rtz' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rtz' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rtz' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rtz' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rtz' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rtz' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rtz' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rtz' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rtz' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rtz' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rtz' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rtz' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rtz' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rtz' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..5539d9ef3fc --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rtz + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rtz + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rtz + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rtz + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rtz + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rtz + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rtz + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rtz + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rtz + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rtz + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rtz + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rtz + fsqrt.d a1, a2 + fsqrt.d a1, a2, rtz + fsqrt.d a0, a1 + fsqrt.d a0, a1, rtz + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rtz + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rtz + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rtz + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rtz + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rtz + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rtz + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rtz + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rtz + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rtz + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rtz + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rtz + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rtz + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rtz + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rtz + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rtz + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rtz + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rtz + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rtz + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rtz + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rtz + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rtz + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rtz + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..5e3c1a88592 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e61553[ ]+fadd.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae61553[ ]+fsub.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e61553[ ]+fmul.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae61553[ ]+fdiv.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a061553[ ]+fsqrt.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e61543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6154f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e61547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6154b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2061553[ ]+fcvt.w.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20615d3[ ]+fcvt.w.d[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2161553[ ]+fcvt.wu.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21615d3[ ]+fcvt.wu.d[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40161553[ ]+fcvt.s.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401615d3[ ]+fcvt.s.d[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..62807248e77 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rtz + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rtz + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rtz + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rtz + fsqrt.d a0, a2 + fsqrt.d a0, a2, rtz + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rtz + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rtz + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rtz + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rtz + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rtz + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rtz + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rtz + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rtz + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rtz + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rtz + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs 2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:53:35 PST (-0800), binutils@sourceware.org wrote: > This commit adds several assembler tests for Zdinx register pairs. > > gas/ChangeLog: > > * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx > register pairs. > * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. > * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx > register pairs (failure cases). > * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. > * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. > --- > .../gas/riscv/zdinx-32-regpair-fail.d | 3 + > .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++++++++++ > .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++++++++++ > gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++++++ > gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++++++++++ > 5 files changed, 357 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s > > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > new file mode 100644 > index 00000000000..f26096ca1c9 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > @@ -0,0 +1,3 @@ > +#as: -march=rv32ima_zdinx > +#source: zdinx-32-regpair-fail.s > +#error_output: zdinx-32-regpair-fail.l > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > new file mode 100644 > index 00000000000..62451c74d80 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > @@ -0,0 +1,111 @@ > +.*Assembler messages: > +.*Error: illegal operands `fadd\.d a1,a2,a4' > +.*Error: illegal operands `fadd\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fadd\.d a0,a1,a4' > +.*Error: illegal operands `fadd\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fadd\.d a0,a2,a1' > +.*Error: illegal operands `fadd\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fsub\.d a1,a2,a4' > +.*Error: illegal operands `fsub\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fsub\.d a0,a1,a4' > +.*Error: illegal operands `fsub\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fsub\.d a0,a2,a1' > +.*Error: illegal operands `fsub\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fmul\.d a1,a2,a4' > +.*Error: illegal operands `fmul\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fmul\.d a0,a1,a4' > +.*Error: illegal operands `fmul\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fmul\.d a0,a2,a1' > +.*Error: illegal operands `fmul\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fdiv\.d a1,a2,a4' > +.*Error: illegal operands `fdiv\.d a1,a2,a4,rtz' > +.*Error: illegal operands `fdiv\.d a0,a1,a4' > +.*Error: illegal operands `fdiv\.d a0,a1,a4,rtz' > +.*Error: illegal operands `fdiv\.d a0,a2,a1' > +.*Error: illegal operands `fdiv\.d a0,a2,a1,rtz' > +.*Error: illegal operands `fsqrt\.d a1,a2' > +.*Error: illegal operands `fsqrt\.d a1,a2,rtz' > +.*Error: illegal operands `fsqrt\.d a0,a1' > +.*Error: illegal operands `fsqrt\.d a0,a1,rtz' > +.*Error: illegal operands `fmin\.d a1,a2,a4' > +.*Error: illegal operands `fmin\.d a0,a1,a4' > +.*Error: illegal operands `fmin\.d a0,a2,a1' > +.*Error: illegal operands `fmax\.d a1,a2,a4' > +.*Error: illegal operands `fmax\.d a0,a1,a4' > +.*Error: illegal operands `fmax\.d a0,a2,a1' > +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' > +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' > +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' > +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' > +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' > +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' > +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' > +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' > +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' > +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' > +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' > +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' > +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' > +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' > +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' > +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' > +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fsgnj\.d a1,a2,a4' > +.*Error: illegal operands `fsgnj\.d a0,a1,a4' > +.*Error: illegal operands `fsgnj\.d a0,a2,a1' > +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' > +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' > +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' > +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' > +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' > +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' > +.*Error: illegal operands `fmv\.d a1,a2' > +.*Error: illegal operands `fmv\.d a0,a1' > +.*Error: illegal operands `fneg\.d a1,a2' > +.*Error: illegal operands `fneg\.d a0,a1' > +.*Error: illegal operands `fabs\.d a1,a2' > +.*Error: illegal operands `fabs\.d a0,a1' > +.*Error: illegal operands `feq\.d a0,a1,a4' > +.*Error: illegal operands `feq\.d a0,a2,a1' > +.*Error: illegal operands `flt\.d a0,a1,a4' > +.*Error: illegal operands `flt\.d a0,a2,a1' > +.*Error: illegal operands `fle\.d a0,a1,a4' > +.*Error: illegal operands `fle\.d a0,a2,a1' > +.*Error: illegal operands `fgt\.d a0,a1,a4' > +.*Error: illegal operands `fgt\.d a0,a2,a1' > +.*Error: illegal operands `fge\.d a0,a1,a4' > +.*Error: illegal operands `fge\.d a0,a2,a1' > +.*Error: illegal operands `fclass\.d a0,a1' > +.*Error: illegal operands `fcvt\.w\.d a0,a1' > +.*Error: illegal operands `fcvt\.w\.d a0,a1,rtz' > +.*Error: illegal operands `fcvt\.w\.d a3,a1' > +.*Error: illegal operands `fcvt\.w\.d a3,a1,rtz' > +.*Error: illegal operands `fcvt\.wu\.d a0,a1' > +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rtz' > +.*Error: illegal operands `fcvt\.wu\.d a3,a1' > +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rtz' > +.*Error: illegal operands `fcvt\.d\.w a1,a2' > +.*Error: illegal operands `fcvt\.d\.w a1,a3' > +.*Error: illegal operands `fcvt\.d\.wu a1,a2' > +.*Error: illegal operands `fcvt\.d\.wu a1,a3' > +.*Error: illegal operands `fcvt\.s\.d a0,a1' > +.*Error: illegal operands `fcvt\.s\.d a0,a1,rtz' > +.*Error: illegal operands `fcvt\.s\.d a3,a1' > +.*Error: illegal operands `fcvt\.s\.d a3,a1,rtz' > +.*Error: illegal operands `fcvt\.d\.s a1,a2' > +.*Error: illegal operands `fcvt\.d\.s a1,a3' > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > new file mode 100644 > index 00000000000..5539d9ef3fc > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > @@ -0,0 +1,116 @@ > +target: > + fadd.d a1, a2, a4 > + fadd.d a1, a2, a4, rtz > + fadd.d a0, a1, a4 > + fadd.d a0, a1, a4, rtz > + fadd.d a0, a2, a1 > + fadd.d a0, a2, a1, rtz > + fsub.d a1, a2, a4 > + fsub.d a1, a2, a4, rtz > + fsub.d a0, a1, a4 > + fsub.d a0, a1, a4, rtz > + fsub.d a0, a2, a1 > + fsub.d a0, a2, a1, rtz > + fmul.d a1, a2, a4 > + fmul.d a1, a2, a4, rtz > + fmul.d a0, a1, a4 > + fmul.d a0, a1, a4, rtz > + fmul.d a0, a2, a1 > + fmul.d a0, a2, a1, rtz > + fdiv.d a1, a2, a4 > + fdiv.d a1, a2, a4, rtz > + fdiv.d a0, a1, a4 > + fdiv.d a0, a1, a4, rtz > + fdiv.d a0, a2, a1 > + fdiv.d a0, a2, a1, rtz > + fsqrt.d a1, a2 > + fsqrt.d a1, a2, rtz > + fsqrt.d a0, a1 > + fsqrt.d a0, a1, rtz > + fmin.d a1, a2, a4 > + fmin.d a0, a1, a4 > + fmin.d a0, a2, a1 > + fmax.d a1, a2, a4 > + fmax.d a0, a1, a4 > + fmax.d a0, a2, a1 > + fmadd.d a1, a2, a4, a6 > + fmadd.d a1, a2, a4, a6, rtz > + fmadd.d a0, a1, a4, a6 > + fmadd.d a0, a1, a4, a6, rtz > + fmadd.d a0, a2, a1, a6 > + fmadd.d a0, a2, a1, a6, rtz > + fmadd.d a0, a2, a4, a1 > + fmadd.d a0, a2, a4, a1, rtz > + fnmadd.d a1, a2, a4, a6 > + fnmadd.d a1, a2, a4, a6, rtz > + fnmadd.d a0, a1, a4, a6 > + fnmadd.d a0, a1, a4, a6, rtz > + fnmadd.d a0, a2, a1, a6 > + fnmadd.d a0, a2, a1, a6, rtz > + fnmadd.d a0, a2, a4, a1 > + fnmadd.d a0, a2, a4, a1, rtz > + fmsub.d a1, a2, a4, a6 > + fmsub.d a1, a2, a4, a6, rtz > + fmsub.d a0, a1, a4, a6 > + fmsub.d a0, a1, a4, a6, rtz > + fmsub.d a0, a2, a1, a6 > + fmsub.d a0, a2, a1, a6, rtz > + fmsub.d a0, a2, a4, a1 > + fmsub.d a0, a2, a4, a1, rtz > + fnmsub.d a1, a2, a4, a6 > + fnmsub.d a1, a2, a4, a6, rtz > + fnmsub.d a0, a1, a4, a6 > + fnmsub.d a0, a1, a4, a6, rtz > + fnmsub.d a0, a2, a1, a6 > + fnmsub.d a0, a2, a1, a6, rtz > + fnmsub.d a0, a2, a4, a1 > + fnmsub.d a0, a2, a4, a1, rtz > + fsgnj.d a1, a2, a4 > + fsgnj.d a0, a1, a4 > + fsgnj.d a0, a2, a1 > + fsgnjn.d a1, a2, a4 > + fsgnjn.d a0, a1, a4 > + fsgnjn.d a0, a2, a1 > + fsgnjx.d a1, a2, a4 > + fsgnjx.d a0, a1, a4 > + fsgnjx.d a0, a2, a1 > + fmv.d a1, a2 > + fmv.d a0, a1 > + fneg.d a1, a2 > + fneg.d a0, a1 > + fabs.d a1, a2 > + fabs.d a0, a1 > + # Compare instructions: destination is a GPR > + feq.d a0, a1, a4 > + feq.d a0, a2, a1 > + flt.d a0, a1, a4 > + flt.d a0, a2, a1 > + fle.d a0, a1, a4 > + fle.d a0, a2, a1 > + fgt.d a0, a1, a4 > + fgt.d a0, a2, a1 > + fge.d a0, a1, a4 > + fge.d a0, a2, a1 > + # fclass instruction: destination is a GPR > + fclass.d a0, a1 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be odd) > + fcvt.w.d a0, a1 > + fcvt.w.d a0, a1, rtz > + fcvt.w.d a3, a1 > + fcvt.w.d a3, a1, rtz > + fcvt.wu.d a0, a1 > + fcvt.wu.d a0, a1, rtz > + fcvt.wu.d a3, a1 > + fcvt.wu.d a3, a1, rtz > + fcvt.d.w a1, a2 > + fcvt.d.w a1, a3 > + fcvt.d.wu a1, a2 > + fcvt.d.wu a1, a3 > + # fcvt instructions (float-float; FP32 operand can be odd) > + fcvt.s.d a0, a1 > + fcvt.s.d a0, a1, rtz > + fcvt.s.d a3, a1 > + fcvt.s.d a3, a1, rtz > + fcvt.d.s a1, a2 > + fcvt.d.s a1, a3 > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d > new file mode 100644 > index 00000000000..5e3c1a88592 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d > @@ -0,0 +1,65 @@ > +#as: -march=rv32ima_zdinx > +#source: zdinx-32-regpair.s > +#objdump: -dr > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+02e61553[ ]+fadd.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+0ae61553[ ]+fsub.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+12e61553[ ]+fmul.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+1ae61553[ ]+fdiv.d[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+5a061553[ ]+fsqrt.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e61543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e6154f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e61547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+82e6154b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 > +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c2061553[ ]+fcvt.w.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c20615d3[ ]+fcvt.w.d[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c2161553[ ]+fcvt.wu.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c21615d3[ ]+fcvt.wu.d[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40161553[ ]+fcvt.s.d[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+401615d3[ ]+fcvt.s.d[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s > new file mode 100644 > index 00000000000..62807248e77 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s > @@ -0,0 +1,62 @@ > +target: > + fadd.d a0, a2, a4 > + fadd.d a0, a2, a4, rtz > + fsub.d a0, a2, a4 > + fsub.d a0, a2, a4, rtz > + fmul.d a0, a2, a4 > + fmul.d a0, a2, a4, rtz > + fdiv.d a0, a2, a4 > + fdiv.d a0, a2, a4, rtz > + fsqrt.d a0, a2 > + fsqrt.d a0, a2, rtz > + fmin.d a0, a2, a4 > + fmax.d a0, a2, a4 > + fmadd.d a0, a2, a4, a6 > + fmadd.d a0, a2, a4, a6, rtz > + fnmadd.d a0, a2, a4, a6 > + fnmadd.d a0, a2, a4, a6, rtz > + fmsub.d a0, a2, a4, a6 > + fmsub.d a0, a2, a4, a6, rtz > + fnmsub.d a0, a2, a4, a6 > + fnmsub.d a0, a2, a4, a6, rtz > + fsgnj.d a0, a2, a4 > + fsgnjn.d a0, a2, a4 > + fsgnjx.d a0, a2, a4 > + fmv.d a0, a2 > + fneg.d a0, a2 > + fabs.d a0, a2 > + # Compare instructions: destination is a GPR > + feq.d a0, a2, a4 > + feq.d a1, a2, a4 > + flt.d a0, a2, a4 > + flt.d a1, a2, a4 > + fle.d a0, a2, a4 > + fle.d a1, a2, a4 > + fgt.d a0, a2, a4 > + fgt.d a1, a2, a4 > + fge.d a0, a2, a4 > + fge.d a1, a2, a4 > + # fclass instruction: destination is a GPR > + fclass.d a0, a2 > + fclass.d a1, a2 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be odd) > + fcvt.w.d a0, a2 > + fcvt.w.d a0, a2, rtz > + fcvt.w.d a1, a2 > + fcvt.w.d a1, a2, rtz > + fcvt.wu.d a0, a2 > + fcvt.wu.d a0, a2, rtz > + fcvt.wu.d a1, a2 > + fcvt.wu.d a1, a2, rtz > + fcvt.d.w a0, a2 > + fcvt.d.w a0, a1 > + fcvt.d.wu a0, a2 > + fcvt.d.wu a0, a1 > + # fcvt instructions (float-float; FP32 operand can be odd) > + fcvt.s.d a0, a2 > + fcvt.s.d a0, a2, rtz > + fcvt.s.d a1, a2 > + fcvt.s.d a1, a2, rtz > + fcvt.d.s a0, a2 > + fcvt.d.s a0, a1 Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/4] RISC-V: Add disassembler tests for Zdinx regs 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI 2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI @ 2022-02-01 13:53 ` Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI 2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI 3 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:53 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commid adds disassembler tests for invalid Zdinx register numbers (make sure that we don't disassemble invalid encodings). gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. --- gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d | 11 +++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s | 5 +++++ 2 files changed, 16 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..aa0c72cae87 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn 0x02627153 + # fadd.d x3, x5, x7 (invalid) + .insn 0x0272f1d3 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/4] RISC-V: Add disassembler tests for Zdinx regs 2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI @ 2022-02-08 2:00 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:00 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:53:36 PST (-0800), binutils@sourceware.org wrote: > This commid adds disassembler tests for invalid Zdinx register numbers > (make sure that we don't disassemble invalid encodings). > > gas/ChangeLog: > > * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make > sure that invalid encoding is not disassembled. > * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. > --- > gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d | 11 +++++++++++ > gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s | 5 +++++ > 2 files changed, 16 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s > > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d > new file mode 100644 > index 00000000000..018a0e51f03 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d > @@ -0,0 +1,11 @@ > +#as: -march=rv32ima_zdinx > +#source: zdinx-32-regpair-dis.s > +#objdump: -dr -Mnumeric > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 > +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 > diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s > new file mode 100644 > index 00000000000..aa0c72cae87 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s > @@ -0,0 +1,5 @@ > +target: > + # fadd.d x2, x4, x6 > + .insn 0x02627153 > + # fadd.d x3, x5, x7 (invalid) > + .insn 0x0272f1d3 Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI 2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI 2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI @ 2022-02-01 13:53 ` Tsukasa OI 2022-02-08 2:01 ` Palmer Dabbelt 2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI 3 siblings, 1 reply; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:53 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds several assembler tests for Zqinx register pairs / quad-register groups. gas/ChangeLog: * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 10 files changed, 1008 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..ad8aa69ffd7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rtz' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rtz' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rtz' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rtz' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rtz' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rtz' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rtz' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rtz' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rtz' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rtz' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rtz' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rtz' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rtz' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rtz' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rtz' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rtz' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rtz' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..f1437239202 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rtz + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rtz + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rtz + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rtz + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rtz + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rtz + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rtz + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rtz + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rtz + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rtz + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rtz + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rtz + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rtz + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rtz + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rtz + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rtz + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rtz + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rtz + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rtz + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rtz + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rtz + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rtz + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rtz + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rtz + fsqrt.q x5, x8 + fsqrt.q x5, x8, rtz + fsqrt.q x6, x8 + fsqrt.q x6, x8, rtz + fsqrt.q x4, x5 + fsqrt.q x4, x5, rtz + fsqrt.q x4, x6 + fsqrt.q x4, x6, rtz + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rtz + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rtz + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rtz + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rtz + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rtz + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rtz + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rtz + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rtz + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rtz + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rtz + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rtz + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rtz + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rtz + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rtz + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rtz + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rtz + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rtz + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rtz + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rtz + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rtz + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rtz + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rtz + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rtz + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rtz + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rtz + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rtz + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rtz + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rtz + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rtz + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rtz + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rtz + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rtz + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rtz + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rtz + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rtz + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rtz + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rtz + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rtz + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rtz + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rtz + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rtz + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..414b10e48cc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rtz' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rtz' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rtz' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rtz' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rtz' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rtz' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rtz' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rtz' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rtz' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rtz' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rtz' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rtz' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rtz' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rtz' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rtz' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rtz' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rtz' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rtz' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..f01c4f98b9f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rtz + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rtz + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rtz + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rtz + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rtz + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rtz + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rtz + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rtz + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rtz + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rtz + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rtz + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rtz + fsqrt.q a1, a2 + fsqrt.q a1, a2, rtz + fsqrt.q a0, a1 + fsqrt.q a0, a1, rtz + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rtz + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rtz + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rtz + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rtz + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rtz + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rtz + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rtz + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rtz + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rtz + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rtz + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rtz + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rtz + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rtz + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rtz + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rtz + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rtz + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rtz + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rtz + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rtz + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rtz + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rtz + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rtz + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rtz + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rtz + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rtz + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rtz + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rtz + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rtz + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rtz + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rtz + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rtz + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rtz + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..62eefdf69f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e61553[ ]+fadd.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee61553[ ]+fsub.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e61553[ ]+fmul.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee61553[ ]+fdiv.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e061553[ ]+fsqrt.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e61543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6154f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e61547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6154b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6061553[ ]+fcvt.w.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60615d3[ ]+fcvt.w.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6161553[ ]+fcvt.wu.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61615d3[ ]+fcvt.wu.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6261553[ ]+fcvt.l.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62615d3[ ]+fcvt.l.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6361553[ ]+fcvt.lu.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63615d3[ ]+fcvt.lu.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6261553[ ]+fcvt.q.l[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6259553[ ]+fcvt.q.l[ ]+a0,a1,rtz +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6361553[ ]+fcvt.q.lu[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6359553[ ]+fcvt.q.lu[ ]+a0,a1,rtz +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40361553[ ]+fcvt.s.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403615d3[ ]+fcvt.s.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42361553[ ]+fcvt.d.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423615d3[ ]+fcvt.d.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..0c80749fd66 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rtz + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rtz + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rtz + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rtz + fsqrt.q a0, a2 + fsqrt.q a0, a2, rtz + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rtz + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rtz + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rtz + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rtz + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rtz + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rtz + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rtz + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rtz + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rtz + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rtz + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rtz + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rtz + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rtz + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, rtz + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rtz + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, rtz + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rtz + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rtz + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rtz + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rtz + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs 2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI @ 2022-02-08 2:01 ` Palmer Dabbelt 0 siblings, 0 replies; 39+ messages in thread From: Palmer Dabbelt @ 2022-02-08 2:01 UTC (permalink / raw) To: binutils; +Cc: research_trasio, binutils On Tue, 01 Feb 2022 05:53:37 PST (-0800), binutils@sourceware.org wrote: > This commit adds several assembler tests for Zqinx register pairs / > quad-register groups. > > gas/ChangeLog: > > * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx > register pairs. > * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. > * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx > register pairs (failure cases). > * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. > * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. > * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx > register pairs and quad-register groups. > * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. > * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx > register pairs and quad-register groups (failure cases). > * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. > * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. > --- > .../gas/riscv/zqinx-32-regpair-fail.d | 3 + > .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ > .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ > gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ > gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ > .../gas/riscv/zqinx-64-regpair-fail.d | 3 + > .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ > .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ > gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ > gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ > 10 files changed, 1008 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s > > diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d > new file mode 100644 > index 00000000000..957401f4683 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d > @@ -0,0 +1,3 @@ > +#as: -march=rv32ima_zqinx > +#source: zqinx-32-regpair-fail.s > +#error_output: zqinx-32-regpair-fail.l > diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l > new file mode 100644 > index 00000000000..ad8aa69ffd7 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l > @@ -0,0 +1,212 @@ > +.*Assembler messages: > +.*Error: illegal operands `fadd\.q x5,x8,x12' > +.*Error: illegal operands `fadd\.q x5,x8,x12,rtz' > +.*Error: illegal operands `fadd\.q x6,x8,x12' > +.*Error: illegal operands `fadd\.q x6,x8,x12,rtz' > +.*Error: illegal operands `fadd\.q x4,x5,x12' > +.*Error: illegal operands `fadd\.q x4,x5,x12,rtz' > +.*Error: illegal operands `fadd\.q x4,x6,x12' > +.*Error: illegal operands `fadd\.q x4,x6,x12,rtz' > +.*Error: illegal operands `fadd\.q x4,x8,x5' > +.*Error: illegal operands `fadd\.q x4,x8,x5,rtz' > +.*Error: illegal operands `fadd\.q x4,x8,x6' > +.*Error: illegal operands `fadd\.q x4,x8,x6,rtz' > +.*Error: illegal operands `fsub\.q x5,x8,x12' > +.*Error: illegal operands `fsub\.q x5,x8,x12,rtz' > +.*Error: illegal operands `fsub\.q x6,x8,x12' > +.*Error: illegal operands `fsub\.q x6,x8,x12,rtz' > +.*Error: illegal operands `fsub\.q x4,x5,x12' > +.*Error: illegal operands `fsub\.q x4,x5,x12,rtz' > +.*Error: illegal operands `fsub\.q x4,x6,x12' > +.*Error: illegal operands `fsub\.q x4,x6,x12,rtz' > +.*Error: illegal operands `fsub\.q x4,x8,x5' > +.*Error: illegal operands `fsub\.q x4,x8,x5,rtz' > +.*Error: illegal operands `fsub\.q x4,x8,x6' > +.*Error: illegal operands `fsub\.q x4,x8,x6,rtz' > +.*Error: illegal operands `fmul\.q x5,x8,x12' > +.*Error: illegal operands `fmul\.q x5,x8,x12,rtz' > +.*Error: illegal operands `fmul\.q x6,x8,x12' > +.*Error: illegal operands `fmul\.q x6,x8,x12,rtz' > +.*Error: illegal operands `fmul\.q x4,x5,x12' > +.*Error: illegal operands `fmul\.q x4,x5,x12,rtz' > +.*Error: illegal operands `fmul\.q x4,x6,x12' > +.*Error: illegal operands `fmul\.q x4,x6,x12,rtz' > +.*Error: illegal operands `fmul\.q x4,x8,x5' > +.*Error: illegal operands `fmul\.q x4,x8,x5,rtz' > +.*Error: illegal operands `fmul\.q x4,x8,x6' > +.*Error: illegal operands `fmul\.q x4,x8,x6,rtz' > +.*Error: illegal operands `fdiv\.q x5,x8,x12' > +.*Error: illegal operands `fdiv\.q x5,x8,x12,rtz' > +.*Error: illegal operands `fdiv\.q x6,x8,x12' > +.*Error: illegal operands `fdiv\.q x6,x8,x12,rtz' > +.*Error: illegal operands `fdiv\.q x4,x5,x12' > +.*Error: illegal operands `fdiv\.q x4,x5,x12,rtz' > +.*Error: illegal operands `fdiv\.q x4,x6,x12' > +.*Error: illegal operands `fdiv\.q x4,x6,x12,rtz' > +.*Error: illegal operands `fdiv\.q x4,x8,x5' > +.*Error: illegal operands `fdiv\.q x4,x8,x5,rtz' > +.*Error: illegal operands `fdiv\.q x4,x8,x6' > +.*Error: illegal operands `fdiv\.q x4,x8,x6,rtz' > +.*Error: illegal operands `fsqrt\.q x5,x8' > +.*Error: illegal operands `fsqrt\.q x5,x8,rtz' > +.*Error: illegal operands `fsqrt\.q x6,x8' > +.*Error: illegal operands `fsqrt\.q x6,x8,rtz' > +.*Error: illegal operands `fsqrt\.q x4,x5' > +.*Error: illegal operands `fsqrt\.q x4,x5,rtz' > +.*Error: illegal operands `fsqrt\.q x4,x6' > +.*Error: illegal operands `fsqrt\.q x4,x6,rtz' > +.*Error: illegal operands `fmin\.q x5,x8,x12' > +.*Error: illegal operands `fmin\.q x6,x8,x12' > +.*Error: illegal operands `fmin\.q x4,x5,x12' > +.*Error: illegal operands `fmin\.q x4,x6,x12' > +.*Error: illegal operands `fmin\.q x4,x8,x5' > +.*Error: illegal operands `fmin\.q x4,x8,x6' > +.*Error: illegal operands `fmax\.q x5,x8,x12' > +.*Error: illegal operands `fmax\.q x6,x8,x12' > +.*Error: illegal operands `fmax\.q x4,x5,x12' > +.*Error: illegal operands `fmax\.q x4,x6,x12' > +.*Error: illegal operands `fmax\.q x4,x8,x5' > +.*Error: illegal operands `fmax\.q x4,x8,x6' > +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' > +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rtz' > +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' > +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rtz' > +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' > +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rtz' > +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' > +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rtz' > +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' > +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rtz' > +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' > +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rtz' > +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' > +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rtz' > +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' > +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rtz' > +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' > +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rtz' > +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' > +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rtz' > +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' > +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rtz' > +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' > +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rtz' > +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' > +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rtz' > +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' > +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rtz' > +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' > +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rtz' > +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' > +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rtz' > +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' > +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rtz' > +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' > +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rtz' > +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' > +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rtz' > +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' > +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rtz' > +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' > +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rtz' > +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' > +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rtz' > +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' > +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rtz' > +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' > +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rtz' > +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' > +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rtz' > +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' > +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rtz' > +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' > +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rtz' > +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' > +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rtz' > +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' > +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rtz' > +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' > +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rtz' > +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' > +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rtz' > +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' > +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rtz' > +.*Error: illegal operands `fsgnj\.q x5,x8,x12' > +.*Error: illegal operands `fsgnj\.q x6,x8,x12' > +.*Error: illegal operands `fsgnj\.q x4,x5,x12' > +.*Error: illegal operands `fsgnj\.q x4,x6,x12' > +.*Error: illegal operands `fsgnj\.q x4,x8,x5' > +.*Error: illegal operands `fsgnj\.q x4,x8,x6' > +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' > +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' > +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' > +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' > +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' > +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' > +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' > +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' > +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' > +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' > +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' > +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' > +.*Error: illegal operands `fmv\.q x5,x8' > +.*Error: illegal operands `fmv\.q x6,x8' > +.*Error: illegal operands `fmv\.q x4,x5' > +.*Error: illegal operands `fmv\.q x4,x6' > +.*Error: illegal operands `fneg\.q x5,x8' > +.*Error: illegal operands `fneg\.q x6,x8' > +.*Error: illegal operands `fneg\.q x4,x5' > +.*Error: illegal operands `fneg\.q x4,x6' > +.*Error: illegal operands `fabs\.q x5,x8' > +.*Error: illegal operands `fabs\.q x6,x8' > +.*Error: illegal operands `fabs\.q x4,x5' > +.*Error: illegal operands `fabs\.q x4,x6' > +.*Error: illegal operands `feq\.q x4,x5,x12' > +.*Error: illegal operands `feq\.q x4,x6,x12' > +.*Error: illegal operands `feq\.q x4,x8,x5' > +.*Error: illegal operands `feq\.q x4,x8,x6' > +.*Error: illegal operands `flt\.q x4,x5,x12' > +.*Error: illegal operands `flt\.q x4,x6,x12' > +.*Error: illegal operands `flt\.q x4,x8,x5' > +.*Error: illegal operands `flt\.q x4,x8,x6' > +.*Error: illegal operands `fle\.q x4,x5,x12' > +.*Error: illegal operands `fle\.q x4,x6,x12' > +.*Error: illegal operands `fle\.q x4,x8,x5' > +.*Error: illegal operands `fle\.q x4,x8,x6' > +.*Error: illegal operands `fgt\.q x4,x5,x12' > +.*Error: illegal operands `fgt\.q x4,x6,x12' > +.*Error: illegal operands `fgt\.q x4,x8,x5' > +.*Error: illegal operands `fgt\.q x4,x8,x6' > +.*Error: illegal operands `fge\.q x4,x5,x12' > +.*Error: illegal operands `fge\.q x4,x6,x12' > +.*Error: illegal operands `fge\.q x4,x8,x5' > +.*Error: illegal operands `fge\.q x4,x8,x6' > +.*Error: illegal operands `fclass\.q x4,x5' > +.*Error: illegal operands `fclass\.q x4,x6' > +.*Error: illegal operands `fcvt\.w\.q x4,x5' > +.*Error: illegal operands `fcvt\.w\.q x4,x5,rtz' > +.*Error: illegal operands `fcvt\.w\.q x4,x6' > +.*Error: illegal operands `fcvt\.w\.q x4,x6,rtz' > +.*Error: illegal operands `fcvt\.wu\.q x4,x5' > +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rtz' > +.*Error: illegal operands `fcvt\.wu\.q x4,x6' > +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rtz' > +.*Error: illegal operands `fcvt\.q\.w x5,x4' > +.*Error: illegal operands `fcvt\.q\.w x6,x4' > +.*Error: illegal operands `fcvt\.q\.wu x5,x4' > +.*Error: illegal operands `fcvt\.q\.wu x6,x4' > +.*Error: illegal operands `fcvt\.s\.q x4,x5' > +.*Error: illegal operands `fcvt\.s\.q x4,x5,rtz' > +.*Error: illegal operands `fcvt\.s\.q x4,x6' > +.*Error: illegal operands `fcvt\.s\.q x4,x6,rtz' > +.*Error: illegal operands `fcvt\.d\.q x4,x5' > +.*Error: illegal operands `fcvt\.d\.q x4,x5,rtz' > +.*Error: illegal operands `fcvt\.d\.q x4,x6' > +.*Error: illegal operands `fcvt\.d\.q x4,x6,rtz' > +.*Error: illegal operands `fcvt\.d\.q x5,x8' > +.*Error: illegal operands `fcvt\.d\.q x5,x8,rtz' > +.*Error: illegal operands `fcvt\.q\.s x5,x4' > +.*Error: illegal operands `fcvt\.q\.s x6,x4' > +.*Error: illegal operands `fcvt\.q\.d x5,x4' > +.*Error: illegal operands `fcvt\.q\.d x6,x4' > +.*Error: illegal operands `fcvt\.q\.d x8,x5' > diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s > new file mode 100644 > index 00000000000..f1437239202 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s > @@ -0,0 +1,218 @@ > +target: > + fadd.q x5, x8, x12 > + fadd.q x5, x8, x12, rtz > + fadd.q x6, x8, x12 > + fadd.q x6, x8, x12, rtz > + fadd.q x4, x5, x12 > + fadd.q x4, x5, x12, rtz > + fadd.q x4, x6, x12 > + fadd.q x4, x6, x12, rtz > + fadd.q x4, x8, x5 > + fadd.q x4, x8, x5, rtz > + fadd.q x4, x8, x6 > + fadd.q x4, x8, x6, rtz > + fsub.q x5, x8, x12 > + fsub.q x5, x8, x12, rtz > + fsub.q x6, x8, x12 > + fsub.q x6, x8, x12, rtz > + fsub.q x4, x5, x12 > + fsub.q x4, x5, x12, rtz > + fsub.q x4, x6, x12 > + fsub.q x4, x6, x12, rtz > + fsub.q x4, x8, x5 > + fsub.q x4, x8, x5, rtz > + fsub.q x4, x8, x6 > + fsub.q x4, x8, x6, rtz > + fmul.q x5, x8, x12 > + fmul.q x5, x8, x12, rtz > + fmul.q x6, x8, x12 > + fmul.q x6, x8, x12, rtz > + fmul.q x4, x5, x12 > + fmul.q x4, x5, x12, rtz > + fmul.q x4, x6, x12 > + fmul.q x4, x6, x12, rtz > + fmul.q x4, x8, x5 > + fmul.q x4, x8, x5, rtz > + fmul.q x4, x8, x6 > + fmul.q x4, x8, x6, rtz > + fdiv.q x5, x8, x12 > + fdiv.q x5, x8, x12, rtz > + fdiv.q x6, x8, x12 > + fdiv.q x6, x8, x12, rtz > + fdiv.q x4, x5, x12 > + fdiv.q x4, x5, x12, rtz > + fdiv.q x4, x6, x12 > + fdiv.q x4, x6, x12, rtz > + fdiv.q x4, x8, x5 > + fdiv.q x4, x8, x5, rtz > + fdiv.q x4, x8, x6 > + fdiv.q x4, x8, x6, rtz > + fsqrt.q x5, x8 > + fsqrt.q x5, x8, rtz > + fsqrt.q x6, x8 > + fsqrt.q x6, x8, rtz > + fsqrt.q x4, x5 > + fsqrt.q x4, x5, rtz > + fsqrt.q x4, x6 > + fsqrt.q x4, x6, rtz > + fmin.q x5, x8, x12 > + fmin.q x6, x8, x12 > + fmin.q x4, x5, x12 > + fmin.q x4, x6, x12 > + fmin.q x4, x8, x5 > + fmin.q x4, x8, x6 > + fmax.q x5, x8, x12 > + fmax.q x6, x8, x12 > + fmax.q x4, x5, x12 > + fmax.q x4, x6, x12 > + fmax.q x4, x8, x5 > + fmax.q x4, x8, x6 > + fmadd.q x5, x8, x12, x16 > + fmadd.q x5, x8, x12, x16, rtz > + fmadd.q x6, x8, x12, x16 > + fmadd.q x6, x8, x12, x16, rtz > + fmadd.q x4, x5, x12, x16 > + fmadd.q x4, x5, x12, x16, rtz > + fmadd.q x4, x6, x12, x16 > + fmadd.q x4, x6, x12, x16, rtz > + fmadd.q x4, x8, x5, x16 > + fmadd.q x4, x8, x5, x16, rtz > + fmadd.q x4, x8, x6, x16 > + fmadd.q x4, x8, x6, x16, rtz > + fmadd.q x4, x8, x12, x5 > + fmadd.q x4, x8, x12, x5, rtz > + fmadd.q x4, x8, x12, x6 > + fmadd.q x4, x8, x12, x6, rtz > + fnmadd.q x5, x8, x12, x16 > + fnmadd.q x5, x8, x12, x16, rtz > + fnmadd.q x6, x8, x12, x16 > + fnmadd.q x6, x8, x12, x16, rtz > + fnmadd.q x4, x5, x12, x16 > + fnmadd.q x4, x5, x12, x16, rtz > + fnmadd.q x4, x6, x12, x16 > + fnmadd.q x4, x6, x12, x16, rtz > + fnmadd.q x4, x8, x5, x16 > + fnmadd.q x4, x8, x5, x16, rtz > + fnmadd.q x4, x8, x6, x16 > + fnmadd.q x4, x8, x6, x16, rtz > + fnmadd.q x4, x8, x12, x5 > + fnmadd.q x4, x8, x12, x5, rtz > + fnmadd.q x4, x8, x12, x6 > + fnmadd.q x4, x8, x12, x6, rtz > + fmsub.q x5, x8, x12, x16 > + fmsub.q x5, x8, x12, x16, rtz > + fmsub.q x6, x8, x12, x16 > + fmsub.q x6, x8, x12, x16, rtz > + fmsub.q x4, x5, x12, x16 > + fmsub.q x4, x5, x12, x16, rtz > + fmsub.q x4, x6, x12, x16 > + fmsub.q x4, x6, x12, x16, rtz > + fmsub.q x4, x8, x5, x16 > + fmsub.q x4, x8, x5, x16, rtz > + fmsub.q x4, x8, x6, x16 > + fmsub.q x4, x8, x6, x16, rtz > + fmsub.q x4, x8, x12, x5 > + fmsub.q x4, x8, x12, x5, rtz > + fmsub.q x4, x8, x12, x6 > + fmsub.q x4, x8, x12, x6, rtz > + fnmsub.q x5, x8, x12, x16 > + fnmsub.q x5, x8, x12, x16, rtz > + fnmsub.q x6, x8, x12, x16 > + fnmsub.q x6, x8, x12, x16, rtz > + fnmsub.q x4, x5, x12, x16 > + fnmsub.q x4, x5, x12, x16, rtz > + fnmsub.q x4, x6, x12, x16 > + fnmsub.q x4, x6, x12, x16, rtz > + fnmsub.q x4, x8, x5, x16 > + fnmsub.q x4, x8, x5, x16, rtz > + fnmsub.q x4, x8, x6, x16 > + fnmsub.q x4, x8, x6, x16, rtz > + fnmsub.q x4, x8, x12, x5 > + fnmsub.q x4, x8, x12, x5, rtz > + fnmsub.q x4, x8, x12, x6 > + fnmsub.q x4, x8, x12, x6, rtz > + fsgnj.q x5, x8, x12 > + fsgnj.q x6, x8, x12 > + fsgnj.q x4, x5, x12 > + fsgnj.q x4, x6, x12 > + fsgnj.q x4, x8, x5 > + fsgnj.q x4, x8, x6 > + fsgnjn.q x5, x8, x12 > + fsgnjn.q x6, x8, x12 > + fsgnjn.q x4, x5, x12 > + fsgnjn.q x4, x6, x12 > + fsgnjn.q x4, x8, x5 > + fsgnjn.q x4, x8, x6 > + fsgnjx.q x5, x8, x12 > + fsgnjx.q x6, x8, x12 > + fsgnjx.q x4, x5, x12 > + fsgnjx.q x4, x6, x12 > + fsgnjx.q x4, x8, x5 > + fsgnjx.q x4, x8, x6 > + fmv.q x5, x8 > + fmv.q x6, x8 > + fmv.q x4, x5 > + fmv.q x4, x6 > + fneg.q x5, x8 > + fneg.q x6, x8 > + fneg.q x4, x5 > + fneg.q x4, x6 > + fabs.q x5, x8 > + fabs.q x6, x8 > + fabs.q x4, x5 > + fabs.q x4, x6 > + # Compare instructions: destination is a GPR > + feq.q x4, x5, x12 > + feq.q x4, x6, x12 > + feq.q x4, x8, x5 > + feq.q x4, x8, x6 > + flt.q x4, x5, x12 > + flt.q x4, x6, x12 > + flt.q x4, x8, x5 > + flt.q x4, x8, x6 > + fle.q x4, x5, x12 > + fle.q x4, x6, x12 > + fle.q x4, x8, x5 > + fle.q x4, x8, x6 > + fgt.q x4, x5, x12 > + fgt.q x4, x6, x12 > + fgt.q x4, x8, x5 > + fgt.q x4, x8, x6 > + fge.q x4, x5, x12 > + fge.q x4, x6, x12 > + fge.q x4, x8, x5 > + fge.q x4, x8, x6 > + # fclass instruction: destination is a GPR > + fclass.q x4, x5 > + fclass.q x4, x6 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be any) > + fcvt.w.q x4, x5 > + fcvt.w.q x4, x5, rtz > + fcvt.w.q x4, x6 > + fcvt.w.q x4, x6, rtz > + fcvt.wu.q x4, x5 > + fcvt.wu.q x4, x5, rtz > + fcvt.wu.q x4, x6 > + fcvt.wu.q x4, x6, rtz > + fcvt.q.w x5, x4 > + fcvt.q.w x6, x4 > + fcvt.q.wu x5, x4 > + fcvt.q.wu x6, x4 > + # fcvt instructions (float-float; FP32 operand can be any, > + # FP64 operand can be (x%4)==2) > + fcvt.s.q x4, x5 > + fcvt.s.q x4, x5, rtz > + fcvt.s.q x4, x6 > + fcvt.s.q x4, x6, rtz > + fcvt.d.q x4, x5 > + fcvt.d.q x4, x5, rtz > + fcvt.d.q x4, x6 > + fcvt.d.q x4, x6, rtz > + fcvt.d.q x5, x8 > + fcvt.d.q x5, x8, rtz > + fcvt.q.s x5, x4 > + fcvt.q.s x6, x4 > + fcvt.q.d x5, x4 > + fcvt.q.d x6, x4 > + fcvt.q.d x8, x5 > diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d > new file mode 100644 > index 00000000000..fcfdab597b1 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d > @@ -0,0 +1,66 @@ > +#as: -march=rv32ima_zqinx > +#source: zqinx-32-regpair.s > +#objdump: -dr > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 > +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 > +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 > +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 > +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 > +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 > +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 > +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 > +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 > +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 > +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 > +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 > +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 > +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 > +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 > +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 > +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 > +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp > +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 > +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 > +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp > +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 > +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 > +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 > +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 > +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 > +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 > +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp > +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 > +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 > +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp > +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 > diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s > new file mode 100644 > index 00000000000..2f340767376 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s > @@ -0,0 +1,64 @@ > +target: > + fadd.q x4, x8, x12 > + fsub.q x4, x8, x12 > + fmul.q x4, x8, x12 > + fdiv.q x4, x8, x12 > + fsqrt.q x4, x8 > + fmin.q x4, x8, x12 > + fmax.q x4, x8, x12 > + fmadd.q x4, x8, x12, x16 > + fnmadd.q x4, x8, x12, x16 > + fmsub.q x4, x8, x12, x16 > + fnmsub.q x4, x8, x12, x16 > + fsgnj.q x4, x8, x12 > + fsgnjn.q x4, x8, x12 > + fsgnjx.q x4, x8, x12 > + fmv.q x4, x8 > + fneg.q x4, x8 > + fabs.q x4, x8 > + # Compare instructions: destination is a GPR > + feq.q x4, x8, x12 > + feq.q x5, x8, x12 > + feq.q x6, x8, x12 > + flt.q x4, x8, x12 > + flt.q x5, x8, x12 > + flt.q x6, x8, x12 > + fle.q x4, x8, x12 > + fle.q x5, x8, x12 > + fle.q x6, x8, x12 > + fgt.q x4, x8, x12 > + fgt.q x5, x8, x12 > + fgt.q x6, x8, x12 > + fge.q x4, x8, x12 > + fge.q x5, x8, x12 > + fge.q x6, x8, x12 > + # fclass instruction: destination is a GPR > + fclass.q x4, x8 > + fclass.q x5, x8 > + fclass.q x6, x8 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be any) > + fcvt.w.q x4, x8 > + fcvt.w.q x5, x8 > + fcvt.w.q x6, x8 > + fcvt.wu.q x4, x8 > + fcvt.wu.q x5, x8 > + fcvt.wu.q x6, x8 > + fcvt.q.w x8, x4 > + fcvt.q.w x8, x5 > + fcvt.q.w x8, x6 > + fcvt.q.wu x8, x4 > + fcvt.q.wu x8, x5 > + fcvt.q.wu x8, x6 > + # fcvt instructions (float-float; FP32 operand can be any, > + # FP64 operand can be (x%4)==2) > + fcvt.s.q x4, x8 > + fcvt.s.q x5, x8 > + fcvt.s.q x6, x8 > + fcvt.d.q x4, x8 > + fcvt.d.q x6, x8 > + fcvt.q.s x8, x4 > + fcvt.q.s x8, x5 > + fcvt.q.s x8, x6 > + fcvt.q.d x8, x4 > + fcvt.q.d x8, x6 > diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d > new file mode 100644 > index 00000000000..bac4e356675 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d > @@ -0,0 +1,3 @@ > +#as: -march=rv64ima_zqinx > +#source: zqinx-64-regpair-fail.s > +#error_output: zqinx-64-regpair-fail.l > diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l > new file mode 100644 > index 00000000000..414b10e48cc > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l > @@ -0,0 +1,133 @@ > +.*Assembler messages: > +.*Error: illegal operands `fadd\.q a1,a2,a4' > +.*Error: illegal operands `fadd\.q a1,a2,a4,rtz' > +.*Error: illegal operands `fadd\.q a0,a1,a4' > +.*Error: illegal operands `fadd\.q a0,a1,a4,rtz' > +.*Error: illegal operands `fadd\.q a0,a2,a1' > +.*Error: illegal operands `fadd\.q a0,a2,a1,rtz' > +.*Error: illegal operands `fsub\.q a1,a2,a4' > +.*Error: illegal operands `fsub\.q a1,a2,a4,rtz' > +.*Error: illegal operands `fsub\.q a0,a1,a4' > +.*Error: illegal operands `fsub\.q a0,a1,a4,rtz' > +.*Error: illegal operands `fsub\.q a0,a2,a1' > +.*Error: illegal operands `fsub\.q a0,a2,a1,rtz' > +.*Error: illegal operands `fmul\.q a1,a2,a4' > +.*Error: illegal operands `fmul\.q a1,a2,a4,rtz' > +.*Error: illegal operands `fmul\.q a0,a1,a4' > +.*Error: illegal operands `fmul\.q a0,a1,a4,rtz' > +.*Error: illegal operands `fmul\.q a0,a2,a1' > +.*Error: illegal operands `fmul\.q a0,a2,a1,rtz' > +.*Error: illegal operands `fdiv\.q a1,a2,a4' > +.*Error: illegal operands `fdiv\.q a1,a2,a4,rtz' > +.*Error: illegal operands `fdiv\.q a0,a1,a4' > +.*Error: illegal operands `fdiv\.q a0,a1,a4,rtz' > +.*Error: illegal operands `fdiv\.q a0,a2,a1' > +.*Error: illegal operands `fdiv\.q a0,a2,a1,rtz' > +.*Error: illegal operands `fsqrt\.q a1,a2' > +.*Error: illegal operands `fsqrt\.q a1,a2,rtz' > +.*Error: illegal operands `fsqrt\.q a0,a1' > +.*Error: illegal operands `fsqrt\.q a0,a1,rtz' > +.*Error: illegal operands `fmin\.q a1,a2,a4' > +.*Error: illegal operands `fmin\.q a0,a1,a4' > +.*Error: illegal operands `fmin\.q a0,a2,a1' > +.*Error: illegal operands `fmax\.q a1,a2,a4' > +.*Error: illegal operands `fmax\.q a0,a1,a4' > +.*Error: illegal operands `fmax\.q a0,a2,a1' > +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' > +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' > +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' > +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' > +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' > +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' > +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' > +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' > +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' > +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' > +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' > +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' > +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' > +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rtz' > +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' > +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rtz' > +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' > +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rtz' > +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' > +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rtz' > +.*Error: illegal operands `fsgnj\.q a1,a2,a4' > +.*Error: illegal operands `fsgnj\.q a0,a1,a4' > +.*Error: illegal operands `fsgnj\.q a0,a2,a1' > +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' > +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' > +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' > +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' > +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' > +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' > +.*Error: illegal operands `fmv\.q a1,a2' > +.*Error: illegal operands `fmv\.q a0,a1' > +.*Error: illegal operands `fneg\.q a1,a2' > +.*Error: illegal operands `fneg\.q a0,a1' > +.*Error: illegal operands `fabs\.q a1,a2' > +.*Error: illegal operands `fabs\.q a0,a1' > +.*Error: illegal operands `feq\.q a0,a1,a4' > +.*Error: illegal operands `feq\.q a0,a2,a1' > +.*Error: illegal operands `flt\.q a0,a1,a4' > +.*Error: illegal operands `flt\.q a0,a2,a1' > +.*Error: illegal operands `fle\.q a0,a1,a4' > +.*Error: illegal operands `fle\.q a0,a2,a1' > +.*Error: illegal operands `fgt\.q a0,a1,a4' > +.*Error: illegal operands `fgt\.q a0,a2,a1' > +.*Error: illegal operands `fge\.q a0,a1,a4' > +.*Error: illegal operands `fge\.q a0,a2,a1' > +.*Error: illegal operands `fclass\.q a0,a1' > +.*Error: illegal operands `fcvt\.w\.q a0,a1' > +.*Error: illegal operands `fcvt\.w\.q a0,a1,rtz' > +.*Error: illegal operands `fcvt\.w\.q a3,a1' > +.*Error: illegal operands `fcvt\.w\.q a3,a1,rtz' > +.*Error: illegal operands `fcvt\.wu\.q a0,a1' > +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rtz' > +.*Error: illegal operands `fcvt\.wu\.q a3,a1' > +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rtz' > +.*Error: illegal operands `fcvt\.l\.q a0,a1' > +.*Error: illegal operands `fcvt\.l\.q a0,a1,rtz' > +.*Error: illegal operands `fcvt\.l\.q a3,a1' > +.*Error: illegal operands `fcvt\.l\.q a3,a1,rtz' > +.*Error: illegal operands `fcvt\.lu\.q a0,a1' > +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rtz' > +.*Error: illegal operands `fcvt\.lu\.q a3,a1' > +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rtz' > +.*Error: illegal operands `fcvt\.q\.w a1,a2' > +.*Error: illegal operands `fcvt\.q\.w a1,a3' > +.*Error: illegal operands `fcvt\.q\.wu a1,a2' > +.*Error: illegal operands `fcvt\.q\.wu a1,a3' > +.*Error: illegal operands `fcvt\.q\.l a1,a2' > +.*Error: illegal operands `fcvt\.q\.l a1,a2,rtz' > +.*Error: illegal operands `fcvt\.q\.l a1,a3' > +.*Error: illegal operands `fcvt\.q\.l a1,a3,rtz' > +.*Error: illegal operands `fcvt\.q\.lu a1,a2' > +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rtz' > +.*Error: illegal operands `fcvt\.q\.lu a1,a3' > +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rtz' > +.*Error: illegal operands `fcvt\.s\.q a0,a1' > +.*Error: illegal operands `fcvt\.s\.q a0,a1,rtz' > +.*Error: illegal operands `fcvt\.s\.q a3,a1' > +.*Error: illegal operands `fcvt\.s\.q a3,a1,rtz' > +.*Error: illegal operands `fcvt\.d\.q a0,a1' > +.*Error: illegal operands `fcvt\.d\.q a0,a1,rtz' > +.*Error: illegal operands `fcvt\.d\.q a3,a1' > +.*Error: illegal operands `fcvt\.d\.q a3,a1,rtz' > +.*Error: illegal operands `fcvt\.q\.s a1,a2' > +.*Error: illegal operands `fcvt\.q\.s a1,a3' > +.*Error: illegal operands `fcvt\.q\.d a1,a2' > +.*Error: illegal operands `fcvt\.q\.d a1,a3' > diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s > new file mode 100644 > index 00000000000..f01c4f98b9f > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s > @@ -0,0 +1,138 @@ > +target: > + fadd.q a1, a2, a4 > + fadd.q a1, a2, a4, rtz > + fadd.q a0, a1, a4 > + fadd.q a0, a1, a4, rtz > + fadd.q a0, a2, a1 > + fadd.q a0, a2, a1, rtz > + fsub.q a1, a2, a4 > + fsub.q a1, a2, a4, rtz > + fsub.q a0, a1, a4 > + fsub.q a0, a1, a4, rtz > + fsub.q a0, a2, a1 > + fsub.q a0, a2, a1, rtz > + fmul.q a1, a2, a4 > + fmul.q a1, a2, a4, rtz > + fmul.q a0, a1, a4 > + fmul.q a0, a1, a4, rtz > + fmul.q a0, a2, a1 > + fmul.q a0, a2, a1, rtz > + fdiv.q a1, a2, a4 > + fdiv.q a1, a2, a4, rtz > + fdiv.q a0, a1, a4 > + fdiv.q a0, a1, a4, rtz > + fdiv.q a0, a2, a1 > + fdiv.q a0, a2, a1, rtz > + fsqrt.q a1, a2 > + fsqrt.q a1, a2, rtz > + fsqrt.q a0, a1 > + fsqrt.q a0, a1, rtz > + fmin.q a1, a2, a4 > + fmin.q a0, a1, a4 > + fmin.q a0, a2, a1 > + fmax.q a1, a2, a4 > + fmax.q a0, a1, a4 > + fmax.q a0, a2, a1 > + fmadd.q a1, a2, a4, a6 > + fmadd.q a1, a2, a4, a6, rtz > + fmadd.q a0, a1, a4, a6 > + fmadd.q a0, a1, a4, a6, rtz > + fmadd.q a0, a2, a1, a6 > + fmadd.q a0, a2, a1, a6, rtz > + fmadd.q a0, a2, a4, a1 > + fmadd.q a0, a2, a4, a1, rtz > + fnmadd.q a1, a2, a4, a6 > + fnmadd.q a1, a2, a4, a6, rtz > + fnmadd.q a0, a1, a4, a6 > + fnmadd.q a0, a1, a4, a6, rtz > + fnmadd.q a0, a2, a1, a6 > + fnmadd.q a0, a2, a1, a6, rtz > + fnmadd.q a0, a2, a4, a1 > + fnmadd.q a0, a2, a4, a1, rtz > + fmsub.q a1, a2, a4, a6 > + fmsub.q a1, a2, a4, a6, rtz > + fmsub.q a0, a1, a4, a6 > + fmsub.q a0, a1, a4, a6, rtz > + fmsub.q a0, a2, a1, a6 > + fmsub.q a0, a2, a1, a6, rtz > + fmsub.q a0, a2, a4, a1 > + fmsub.q a0, a2, a4, a1, rtz > + fnmsub.q a1, a2, a4, a6 > + fnmsub.q a1, a2, a4, a6, rtz > + fnmsub.q a0, a1, a4, a6 > + fnmsub.q a0, a1, a4, a6, rtz > + fnmsub.q a0, a2, a1, a6 > + fnmsub.q a0, a2, a1, a6, rtz > + fnmsub.q a0, a2, a4, a1 > + fnmsub.q a0, a2, a4, a1, rtz > + fsgnj.q a1, a2, a4 > + fsgnj.q a0, a1, a4 > + fsgnj.q a0, a2, a1 > + fsgnjn.q a1, a2, a4 > + fsgnjn.q a0, a1, a4 > + fsgnjn.q a0, a2, a1 > + fsgnjx.q a1, a2, a4 > + fsgnjx.q a0, a1, a4 > + fsgnjx.q a0, a2, a1 > + fmv.q a1, a2 > + fmv.q a0, a1 > + fneg.q a1, a2 > + fneg.q a0, a1 > + fabs.q a1, a2 > + fabs.q a0, a1 > + # Compare instructions: destination is a GPR > + feq.q a0, a1, a4 > + feq.q a0, a2, a1 > + flt.q a0, a1, a4 > + flt.q a0, a2, a1 > + fle.q a0, a1, a4 > + fle.q a0, a2, a1 > + fgt.q a0, a1, a4 > + fgt.q a0, a2, a1 > + fge.q a0, a1, a4 > + fge.q a0, a2, a1 > + # fclass instruction: destination is a GPR > + fclass.q a0, a1 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be odd) > + fcvt.w.q a0, a1 > + fcvt.w.q a0, a1, rtz > + fcvt.w.q a3, a1 > + fcvt.w.q a3, a1, rtz > + fcvt.wu.q a0, a1 > + fcvt.wu.q a0, a1, rtz > + fcvt.wu.q a3, a1 > + fcvt.wu.q a3, a1, rtz > + fcvt.l.q a0, a1 > + fcvt.l.q a0, a1, rtz > + fcvt.l.q a3, a1 > + fcvt.l.q a3, a1, rtz > + fcvt.lu.q a0, a1 > + fcvt.lu.q a0, a1, rtz > + fcvt.lu.q a3, a1 > + fcvt.lu.q a3, a1, rtz > + fcvt.q.w a1, a2 > + fcvt.q.w a1, a3 > + fcvt.q.wu a1, a2 > + fcvt.q.wu a1, a3 > + fcvt.q.l a1, a2 > + fcvt.q.l a1, a2, rtz > + fcvt.q.l a1, a3 > + fcvt.q.l a1, a3, rtz > + fcvt.q.lu a1, a2 > + fcvt.q.lu a1, a2, rtz > + fcvt.q.lu a1, a3 > + fcvt.q.lu a1, a3, rtz > + # fcvt instructions (float-float; FP32/FP64 operand can be odd) > + fcvt.s.q a0, a1 > + fcvt.s.q a0, a1, rtz > + fcvt.s.q a3, a1 > + fcvt.s.q a3, a1, rtz > + fcvt.d.q a0, a1 > + fcvt.d.q a0, a1, rtz > + fcvt.d.q a3, a1 > + fcvt.d.q a3, a1, rtz > + fcvt.q.s a1, a2 > + fcvt.q.s a1, a3 > + fcvt.q.d a1, a2 > + fcvt.q.d a1, a3 > diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d > new file mode 100644 > index 00000000000..62eefdf69f6 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d > @@ -0,0 +1,87 @@ > +#as: -march=rv64ima_zqinx > +#source: zqinx-64-regpair.s > +#objdump: -dr > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+06e61553[ ]+fadd.q[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+0ee61553[ ]+fsub.q[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+16e61553[ ]+fmul.q[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+1ee61553[ ]+fdiv.q[ ]+a0,a2,a4,rtz > +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+5e061553[ ]+fsqrt.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e61543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6154f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e61547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 > +[ ]+[0-9a-f]+:[ ]+86e6154b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rtz > +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 > +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 > +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 > +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6061553[ ]+fcvt.w.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c60615d3[ ]+fcvt.w.q[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6161553[ ]+fcvt.wu.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c61615d3[ ]+fcvt.wu.q[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6261553[ ]+fcvt.l.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c62615d3[ ]+fcvt.l.q[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+c6361553[ ]+fcvt.lu.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+c63615d3[ ]+fcvt.lu.q[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6261553[ ]+fcvt.q.l[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d6259553[ ]+fcvt.q.l[ ]+a0,a1,rtz > +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+d6361553[ ]+fcvt.q.lu[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+d6359553[ ]+fcvt.q.lu[ ]+a0,a1,rtz > +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+40361553[ ]+fcvt.s.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+403615d3[ ]+fcvt.s.q[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+42361553[ ]+fcvt.d.q[ ]+a0,a2,rtz > +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 > +[ ]+[0-9a-f]+:[ ]+423615d3[ ]+fcvt.d.q[ ]+a1,a2,rtz > +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 > +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 > +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 > diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s > new file mode 100644 > index 00000000000..0c80749fd66 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s > @@ -0,0 +1,84 @@ > +target: > + fadd.q a0, a2, a4 > + fadd.q a0, a2, a4, rtz > + fsub.q a0, a2, a4 > + fsub.q a0, a2, a4, rtz > + fmul.q a0, a2, a4 > + fmul.q a0, a2, a4, rtz > + fdiv.q a0, a2, a4 > + fdiv.q a0, a2, a4, rtz > + fsqrt.q a0, a2 > + fsqrt.q a0, a2, rtz > + fmin.q a0, a2, a4 > + fmax.q a0, a2, a4 > + fmadd.q a0, a2, a4, a6 > + fmadd.q a0, a2, a4, a6, rtz > + fnmadd.q a0, a2, a4, a6 > + fnmadd.q a0, a2, a4, a6, rtz > + fmsub.q a0, a2, a4, a6 > + fmsub.q a0, a2, a4, a6, rtz > + fnmsub.q a0, a2, a4, a6 > + fnmsub.q a0, a2, a4, a6, rtz > + fsgnj.q a0, a2, a4 > + fsgnjn.q a0, a2, a4 > + fsgnjx.q a0, a2, a4 > + fmv.q a0, a2 > + fneg.q a0, a2 > + fabs.q a0, a2 > + # Compare instructions: destination is a GPR > + feq.q a0, a2, a4 > + feq.q a1, a2, a4 > + flt.q a0, a2, a4 > + flt.q a1, a2, a4 > + fle.q a0, a2, a4 > + fle.q a1, a2, a4 > + fgt.q a0, a2, a4 > + fgt.q a1, a2, a4 > + fge.q a0, a2, a4 > + fge.q a1, a2, a4 > + # fclass instruction: destination is a GPR > + fclass.q a0, a2 > + fclass.q a1, a2 > + # fcvt instructions (float-int or int-float; > + # integer operand register can be odd) > + fcvt.w.q a0, a2 > + fcvt.w.q a0, a2, rtz > + fcvt.w.q a1, a2 > + fcvt.w.q a1, a2, rtz > + fcvt.wu.q a0, a2 > + fcvt.wu.q a0, a2, rtz > + fcvt.wu.q a1, a2 > + fcvt.wu.q a1, a2, rtz > + fcvt.l.q a0, a2 > + fcvt.l.q a0, a2, rtz > + fcvt.l.q a1, a2 > + fcvt.l.q a1, a2, rtz > + fcvt.lu.q a0, a2 > + fcvt.lu.q a0, a2, rtz > + fcvt.lu.q a1, a2 > + fcvt.lu.q a1, a2, rtz > + fcvt.q.w a0, a2 > + fcvt.q.w a0, a1 > + fcvt.q.wu a0, a2 > + fcvt.q.wu a0, a1 > + fcvt.q.l a0, a2 > + fcvt.q.l a0, a2, rtz > + fcvt.q.l a0, a1 > + fcvt.q.l a0, a1, rtz > + fcvt.q.lu a0, a2 > + fcvt.q.lu a0, a2, rtz > + fcvt.q.lu a0, a1 > + fcvt.q.lu a0, a1, rtz > + # fcvt instructions (float-float; FP32/FP64 operand can be odd) > + fcvt.s.q a0, a2 > + fcvt.s.q a0, a2, rtz > + fcvt.s.q a1, a2 > + fcvt.s.q a1, a2, rtz > + fcvt.d.q a0, a2 > + fcvt.d.q a0, a2, rtz > + fcvt.d.q a1, a2 > + fcvt.d.q a1, a2, rtz > + fcvt.q.s a0, a2 > + fcvt.q.s a0, a1 > + fcvt.q.d a0, a2 > + fcvt.q.d a0, a1 Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 4/4] RISC-V: Add disassembler tests for Zqinx regs 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI ` (2 preceding siblings ...) 2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI @ 2022-02-01 13:53 ` Tsukasa OI 3 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-02-01 13:53 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commid adds disassembler tests for invalid Zqinx register numbers (make sure that we don't disassemble invalid encodings). gas/ChangeLog: * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. --- gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s | 7 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d | 11 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s | 5 +++++ 4 files changed, 35 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..e11e671ecdc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn 0x06c47253 + # fadd.q x5, x9, x13 (invalid) + .insn 0x06d4f2d3 + # fadd.q x6, x10, x14 (invalid) + .insn 0x06e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..9edeae84ba7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn 0x06627153 + # fadd.q x3, x5, x7 (invalid) + .insn 0x0672f1d3 -- 2.32.0 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI ` (7 preceding siblings ...) 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI ` (10 more replies) 8 siblings, 11 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This patchset fixes various issues on Zfinx/Zdinx/Zqinx extensions. PATCH v1: <https://sourceware.org/pipermail/binutils/2022-February/119570.html> (Part 1) <https://sourceware.org/pipermail/binutils/2022-February/119576.html> (Part 2A) <https://sourceware.org/pipermail/binutils/2022-February/119582.html> (Part 3) Although general idea of my fixes is reviewed by Palmer Dabbelt (and this patchset is based on reviewed Part 1+2A+3 of PATCH v1), I made relatively large changes to former Part 2A (06 and 07 in PATCH v2). So, I'll explain what happened since then. Part 1 and 3 of PATCH v1 (01-05, 08-11 in PATCH v2) are practically unchanged. Patrick O'Neill made important changes to error and feature handling on the assembler (commit e4028336b19998e74a51dd0918a8b3922e08a537) but it affected my PATCH v1 in a bad way. On a GAS testcase gas/riscv/rouding-fail, it should generate errors like this: /.../gas/testsuite/gas/riscv/rouding-fail.s:2: Error: illegal operands `fadd.s fa1,fa1,fa1,' /.../gas/testsuite/gas/riscv/rouding-fail.s:3: Error: illegal operands `fadd.d fa1,fa1,fa1,' But with rebased PATCH v1, it looks like this: /.../gas/testsuite/gas/riscv/rouding-fail.s:2: Error: illegal operands `fadd.s fa1,fa1,fa1,' /.../gas/testsuite/gas/riscv/rouding-fail.s:3: Error: illegal operands `fadd.d fa1,fa1,fa1,', extension `zdinx' required Note that "extension `zdinx' required" on `fadd.d'. If D/Zdinx or Q/Zqinx assembler instruction fails to parse with a reason BUT insufficient ISA extensions (e.g. D or Zdinx is enabled but has an invalid operand), it fails with an "extension required" message. This is caused as follows (e.g. on `fadd.d'): - In my PATCH v1, all D/Zdinx and Q/Zqinx instructions are splitted to XLEN-independent D/Q and XLEN-dependent Zdinx/Zqinx variants (due to register constraints in Zdinx/Zqinx). - All three entries of "fadd.d" are scanned: 1. XLEN-independent D variant 2. RV32_Zdinx variant 3. RV64_Zdinx variant - But at least one of them fails because of insufficient ISA extensions (because D and Zdinx are mutually exclusive). - So, `error.missing_ext' is set to a non-null value on `riscv_ip' function. - Since `error.missing_ext' is non-null, "extension required" message is generated and shown. That's why I needed a special pinfo flag `INSN_F_OR_X' on PATCH v2. In my PATCH v2, I implemented as follows: if an instruction (with INSN_F_OR_X) parsing fails with an insufficient extension error, it tests with secondary instruction class (diagnostics-only) and `error.missing_ext' is set only if it ALSO fails (note that setting `error.missing_ext' is suppressed but fails anyway even if the secondary test succeeds). On XLEN-independent D variant of `fadd.d' with Zdinx enabled (instruction class INSN_CLASS_D), it also checks Zdinx with secondary instruction class INSN_CLASS_D_OR_ZDINX. It can suppress unnecessary "extension required" error. Tsukasa OI (11): RISC-V: Fix disassembling Zfinx with -M numeric RISC-V: Make indentation consistent RISC-V: Use different registers for testing RISC-V: Relax `fmv.[sdq]' requirements RISC-V: Fix RV64_Zqinx to use register pairs RISC-V: Prepare D/Q and Zdinx/Zqinx separation RISC-V: Validate Zdinx/Zqinx register pairs RISC-V: Add assembler testcases for Zdinx regs RISC-V: Add disassembler tests for Zdinx regs RISC-V: Add assembler testcases for Zqinx regs RISC-V: Add disassembler tests for Zqinx regs bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 20 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ gas/testsuite/gas/riscv/zdinx.d | 7 +- gas/testsuite/gas/riscv/zdinx.s | 7 +- gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 + gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 + gas/testsuite/gas/riscv/zfinx.d | 7 +- gas/testsuite/gas/riscv/zfinx.s | 7 +- .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ gas/testsuite/gas/riscv/zqinx.d | 69 +-- gas/testsuite/gas/riscv/zqinx.s | 69 +-- include/opcode/riscv.h | 10 +- opcodes/riscv-dis.c | 2 +- opcodes/riscv-opc.c | 541 ++++++++++++++---- 34 files changed, 1985 insertions(+), 190 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s base-commit: cb3a7614feb82ffdc25161bf60529116c6112ab3 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI ` (9 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions. --- gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++ gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++ opcodes/riscv-dis.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d new file mode 100644 index 00000000000..ba3f62295eb --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d @@ -0,0 +1,10 @@ +#as: -march=rv64ima_zfinx +#source: zfinx-dis-numeric.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s new file mode 100644 index 00000000000..b55cbd56b21 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s @@ -0,0 +1,2 @@ +target: + feq.s a0, a1, a2 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 9ff31167775..164fd209dbd 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) /* If arch has ZFINX flags, use gpr for disassemble. */ if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) { -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 02/11] RISC-V: Make indentation consistent 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI ` (8 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit makes indentation consistent (replaces two spaces to a tab) on Zfinx / Zdinx / Zqinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Make indentation consistent. * testsuite/gas/riscv/zdinx.s: Likewise. * testsuite/gas/riscv/zqinx.s: Likewise. --- gas/testsuite/gas/riscv/zdinx.s | 2 +- gas/testsuite/gas/riscv/zfinx.s | 2 +- gas/testsuite/gas/riscv/zqinx.s | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..d8d13c88046 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -28,6 +28,6 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 - fneg.d a0, a0 + fneg.d a0, a0 fabs.d a0, a0 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..37a2aa75992 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -26,6 +26,6 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 - fneg.s a0, a0 + fneg.s a0, a0 fabs.s a0, a0 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..4b83552aced 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -30,6 +30,6 @@ target: fle.q a0, a1, a2 fgt.q a0, a1, a2 fge.q a0, a1, a2 - fneg.q a0, a0 + fneg.q a0, a0 fabs.q a0, a0 fclass.q a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 03/11] RISC-V: Use different registers for testing 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI ` (7 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit ensures that different registers are used when testing. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers. * testsuite/gas/riscv/zqinx.d: Likewise. --- gas/testsuite/gas/riscv/zdinx.d | 6 +++--- gas/testsuite/gas/riscv/zdinx.s | 6 +++--- gas/testsuite/gas/riscv/zfinx.d | 6 +++--- gas/testsuite/gas/riscv/zfinx.s | 6 +++--- gas/testsuite/gas/riscv/zqinx.d | 6 +++--- gas/testsuite/gas/riscv/zqinx.s | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..cb465bfbef4 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -11,7 +11,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 @@ -36,6 +36,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index d8d13c88046..f44358111de 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -3,7 +3,7 @@ target: fsub.d a0, a1, a2 fmul.d a0, a1, a2 fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fsqrt.d a0, a1 fmin.d a0, a1, a2 fmax.d a0, a1, a2 fmadd.d a0, a1, a2, a3 @@ -28,6 +28,6 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..6465c08ea9a 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -11,7 +11,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 @@ -34,6 +34,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 37a2aa75992..41ae0e38ad4 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -3,7 +3,7 @@ target: fsub.s a0, a1, a2 fmul.s a0, a1, a2 fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fsqrt.s a0, a1 fmin.s a0, a1, a2 fmax.s a0, a1, a2 fmadd.s a0, a1, a2, a3 @@ -26,6 +26,6 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..2123ee1b864 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -11,7 +11,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 @@ -38,6 +38,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 4b83552aced..ecfa509b98c 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -3,7 +3,7 @@ target: fsub.q a0, a1, a2 fmul.q a0, a1, a2 fdiv.q a0, a1, a2 - fsqrt.q a0, a0 + fsqrt.q a0, a1 fmin.q a0, a1, a2 fmax.q a0, a1, a2 fmadd.q a0, a1, a2, a3 @@ -30,6 +30,6 @@ target: fle.q a0, a1, a2 fgt.q a0, a1, a2 fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 + fneg.q a0, a1 + fabs.q a0, a1 fclass.q a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (2 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI ` (6 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit relaxes requirements to `fmv.s' instructions from F to (F or Zfinx). The same applies to `fmv.d' and `fmv.q'. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index cb465bfbef4..3db2cb56f1a 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -36,6 +36,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index f44358111de..cdf5f3c2e7e 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -28,6 +28,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 6465c08ea9a..6fc4491fbc0 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -34,6 +34,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 41ae0e38ad4..d63c0c37570 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -26,6 +26,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index 2123ee1b864..cff600ac217 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -38,6 +38,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ecfa509b98c..02147b1919c 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -30,6 +30,7 @@ target: fle.q a0, a1, a2 fgt.q a0, a1, a2 fge.q a0, a1, a2 + fmv.q a0, a1 fneg.q a0, a1 fabs.q a0, a1 fclass.q a0, a1 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bbd4a3718f6..d6abe21e3c8 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -666,7 +666,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -724,7 +724,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -781,7 +781,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (3 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI ` (5 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit ensures that all FP128 register numbers to be even because RV64_Zqinx would require it. gas/ChangeLog: * testsuite/gas/riscv/zqinx.s: Make register numbers even. * testsuite/gas/riscv/zqinx.d: Likewise. --- gas/testsuite/gas/riscv/zqinx.d | 70 ++++++++++++++++----------------- gas/testsuite/gas/riscv/zqinx.s | 70 ++++++++++++++++----------------- 2 files changed, 70 insertions(+), 70 deletions(-) diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index cff600ac217..52b5445d010 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,38 +7,38 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 02147b1919c..2dc2a7c1483 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,36 +1,36 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a1 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fmv.q a0, a1 - fneg.q a0, a1 - fabs.q a0, a1 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fsub.q a0, a2, a4 + fmul.q a0, a2, a4 + fdiv.q a0, a2, a4 + fsqrt.q a0, a2 + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6 + fcvt.w.q a0, a2 + fcvt.wu.q a0, a2 + fcvt.l.q a0, a2 + fcvt.lu.q a0, a2 + fcvt.s.q a0, a2 + fcvt.d.q a0, a2 + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.lu a0, a2 + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (4 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI ` (4 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit renames instruction class names for Zdinx/Zqinx to prepare separation between D/Q and Zdinx/Zqinx. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect renamed instruction classes. (riscv_multi_subset_supports_ext) Reflect renamed instruction classes. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Rename INSN_CLASS_D_OR_ZDINX to INSN_CLASS_ZDINX, INSN_CLASS_Q_OR_ZQINX to INSN_CLASS_ZQINX. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Reflect renamed instruction classes. --- bfd/elfxx-riscv.c | 8 +- include/opcode/riscv.h | 4 +- opcodes/riscv-opc.c | 202 ++++++++++++++++++++--------------------- 3 files changed, 107 insertions(+), 107 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b2806185fa8..79b601c5518 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2356,10 +2356,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_F_OR_ZFINX: return (riscv_subset_supports (rps, "f") || riscv_subset_supports (rps, "zfinx")); - case INSN_CLASS_D_OR_ZDINX: + case INSN_CLASS_ZDINX: return (riscv_subset_supports (rps, "d") || riscv_subset_supports (rps, "zdinx")); - case INSN_CLASS_Q_OR_ZQINX: + case INSN_CLASS_ZQINX: return (riscv_subset_supports (rps, "q") || riscv_subset_supports (rps, "zqinx")); case INSN_CLASS_ZFH: @@ -2468,9 +2468,9 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "c"; case INSN_CLASS_F_OR_ZFINX: return "f' or `zfinx"; - case INSN_CLASS_D_OR_ZDINX: + case INSN_CLASS_ZDINX: return "d' or `zdinx"; - case INSN_CLASS_Q_OR_ZQINX: + case INSN_CLASS_ZQINX: return "q' or `zqinx"; case INSN_CLASS_ZBA: return "zba"; diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 0d1fbcf8fc5..fffe0486b15 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,8 +368,8 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH, INSN_CLASS_Q_AND_ZFH, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d6abe21e3c8..b3d15138fb8 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -724,115 +724,115 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{"fsgnjn.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{"fsgnjx.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fmin.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{"fmax.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fcvt.d.w", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fclass.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{"feq.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{"flt.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fle.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fgt.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fge.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, /* Quad-precision floating-point instruction subset. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, +{"fsgnjn.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, +{"fsgnjx.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, +{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, +{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, +{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, +{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, +{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, +{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, +{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, +{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, +{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, +{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, +{"fmin.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, +{"fmax.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, +{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, +{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, +{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, +{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, +{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, +{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, +{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, +{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, +{"fcvt.q.w", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, +{"fcvt.q.wu", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.q.s", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, +{"fcvt.q.d", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, +{"fclass.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, +{"feq.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, +{"flt.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{"fle.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fgt.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{"fge.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (5 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI ` (3 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds floating point register number validation on Zdinx/Zqinx extensions by separating handling on D/Q and Zdinx/Zqinx extensions (per-xlen on Zdinx/Zqinx). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Change meanings of renamed instruction classes. (riscv_multi_subset_supports_ext): Change meanings of renamed instruction classes. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new instruction flag INSN_F_OR_X. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Re-add INSN_CLASS_D_OR_ZDINX and INSN_CLASS_Q_OR_ZQINX as diagnostics- only instruction classes. (INSN_F_OR_X): New pinfo flag for better error handling. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new matching functions and pinfo flag. --- bfd/elfxx-riscv.c | 16 +- gas/config/tc-riscv.c | 20 +- include/opcode/riscv.h | 6 + opcodes/riscv-opc.c | 539 +++++++++++++++++++++++++++++++++-------- 4 files changed, 471 insertions(+), 110 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 79b601c5518..d41520404eb 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2356,12 +2356,16 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_F_OR_ZFINX: return (riscv_subset_supports (rps, "f") || riscv_subset_supports (rps, "zfinx")); - case INSN_CLASS_ZDINX: + case INSN_CLASS_D_OR_ZDINX: return (riscv_subset_supports (rps, "d") || riscv_subset_supports (rps, "zdinx")); - case INSN_CLASS_ZQINX: + case INSN_CLASS_Q_OR_ZQINX: return (riscv_subset_supports (rps, "q") || riscv_subset_supports (rps, "zqinx")); + case INSN_CLASS_ZDINX: + return riscv_subset_supports (rps, "zdinx"); + case INSN_CLASS_ZQINX: + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZFH: return riscv_subset_supports (rps, "zfh"); case INSN_CLASS_D_AND_ZFH: @@ -2468,10 +2472,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "c"; case INSN_CLASS_F_OR_ZFINX: return "f' or `zfinx"; - case INSN_CLASS_ZDINX: + case INSN_CLASS_D_OR_ZDINX: return "d' or `zdinx"; - case INSN_CLASS_ZQINX: + case INSN_CLASS_Q_OR_ZQINX: return "q' or `zqinx"; + case INSN_CLASS_ZDINX: + return "zdinx"; + case INSN_CLASS_ZQINX: + return "zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 1b730b4be36..4848d5418bf 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2259,6 +2259,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, int argnum; const struct percent_op_match *p; struct riscv_ip_error error; + enum riscv_insn_class insn_class; error.msg = "unrecognized opcode"; error.statement = str; error.missing_ext = NULL; @@ -2285,8 +2286,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) { - error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, - insn->insn_class); + insn_class = insn->insn_class; + if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_F_OR_X) + switch (insn_class) + { + case INSN_CLASS_D: + case INSN_CLASS_ZDINX: + insn_class = INSN_CLASS_D_OR_ZDINX; + break; + case INSN_CLASS_Q: + case INSN_CLASS_ZQINX: + insn_class = INSN_CLASS_Q_OR_ZQINX; + break; + default: + } + if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class)) + error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, + insn_class); continue; } diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index fffe0486b15..aac109a2c40 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,6 +368,8 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_F_OR_ZFINX, + INSN_CLASS_D_OR_ZDINX, /* Diagnostics only. */ + INSN_CLASS_Q_OR_ZQINX, /* Diagnostics only. */ INSN_CLASS_ZDINX, INSN_CLASS_ZQINX, INSN_CLASS_ZFH, @@ -464,6 +466,10 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has different entry that shares the name but differs + in register operands (FPR or GPR) used. */ +#define INSN_F_OR_X 0x00000080 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index b3d15138fb8..22a7962c7a9 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -715,7 +856,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. D/Zdinx instructions that + share the name must have INSN_F_OR_X flag. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -724,115 +867,303 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, - -/* Quad-precision floating-point instruction subset. */ +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, + +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. Q/Zqinx instructions that + share the name must have INSN_F_OR_X flag. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_F_OR_X }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_F_OR_X }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_F_OR_X }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, INSN_F_OR_X }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_F_OR_X }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_F_OR_X }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (6 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI ` (2 subsequent siblings) 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds several assembler tests for Zdinx register pairs. gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++++++++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++++++++++ 5 files changed, 357 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..62451c74d80 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rtz' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rtz' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rtz' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rtz' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rtz' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rtz' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rtz' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rtz' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rtz' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rtz' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rtz' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rtz' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rtz' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rtz' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rtz' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rtz' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rtz' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..5539d9ef3fc --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rtz + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rtz + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rtz + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rtz + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rtz + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rtz + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rtz + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rtz + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rtz + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rtz + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rtz + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rtz + fsqrt.d a1, a2 + fsqrt.d a1, a2, rtz + fsqrt.d a0, a1 + fsqrt.d a0, a1, rtz + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rtz + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rtz + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rtz + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rtz + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rtz + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rtz + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rtz + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rtz + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rtz + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rtz + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rtz + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rtz + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rtz + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rtz + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rtz + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rtz + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rtz + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rtz + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rtz + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rtz + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rtz + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rtz + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..5e3c1a88592 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e61553[ ]+fadd.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae61553[ ]+fsub.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e61553[ ]+fmul.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae61553[ ]+fdiv.d[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a061553[ ]+fsqrt.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e61543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6154f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e61547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6154b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2061553[ ]+fcvt.w.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20615d3[ ]+fcvt.w.d[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2161553[ ]+fcvt.wu.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21615d3[ ]+fcvt.wu.d[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40161553[ ]+fcvt.s.d[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401615d3[ ]+fcvt.s.d[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..62807248e77 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rtz + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rtz + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rtz + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rtz + fsqrt.d a0, a2 + fsqrt.d a0, a2, rtz + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rtz + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rtz + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rtz + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rtz + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rtz + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rtz + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rtz + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rtz + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rtz + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rtz + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 09/11] RISC-V: Add disassembler tests for Zdinx regs 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (7 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI 2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commid adds disassembler tests for invalid Zdinx register numbers (make sure that we don't disassemble invalid encodings). gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. --- gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d | 11 +++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s | 5 +++++ 2 files changed, 16 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..aa0c72cae87 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn 0x02627153 + # fadd.d x3, x5, x7 (invalid) + .insn 0x0272f1d3 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (8 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI @ 2022-05-22 5:15 ` Tsukasa OI 2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commit adds several assembler tests for Zqinx register pairs / quad-register groups. gas/ChangeLog: * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 10 files changed, 1008 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..ad8aa69ffd7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rtz' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rtz' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rtz' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rtz' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rtz' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rtz' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rtz' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rtz' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rtz' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rtz' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rtz' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rtz' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rtz' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rtz' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rtz' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rtz' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rtz' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..f1437239202 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rtz + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rtz + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rtz + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rtz + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rtz + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rtz + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rtz + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rtz + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rtz + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rtz + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rtz + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rtz + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rtz + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rtz + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rtz + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rtz + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rtz + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rtz + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rtz + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rtz + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rtz + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rtz + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rtz + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rtz + fsqrt.q x5, x8 + fsqrt.q x5, x8, rtz + fsqrt.q x6, x8 + fsqrt.q x6, x8, rtz + fsqrt.q x4, x5 + fsqrt.q x4, x5, rtz + fsqrt.q x4, x6 + fsqrt.q x4, x6, rtz + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rtz + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rtz + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rtz + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rtz + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rtz + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rtz + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rtz + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rtz + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rtz + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rtz + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rtz + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rtz + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rtz + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rtz + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rtz + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rtz + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rtz + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rtz + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rtz + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rtz + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rtz + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rtz + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rtz + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rtz + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rtz + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rtz + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rtz + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rtz + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rtz + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rtz + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rtz + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rtz + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rtz + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rtz + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rtz + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rtz + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rtz + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rtz + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rtz + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rtz + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rtz + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..414b10e48cc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rtz' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rtz' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rtz' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rtz' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rtz' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rtz' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rtz' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rtz' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rtz' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rtz' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rtz' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rtz' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rtz' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rtz' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rtz' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rtz' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rtz' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rtz' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..f01c4f98b9f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rtz + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rtz + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rtz + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rtz + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rtz + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rtz + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rtz + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rtz + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rtz + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rtz + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rtz + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rtz + fsqrt.q a1, a2 + fsqrt.q a1, a2, rtz + fsqrt.q a0, a1 + fsqrt.q a0, a1, rtz + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rtz + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rtz + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rtz + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rtz + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rtz + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rtz + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rtz + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rtz + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rtz + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rtz + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rtz + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rtz + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rtz + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rtz + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rtz + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rtz + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rtz + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rtz + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rtz + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rtz + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rtz + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rtz + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rtz + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rtz + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rtz + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rtz + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rtz + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rtz + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rtz + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rtz + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rtz + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rtz + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..62eefdf69f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e61553[ ]+fadd.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee61553[ ]+fsub.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e61553[ ]+fmul.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee61553[ ]+fdiv.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e061553[ ]+fsqrt.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e61543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6154f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e61547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6154b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6061553[ ]+fcvt.w.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60615d3[ ]+fcvt.w.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6161553[ ]+fcvt.wu.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61615d3[ ]+fcvt.wu.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6261553[ ]+fcvt.l.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62615d3[ ]+fcvt.l.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6361553[ ]+fcvt.lu.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63615d3[ ]+fcvt.lu.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6261553[ ]+fcvt.q.l[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6259553[ ]+fcvt.q.l[ ]+a0,a1,rtz +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6361553[ ]+fcvt.q.lu[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6359553[ ]+fcvt.q.lu[ ]+a0,a1,rtz +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40361553[ ]+fcvt.s.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403615d3[ ]+fcvt.s.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42361553[ ]+fcvt.d.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423615d3[ ]+fcvt.d.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..0c80749fd66 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rtz + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rtz + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rtz + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rtz + fsqrt.q a0, a2 + fsqrt.q a0, a2, rtz + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rtz + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rtz + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rtz + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rtz + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rtz + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rtz + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rtz + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rtz + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rtz + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rtz + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rtz + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rtz + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rtz + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, rtz + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rtz + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, rtz + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rtz + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rtz + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rtz + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rtz + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 11/11] RISC-V: Add disassembler tests for Zqinx regs 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI ` (9 preceding siblings ...) 2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI @ 2022-05-22 5:16 ` Tsukasa OI 10 siblings, 0 replies; 39+ messages in thread From: Tsukasa OI @ 2022-05-22 5:16 UTC (permalink / raw) To: Tsukasa OI; +Cc: binutils This commid adds disassembler tests for invalid Zqinx register numbers (make sure that we don't disassemble invalid encodings). gas/ChangeLog: * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. --- gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s | 7 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d | 11 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s | 5 +++++ 4 files changed, 35 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..e11e671ecdc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn 0x06c47253 + # fadd.q x5, x9, x13 (invalid) + .insn 0x06d4f2d3 + # fadd.q x6, x10, x14 (invalid) + .insn 0x06e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..9edeae84ba7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn 0x06627153 + # fadd.q x3, x5, x7 (invalid) + .insn 0x0672f1d3 -- 2.34.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2022-05-22 5:17 UTC | newest] Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI 2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-08 9:51 ` Tsukasa OI 2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI 2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt 2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI 2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI 2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI 2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI 2022-02-08 2:00 ` Palmer Dabbelt 2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI 2022-02-08 2:01 ` Palmer Dabbelt 2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI 2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI 2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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