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* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-27 20:50 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-27 20:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:dceb9d2a8859af37f420abd2272880952d54a35c
commit dceb9d2a8859af37f420abd2272880952d54a35c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 16:50:41 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 49 ++--------------------
| 29 -------------
2 files changed, 4 insertions(+), 74 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3a4b8cdb02a..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3566,28 +3565,7 @@
}
[(set_attr "type" "fpload,fpload,fpload,load")
(set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v,*")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v")])
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3607,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3616,7 +3594,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-05-01 17:16 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-05-01 17:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:244505d792d0d6d8856a28a726b625e2a84f9d9e
commit 244505d792d0d6d8856a28a726b625e2a84f9d9e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 13:16:42 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 87 ++++++++++-----------------------------------
gcc/config/rs6000/vsx.md | 6 ++--
2 files changed, 21 insertions(+), 72 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0e04f7151f1..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,72 +7841,33 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
}
- /* Deal with Altivec style addresses. These come up on the power8 when GCC
- generates the Altivec load/store (LVX and STVX) to eliminate byte swapping
- the vectors. */
- else if (GET_CODE (addr) == AND
- && CONST_INT_P (XEXP (addr, 1))
- && INTVAL (XEXP (addr, 1)) == -16)
- {
- rtx op0 = XEXP (addr, 0);
- rtx op1 = XEXP (addr, 1);
-
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* Is this reg+reg? */
- if (GET_CODE (op0) == PLUS)
- {
- rtx plus_tmp = (can_create_pseudo_p ()
- ? gen_reg_rtx (Pmode)
- : base_tmp);
-
- emit_insn (gen_rtx_SET (plus_tmp, op0));
- op0 = plus_tmp;
- }
-
- emit_insn (gen_rtx_SET (base_tmp,
- gen_rtx_AND (Pmode, op0, op1)));
- new_addr = base_tmp;
- }
-
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- emit_insn (gen_rtx_SET (base_tmp, addr));
+ emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e0c29353b38..d156c9bd90b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4035,7 +4035,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
@@ -4068,7 +4068,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(any_extend:DI (match_dup 4)))]
{
@@ -4101,7 +4101,7 @@
"=X, X, &b, X, &b"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0)
(zero_extend:GPR (match_dup 4)))]
{
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-29 1:28 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-29 1:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:20d3a09037cd05d36fc9d73eae93fb75dead73bc
commit 20d3a09037cd05d36fc9d73eae93fb75dead73bc
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 21:28:23 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 127 +++------------------
| 35 ------
| 29 -----
| 22 ----
| 35 ------
| 36 ------
| 0
| 35 ------
| 36 ------
| 0
10 files changed, 16 insertions(+), 339 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60e686f2bfa..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3555,33 +3549,12 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-;; 8: GPR 0 any normal address no
-;; 9: GPR 0-3 any offsettable address no
-;; 10: GPR 0-3 any single register yes
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand"
- "=f, f, f, v, v, v, v,
- ?r, ?r, ?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o,
- m, o, Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "O, n, n, O, n, O, n,
- O, n, n")])))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X,
- X, X, &b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
"&& reload_completed"
@@ -3590,47 +3563,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload,
- load, load, load")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v,
- *, *, *")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand"
- "=f, f, f, v, v, v, v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "=X, X, &b, X, &b, X, X")]))))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3667,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -4014,34 +3930,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. For vector registers, we require X-form addressing.
-;; Alternatives:
-;; 1: GPR, element 0, normal address
-;; 2: GPR, element 0-n, offsettable address (fold offset)
-;; 3: GPR, element 0-n, single register (op[3] has offset)
-;; 4: FP/VMX, element 0, X-form address
-;; 5: FP/VMX, element 0-n, single register (op[3] has offset)
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand"
- "=r,r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel
- [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,n,O,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 61f021ee99f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 2561aa930b6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e59ceae6866..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 052371e72ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 65ae21b1a1c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 6a2f23cfc57..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index e69de29bb2d..00000000000
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 22:57 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 22:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:37ab1b98ce5aafc0e8bc2a2dd2478f1f560ee96f
commit 37ab1b98ce5aafc0e8bc2a2dd2478f1f560ee96f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 18:57:10 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 156 +--------------------
| 35 -----
| 29 ----
| 22 ---
| 35 -----
| 36 -----
| 35 -----
| 36 -----
8 files changed, 7 insertions(+), 377 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f25b29855f4..7121f50a449 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3555,22 +3555,12 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
-;; Alternatives:
-;; 1: Load FPR, index 0, normal address, no address change.
-;; 2: Load FPR, index 0-3, offsettable address, element folded into addr.
-;; 3: Load FPR, index 0-3, single register, offset in op[3].
-;; 4: Load VMX, index 0, x-form, power8, no address change.
-;; 5: Load VMX, index 0-3, single register, power8, offset in op[3].
-;; 6: Load VMX, index 0, normal address, power9, no address change.
-;; 7: Load VMX, index 0-3, offsettable address, power9, element in addr.
-;; 8: Load GPR, index 0-3, single register, offset in op[3].
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f,v,v,v,v,?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,o,Q,Z,Q,m,o,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n,O,n,n")])))
- (clobber (match_scratch:P 3 "=X,X,&b,X,&b,X,X,&b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
"&& reload_completed"
@@ -3579,38 +3569,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,fpload,fpload,fpload,fpload,fpload,fpload,load")
- (set_attr "length" "4,4,8,4,8,4,4,8")
- (set_attr "isa" "*,*,*,p8v,p8v,p9v,p9v,*")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-;; Alternatives:
-;; 1: Load FPR, index 0, normal address, no address change.
-;; 2: Load FPR, index 0-3, offsettable address, element folded into addr.
-;; 3: Load FPR, index 0-3, single register, offset in op[3].
-;; 4: Load VMX, index 0, x-form, power8, no address change.
-;; 5: Load VMX, index 0-3, single register, power8, offset in op[3].
-;; 6: Load VMX, index 0, normal address, power9, no address change.
-;; 7: Load VMX, index 0-3, offsettable address, power9, element in addr.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f,v,v,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,o,Q,Z,Q,m,o")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n,O,n")]))))
- (clobber (match_scratch:P 3 "=X,X,&b,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "4,4,8,4,8,4,4")
- (set_attr "isa" "*,*,*,p8v,p8v,p9v,p9v")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3647,25 +3608,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -4023,90 +3965,6 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-;; Alternatives:
-;; 1: GPR, element 0, normal address, no modification
-;; 2: GPR, element 0-3, offsettable address
-;; 3: GPR, element 0-3, single register (offset to op[3])
-;; 4: VSX, element 0, X-form address, no modification
-;; 5: VSX, element 0-3, single register (offset to op[3])
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-;; Alternatives:
-;; 1: GPR, element 0, normal address, no modification
-;; 2: GPR, element 0-3, offsettable address
-;; 3: GPR, element 0-3, single register (offset to op[3])
-;; 4: VMX, element 0, X-form address, no modification
-;; 5: VMX, element 0-3, single register (offset to op[3])
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand"
- "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-;; Alternatives:
-;; 1: GPR, element 0, normal address, no modification
-;; 2: GPR, element 0-3, offsettable address
-;; 3: GPR, element 0-3, single register (offset to op[3])
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,m")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 61f021ee99f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 2561aa930b6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e59ceae6866..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 052371e72ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 65ae21b1a1c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 6a2f23cfc57..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 21:39 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 21:39 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ca77b320a2eee68bcb74fe91b23080f46461e344
commit ca77b320a2eee68bcb74fe91b23080f46461e344
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 17:39:36 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 25 +++----------------------
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c0f5b37ae1e..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3585,16 +3585,16 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
- (unspec:SF [(match_operand:V4SF 1 "non_altivec_memory_operand" "Q,Q")
+ (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3602,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "non_altivec_memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 21:30 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 21:30 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5de5d306dac1f6b24759b44a508cd7fd83680b7e
commit 5de5d306dac1f6b24759b44a508cd7fd83680b7e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 17:29:57 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/predicates.md | 10 -
gcc/config/rs6000/rs6000.cc | 58 ++--
gcc/config/rs6000/rs6000.md | 3 -
gcc/config/rs6000/vsx.md | 321 ++-------------------
| 35 ---
| 41 ---
| 29 --
| 22 --
| 35 ---
| 36 ---
| 31 --
| 40 ---
| 40 ---
| 29 --
| 29 --
| 35 ---
| 36 ---
| 19 --
| 41 ---
19 files changed, 37 insertions(+), 853 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 3b9265ef1c0..52c65534e51 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -957,16 +957,6 @@
return memory_operand (op, mode);
})
-;; Anything that matches memory_operand but does not match
-;; altivec_indexed_or_indirect_operand. This used by vec_extract memory
-;; optimizations.
-(define_predicate "non_altivec_memory_operand"
- (match_code "mem")
-{
- return (memory_operand (op, mode)
- && !altivec_indexed_or_indirect_operand (op, mode));
-})
-
;; Return 1 if the operand is a MEM with an indexed-form address.
(define_special_predicate "indexed_address_mem"
(match_test "(MEM_P (op)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 332cb862f54..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- emit_insn (gen_rtx_SET (base_tmp, addr));
+ emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e70266e5729..c0f5b37ae1e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3555,16 +3549,15 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "non_altivec_memory_operand" "m,Z,m,m")
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3572,28 +3565,7 @@
}
[(set_attr "type" "fpload,fpload,fpload,load")
(set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v,*")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "non_altivec_memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v")])
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3977,146 +3949,20 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. For vector registers, we require X-form addressing.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "non_altivec_memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "non_altivec_memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=f,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "Q,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "non_altivec_memory_operand" "Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "non_altivec_memory_operand" "m")
- (parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
@@ -4141,153 +3987,24 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
-;; on power8 due to the vector byte swap support which creates Altivec
-;; addresses. These are eliminated after register allocation since we use 'Q'
-;; or 'Z' constraints.
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "non_altivec_memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "non_altivec_memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "non_altivec_memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
-;; Fold extracting a V4SI element with a variable element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (any_float:SFDF
- (unspec:SI
- [(match_operand:V4SI 1 "non_altivec_memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Fold extracting a V8HI/V16QI element with a variable element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unsigned_float:SFDF
- (unspec:<VSX_EXTRACT_I2:VEC_base>
- [(match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 61f021ee99f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index a537dfe2350..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIBZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 2561aa930b6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e59ceae6866..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 052371e72ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index f6b027db3bc..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 95805325e9e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index 3cf9bafd4f3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-6.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-6.c
deleted file mode 100644
index e08a3587eb2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-6.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-double
-extract_dbl_uns_v4si_n (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_n_index_4 (vector unsigned int *p, size_t n)
-{
- return vec_extract (p[4], n); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-7.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-7.c
deleted file mode 100644
index ddba763a395..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-7.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-double
-extract_dbl_sign_v4si_n (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_n_index_4 (vector int *p, size_t n)
-{
- return vec_extract (p[4], n); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 65ae21b1a1c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 6a2f23cfc57..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index a1d3947fabb..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 533a80d3d52..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIHZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 19:07 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 19:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4bec3326965c6b656584d5b425fb1b258654166f
commit 4bec3326965c6b656584d5b425fb1b258654166f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 15:07:43 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 3 --
gcc/config/rs6000/vsx.md | 56 ----------------------
| 41 ----------------
| 40 ----------------
| 40 ----------------
| 41 ----------------
6 files changed, 221 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bf07d62606a..e33675781ce 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4043,62 +4043,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p9v")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "non_altivec_memory_operand" "Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
;; Fold extracting a V8HI element with a constant element with sign extension
;; to either DImode or SImode.
(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index a537dfe2350..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIBZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 95805325e9e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index 3cf9bafd4f3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 533a80d3d52..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIHZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 18:28 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 18:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7cf41bef63699170ed47369c069a99e9f70cbac8
commit 7cf41bef63699170ed47369c069a99e9f70cbac8
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 14:28:13 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dc8d45d30e7..feb7fc753a6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4085,28 +4085,23 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
-;; on power8 due to the vector byte swap support which creates Altivec
-;; addresses. These are eliminated after register allocation since we use 'Q'
-;; or 'Z' constraints.
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "non_altivec_memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 18:11 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 18:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0a8feb2776ceb24ac1c89fe0b216a0bc7992a9d5
commit 0a8feb2776ceb24ac1c89fe0b216a0bc7992a9d5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 14:11:43 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 29 ++++++++--------------
| 0
| 0
| 0
| 0
| 0
6 files changed, 10 insertions(+), 19 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ecf1279c95b..42336bbf36b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3977,26 +3971,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. For vector registers, we require X-form addressing.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..e69de29bb2d
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 17:33 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 17:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d983d746c931a0ee8ae86f2f1407779a4fafc8f3
commit d983d746c931a0ee8ae86f2f1407779a4fafc8f3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 13:33:23 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 87 ++-----
gcc/config/rs6000/rs6000.md | 3 -
gcc/config/rs6000/vsx.md | 282 ++-------------------
| 35 ---
| 41 ---
| 29 ---
| 22 --
| 35 ---
| 36 ---
| 31 ---
| 40 ---
| 40 ---
| 35 ---
| 36 ---
| 19 --
| 41 ---
16 files changed, 37 insertions(+), 775 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0e04f7151f1..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,72 +7841,33 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
}
- /* Deal with Altivec style addresses. These come up on the power8 when GCC
- generates the Altivec load/store (LVX and STVX) to eliminate byte swapping
- the vectors. */
- else if (GET_CODE (addr) == AND
- && CONST_INT_P (XEXP (addr, 1))
- && INTVAL (XEXP (addr, 1)) == -16)
- {
- rtx op0 = XEXP (addr, 0);
- rtx op1 = XEXP (addr, 1);
-
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* Is this reg+reg? */
- if (GET_CODE (op0) == PLUS)
- {
- rtx plus_tmp = (can_create_pseudo_p ()
- ? gen_reg_rtx (Pmode)
- : base_tmp);
-
- emit_insn (gen_rtx_SET (plus_tmp, op0));
- op0 = plus_tmp;
- }
-
- emit_insn (gen_rtx_SET (base_tmp,
- gen_rtx_AND (Pmode, op0, op1)));
- new_addr = base_tmp;
- }
-
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- emit_insn (gen_rtx_SET (base_tmp, addr));
+ emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7fa64dca29a..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3555,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3564,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3572,28 +3565,7 @@
}
[(set_attr "type" "fpload,fpload,fpload,load")
(set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v,*")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v")])
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3613,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3622,7 +3594,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3630,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3977,146 +3930,20 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. For vector registers, we require X-form addressing.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p9v")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
@@ -4141,92 +3968,21 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
-;; on power8 due to the vector byte swap support which creates Altivec
-;; addresses. These are eliminated after register allocation since we use 'Q'
-;; or 'Z' constraints.
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 61f021ee99f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index a537dfe2350..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIBZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 2561aa930b6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e59ceae6866..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 052371e72ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index f6b027db3bc..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 95805325e9e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index 3cf9bafd4f3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 65ae21b1a1c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 6a2f23cfc57..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index a1d3947fabb..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 533a80d3d52..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIHZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 6:29 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 6:29 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:36affc7dd7f6557971477250aa953345fb7e9671
commit 36affc7dd7f6557971477250aa953345fb7e9671
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 02:29:11 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 3 --
gcc/config/rs6000/vsx.md | 56 ----------------------
| 40 ----------------
| 40 ----------------
| 40 ----------------
| 40 ----------------
6 files changed, 219 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7fa64dca29a..838caaab9ec 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4043,62 +4043,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p9v")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
;; Fold extracting a V8HI element with a constant element with sign extension
;; to either DImode or SImode.
(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index fd6b6d03699..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 79f634b33b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index d51d26482c3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 24ad6fd3a7e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-28 3:57 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-28 3:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9e16acd335b28021ca87cd950d470d40dc513ec6
commit 9e16acd335b28021ca87cd950d470d40dc513ec6
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 23:57:27 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 58 ++++++++++++++-------------------------------
1 file changed, 18 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 332cb862f54..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- emit_insn (gen_rtx_SET (base_tmp, addr));
+ emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-27 19:33 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-27 19:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:670ba6be726f7e3c7c351cadfcbf1a622935a804
commit 670ba6be726f7e3c7c351cadfcbf1a622935a804
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 15:33:51 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 ++++++++++++++-------------------------------
1 file changed, 17 insertions(+), 39 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-27 19:11 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-27 19:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b88b631d6981f177487212d322bdb832c2fa8cbd
commit b88b631d6981f177487212d322bdb832c2fa8cbd
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 15:11:22 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 ++---
gcc/config/rs6000/rs6000.md | 3 -
gcc/config/rs6000/vsx.md | 278 ++-------------------
| 35 ---
| 40 ---
| 35 ---
| 36 ---
| 31 ---
| 40 ---
| 40 ---
| 35 ---
| 36 ---
| 19 --
| 40 ---
14 files changed, 33 insertions(+), 691 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2a5a9b45e34..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3555,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3574,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory with constant element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p7v,p9v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3630,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3977,151 +3930,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. If the element number is 0 or the address is offsettable, we don't
-;; need a temporary base register. For vector registers, we require X-form
-;; addressing.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,n,O,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
@@ -4143,92 +3968,21 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
-;; on power8 due to the vector byte swap support which creates Altivec
-;; addresses. These are eliminated after register allocation since we use 'Q'
-;; or 'Z' constraints.
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 61f021ee99f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index fd6b6d03699..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e59ceae6866..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 052371e72ef..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index f6b027db3bc..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 79f634b33b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index d51d26482c3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 65ae21b1a1c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 6a2f23cfc57..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index a1d3947fabb..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 24ad6fd3a7e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-27 2:58 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-27 2:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1aae4cc74b48ec33740548412ef4c3e9f57ba855
commit 1aae4cc74b48ec33740548412ef4c3e9f57ba855
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 22:58:42 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 66 ----------------------
| 31 ----------
| 19 -------
3 files changed, 116 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 62f9702554a..19a502b99a3 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4110,72 +4110,6 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index f6b027db3bc..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index a1d3947fabb..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-27 2:51 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-27 2:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:740252409e56eb3c22b9c336ba524f442cc2c4e2
commit 740252409e56eb3c22b9c336ba524f442cc2c4e2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 22:51:16 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..003bd534119 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,23 +4089,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-27 2:48 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-27 2:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f3b776659ca12b3f13091fb506f480ebb96e1b8d
commit f3b776659ca12b3f13091fb506f480ebb96e1b8d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 22:48:16 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 3 -
gcc/config/rs6000/vsx.md | 122 ---------------------
| 40 -------
| 31 ------
| 40 -------
| 40 -------
| 19 ----
| 40 -------
8 files changed, 335 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bbc049dc44f..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4045,62 +4045,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,p9v,p9v")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
;; Fold extracting a V8HI element with a constant element with sign extension
;; to either DImode or SImode.
(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
@@ -4163,72 +4107,6 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index fd6b6d03699..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index f6b027db3bc..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 79f634b33b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index d51d26482c3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index a1d3947fabb..e69de29bb2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 24ad6fd3a7e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-26 23:55 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-26 23:55 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d9b6ff3eb2edbeb80bcb8f7b1aa2c01275b0b872
commit d9b6ff3eb2edbeb80bcb8f7b1aa2c01275b0b872
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 19:55:49 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 3 --
gcc/config/rs6000/vsx.md | 56 ----------------------
| 40 ----------------
| 40 ----------------
| 40 ----------------
| 40 ----------------
6 files changed, 219 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1e3750f528..7d6c94aee5b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1807c192d08..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4045,62 +4045,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,p9v,p9v")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8,12")])
-
;; Fold extracting a V8HI element with a constant element with sign extension
;; to either DImode or SImode.
(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index fd6b6d03699..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 79f634b33b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index d51d26482c3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 24ad6fd3a7e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register.. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-26 15:37 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-26 15:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:31dd0a8cefcf602ef2d4ceaad30bcdb8ebbd2a90
commit 31dd0a8cefcf602ef2d4ceaad30bcdb8ebbd2a90
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 11:37:21 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 85 ++--------------------
| 35 ---------
| 35 ---------
| 36 ---------
| 0
| 35 ---------
| 36 ---------
| 0
8 files changed, 8 insertions(+), 254 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..0b7b26c2e2f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,73 +4000,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4089,23 +4022,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 046a203cebc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 6341a59433c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index f86935e51d2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index e1cf0c91048..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 43e889acb5c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
new file mode 100644
index 00000000000..e69de29bb2d
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-26 15:35 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-26 15:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5a759794517862efcfa7ac6a5b18afdb6e16bd5e
commit 5a759794517862efcfa7ac6a5b18afdb6e16bd5e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 11:35:06 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 66 ----------------------
| 31 ----------
| 19 -------
3 files changed, 116 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4a93523090a..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,72 +4107,6 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f6b027db3bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index a1d3947fabb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-26 5:05 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-26 5:05 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1d5a05be9b61c96d73f28bed4ebc44655902e1c7
commit 1d5a05be9b61c96d73f28bed4ebc44655902e1c7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 01:05:04 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 ++++++--------
gcc/config/rs6000/genfusion.pl | 26 ++++------------------
gcc/config/rs6000/rs6000.md | 2 +-
gcc/testsuite/g++.target/powerpc/pr105325.C | 24 --------------------
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 ++--
5 files changed, 14 insertions(+), 59 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 4f367cadc52..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -56,7 +56,7 @@ sub mode_to_ldst_char
sub gen_ld_cmpi_p10
{
my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
- $mempred, $ccmode, $np, $extend, $resultmode, $constraint);
+ $mempred, $ccmode, $np, $extend, $resultmode);
LMODE: foreach $lmode ('DI','SI','HI','QI') {
$ldst = mode_to_ldst_char($lmode);
$clobbermode = $lmode;
@@ -71,34 +71,21 @@ sub gen_ld_cmpi_p10
CCMODE: foreach $ccmode ('CC','CCUNS') {
$np = "NON_PREFIXED_D";
$mempred = "non_update_memory_operand";
- $constraint = "m";
if ( $ccmode eq 'CC' ) {
next CCMODE if $lmode eq 'QI';
- if ( $lmode eq 'HI' ) {
- $np = "NON_PREFIXED_D";
- $mempred = "non_update_memory_operand";
- $echr = "a";
- } elsif ( $lmode eq 'SI' ) {
- # ld and lwa are both DS-FORM.
- $np = "NON_PREFIXED_DS";
- $mempred = "lwa_operand";
- $echr = "a";
- $constraint = "YZ";
- } elsif ( $lmode eq 'DI' ) {
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
# ld and lwa are both DS-FORM.
$np = "NON_PREFIXED_DS";
$mempred = "ds_form_mem_operand";
- $echr = "";
- $constraint = "YZ";
}
$cmpl = "";
+ $echr = "a";
$constpred = "const_m1_to_1_operand";
} else {
if ( $lmode eq 'DI' ) {
# ld is DS-form, but lwz is not.
$np = "NON_PREFIXED_DS";
$mempred = "ds_form_mem_operand";
- $constraint = "YZ";
}
$cmpl = "l";
$echr = "z";
@@ -121,7 +108,7 @@ sub gen_ld_cmpi_p10
print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"${constraint}\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
if ($ccmode eq 'CCUNS') { print " "; }
print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
if ($result eq 'clobber') {
@@ -150,11 +137,6 @@ sub gen_ld_cmpi_p10
print " \"\"\n";
print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign") {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
print " (set_attr \"length\" \"8\")])\n";
print "\n";
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7d6c94aee5b..ec783803820 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -302,7 +302,7 @@
(eq_attr "maybe_prefixed" "no"))
(const_string "no")
- (eq_attr "type" "load,fpload,vecload,vecload,fused_load_cmpi")
+ (eq_attr "type" "load,fpload,vecload")
(if_then_else (match_test "prefixed_load_p (insn)")
(const_string "yes")
(const_string "no"))
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index f4ab384daa7..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 22:46 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 22:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0219e89d01e46892b53991cd976f9361e034f0fe
commit 0219e89d01e46892b53991cd976f9361e034f0fe
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 18:46:32 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 ++++++--------
gcc/config/rs6000/genfusion.pl | 26 ++++------------------
gcc/config/rs6000/rs6000.md | 2 +-
gcc/testsuite/g++.target/powerpc/pr105325.C | 24 --------------------
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 ++--
5 files changed, 14 insertions(+), 59 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 4f367cadc52..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -56,7 +56,7 @@ sub mode_to_ldst_char
sub gen_ld_cmpi_p10
{
my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
- $mempred, $ccmode, $np, $extend, $resultmode, $constraint);
+ $mempred, $ccmode, $np, $extend, $resultmode);
LMODE: foreach $lmode ('DI','SI','HI','QI') {
$ldst = mode_to_ldst_char($lmode);
$clobbermode = $lmode;
@@ -71,34 +71,21 @@ sub gen_ld_cmpi_p10
CCMODE: foreach $ccmode ('CC','CCUNS') {
$np = "NON_PREFIXED_D";
$mempred = "non_update_memory_operand";
- $constraint = "m";
if ( $ccmode eq 'CC' ) {
next CCMODE if $lmode eq 'QI';
- if ( $lmode eq 'HI' ) {
- $np = "NON_PREFIXED_D";
- $mempred = "non_update_memory_operand";
- $echr = "a";
- } elsif ( $lmode eq 'SI' ) {
- # ld and lwa are both DS-FORM.
- $np = "NON_PREFIXED_DS";
- $mempred = "lwa_operand";
- $echr = "a";
- $constraint = "YZ";
- } elsif ( $lmode eq 'DI' ) {
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
# ld and lwa are both DS-FORM.
$np = "NON_PREFIXED_DS";
$mempred = "ds_form_mem_operand";
- $echr = "";
- $constraint = "YZ";
}
$cmpl = "";
+ $echr = "a";
$constpred = "const_m1_to_1_operand";
} else {
if ( $lmode eq 'DI' ) {
# ld is DS-form, but lwz is not.
$np = "NON_PREFIXED_DS";
$mempred = "ds_form_mem_operand";
- $constraint = "YZ";
}
$cmpl = "l";
$echr = "z";
@@ -121,7 +108,7 @@ sub gen_ld_cmpi_p10
print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"${constraint}\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
if ($ccmode eq 'CCUNS') { print " "; }
print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
if ($result eq 'clobber') {
@@ -150,11 +137,6 @@ sub gen_ld_cmpi_p10
print " \"\"\n";
print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign") {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
print " (set_attr \"length\" \"8\")])\n";
print "\n";
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7d6c94aee5b..ec783803820 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -302,7 +302,7 @@
(eq_attr "maybe_prefixed" "no"))
(const_string "no")
- (eq_attr "type" "load,fpload,vecload,vecload,fused_load_cmpi")
+ (eq_attr "type" "load,fpload,vecload")
(if_then_else (match_test "prefixed_load_p (insn)")
(const_string "yes")
(const_string "no"))
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index f4ab384daa7..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 15:48 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 15:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d7f650f4876ccf3ec6660b7672ad69eed4b5368b
commit d7f650f4876ccf3ec6660b7672ad69eed4b5368b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 11:48:51 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 149 +--------------------
| 35 -----
| 35 -----
| 36 -----
| 31 -----
| 35 -----
| 36 -----
| 19 ---
8 files changed, 7 insertions(+), 369 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4a93523090a..0b7b26c2e2f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,73 +4000,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4089,87 +4022,19 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 37cb9c0ae90..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 3314f0cde3a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index c8ba94ad824..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f6b027db3bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index f17bb874f01..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 47c41027a28..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index a1d3947fabb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 6:40 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 6:40 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9488d4440686bc165aac7047685dc9bc3b7e0999
commit 9488d4440686bc165aac7047685dc9bc3b7e0999
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 02:40:09 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 66 ------------------------------------------------
1 file changed, 66 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4a93523090a..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,72 +4107,6 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 6:28 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 6:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:15e6e611bf5b8c7a85c83909da860eeeb42a9e31
commit 15e6e611bf5b8c7a85c83909da860eeeb42a9e31
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 02:28:07 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 149 +--------------------
| 35 -----
| 35 -----
| 63 ---------
| 27 ----
| 35 -----
| 36 -----
| 19 ---
8 files changed, 7 insertions(+), 392 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4a93523090a..0b7b26c2e2f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,73 +4000,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4089,87 +4022,19 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 37cb9c0ae90..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 3314f0cde3a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 4d0e08908cc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index dca53f3fe3d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rldicl. */
-}
-
-/* { dg-final { scan-assembler {\mlwax\M} } } */
-/* { dg-final { scan-assembler {\mlwzx\M} } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index f17bb874f01..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 47c41027a28..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index a1d3947fabb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 2:15 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 2:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:63c6c1f4c95d7f9b643e0f085c889b94b6c26cb0
commit 63c6c1f4c95d7f9b643e0f085c889b94b6c26cb0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 22:15:32 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index cc3bc83ff9b..003bd534119 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,22 +4089,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,fpload")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 1:58 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 1:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fb1b5a0868b45ff8d6dedc037c184f9822842900
commit fb1b5a0868b45ff8d6dedc037c184f9822842900
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 21:58:48 2023 -0400
Revert patches
Diff:
---
gcc/ChangeLog.meissner | 46 +++++++++++++++
gcc/config/rs6000/vsx.md | 67 ----------------------
| 35 -----------
| 35 -----------
| 63 --------------------
| 35 -----------
| 36 ------------
7 files changed, 46 insertions(+), 271 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a31fb05b750..5210646122b 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,49 @@
+==================== Branch work119, patch #81 was reverted ====================
+
+Allow consant element vec_extract to be zero or sign extended
+
+This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
+constant element number to be zero extended. It also allows vec_extract of V4SI
+and V8HI vector types with constant element number to be sign extended.
+
+2023-04-24 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
+ (vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
+ (vsx_extract_v8hi_load_to_z<mode>): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
+ * gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
+
+==================== Branch work119, patch #80 was reverted ====================
+
+Allow consant element vec_extract to be loaded into vector registers.
+
+This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
+constant element number to be loaded into vector registers directly. It also
+will be split before register allocation.
+
+This patch also adds support to rs6000_adjust_vec_address to allow it to be run
+before register allocation.
+
+2023-04-24 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
+ register allocation.
+ (adjust_vec_address_pcrel): Likewise.
+ (rs6000_adjust_vec_address): Likewise.
+ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
+ (vsx_extract_<mode>_load): Allow vector registers to be loaded.
+
==================== Branch work119, patch #72 was reverted ====================
==================== Branch work119, patch #71 was reverted ====================
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a636a2a1470..0b7b26c2e2f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,73 +4000,6 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_z<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 37cb9c0ae90..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 3314f0cde3a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 4d0e08908cc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index f17bb874f01..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 47c41027a28..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-25 1:51 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-25 1:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3f1c236b90f69acda6ba4dcabe07d60ff407a7f4
commit 3f1c236b90f69acda6ba4dcabe07d60ff407a7f4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 21:51:19 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 ++++---------
gcc/config/rs6000/vsx.md | 91 ++--------------------
| 35 ---------
| 35 ---------
| 63 ---------------
| 35 ---------
| 36 ---------
7 files changed, 24 insertions(+), 327 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c9634980302..04877dd51f6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3977,94 +3971,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. If the element number is 0 or the address is offsettable, we don't
-;; need a temporary base register. For vector registers, we require X-form
-;; addressing.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,n,O,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")])
-
-;; Fold extracting a V8HI/V4SI element with a constant element with zero
-;; extension to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
- (zero_extend:GPR
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "*,*,8,*,8")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Fold extracting a V8HI element with a constant element with sign extension
-;; to either DImode or SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_z<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
- (sign_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
}
[(set_attr "type" "load")
- (set_attr "length" "*,*,8")])
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index 37cb9c0ae90..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_element_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 3314f0cde3a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 4d0e08908cc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlwz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index f17bb874f01..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold zero extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index 47c41027a28..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_0_index_4 (vector short *p)
-{
- return vec_extract (p[4], 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_element_3_index_4 (vector short *p)
-{
- return vec_extract (p[4], 3); /* lwa, no extsw. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlhz\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-24 22:57 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-24 22:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2949dcf321ce4ba8ad6ac9d3a6e994b122d9c82b
commit 2949dcf321ce4ba8ad6ac9d3a6e994b122d9c82b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 18:57:06 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 362 +--------------------
| 22 --
| 37 ---
| 37 ---
4 files changed, 9 insertions(+), 449 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ac8ae127055..04877dd51f6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -247,13 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Mode attribute to give the constraint for floating point when used
-;; with FL_CONV modes.
-(define_mode_attr FL_CONV_REG [(SF "wa")
- (DF "wa")
- (KF "v")
- (TF "v")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3984,15 +3971,13 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. If the element number is 0, we don't need a temporary base
-;; register. For vector registers, we require X-form addressing.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,O,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4000,173 +3985,10 @@
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V4SI element from memory with a constant element number and sign
-;; or zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,Q,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "8")])
-
-;; Extract a V8HI element from memory with a constant element number and sign
-;; or zero extend it to either SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_<su><mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r")
- (any_extend:GPR
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
-;; Extract a V16QI element from memory with a constant element number and
-;; zero extend it to either SImode or DImode.
-(define_insn_and_split "*vsx_extract_v16qi_load_to_u<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=r,r")
- (zero_extend:GPR
- (vec_select:QI
- (match_operand:V16QI 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_15_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], QImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "8")])
-
-;; Extract a V4SI/V8HI/V16QI element from memory with a constant element number
-;; and convert it to unsigned float.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I:mode>_load_to_u<FL_CONV:mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONV:FL_CONV_REG>")
- (unsigned_float:FL_CONV
- (vec_select:<VSX_EXTRACT_I:VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<VSX_EX>"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:FL_CONV (match_dup 4)))]
-{
- machine_mode base_mode = <VSX_EXTRACT_I:VEC_base>mode;
-
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- base_mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Extract a V4SI element from memory with a constant element number and
-;; convert it to signed float.
-(define_insn_and_split "*vsx_extract_v4si_load_to_s<mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONV_REG>")
- (float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<FL_CONV_REG>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (sign_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:FL_CONV (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Extract a V8HI element from memory with a constant element number and
-;; convert it to signed float. While we could do this via a LXSIHZX
-;; instruction followed by VEXTSB2D, it is better to do a LWA and MTVSRD
-;; instruction.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONV_REG>,<FL_CONV_REG>")
- (float:FL_CONV
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,Qo")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=&r,&r"))
- (clobber (match_scratch:DI 5 "=<FL_CONV_REG>,<FL_CONV_REG>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (sign_extend:DI (match_dup 6)))
- (set (match_dup 5)
- (match_dup 4))
- (set (match_dup 0)
- (float:FL_CONV (match_dup 5)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[5]) == SCRATCH)
- operands[5] = gen_reg_rtx (DImode);
-
- operands[6] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "12")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4189,12 +4011,12 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4202,175 +4024,9 @@
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; V4SI extract from memory with a variable element number converted to DImode
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p8v")])
-
-;; Extract a V8HI element from memory with a variable element number and sign
-;; or zero extend it to either SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su><mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (any_extend:GPR
- (unspec:SI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
}
[(set_attr "type" "load")])
-;; Extract a V16QI element from memory with a variable element number and zero
-;; extend it to either SImode or DImode.
-(define_insn_and_split "*vsx_extract_v16qi_var_load_to_u<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (zero_extend:GPR
- (unspec:SI
- [(match_operand:V16QI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], QImode);
-}
- [(set_attr "type" "load")])
-
-;; Extract a V4SI/V8HI/V16QI element from memory with a variable element number
-;; and convert it to unsigned float.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I:mode>_var_load_to_u<FL_CONV:mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONV:FL_CONV_REG>")
- (unsigned_float:FL_CONV
- (unspec:<VSX_EXTRACT_I:VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:QI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<VSX_EX>"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:FL_CONV (match_dup 4)))]
-{
- machine_mode base_mode = <VSX_EXTRACT_I:VEC_base>mode;
-
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- base_mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Extract a V4SI element from memory with a constant element number and
-;; convert it to signed float.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_s<mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONV_REG>")
- (float:FL_CONV
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q")
- (match_operand:QI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<FL_CONV_REG>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (sign_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:FL_CONV (match_dup 4)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Extract a V8HI element from memory with a constant element number and
-;; convert it to signed float. While we could do this via a LXSIHZX
-;; instruction followed by VEXTSB2D, it is better to do a LWA and MTVSRD
-;; instruction.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONV_REG>")
- (float:FL_CONV
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=&r"))
- (clobber (match_scratch:DI 5 "=<FL_CONV_REG>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (sign_extend:DI (match_dup 6)))
- (set (match_dup 5)
- (match_dup 4))
- (set (match_dup 0)
- (float:FL_CONV (match_dup 5)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
- if (GET_CODE (operands[5]) == SCRATCH)
- operands[5] = gen_reg_rtx (DImode);
-
- operands[6] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
-}
- [(set_attr "type" "load")
- (set_attr "length" "12")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index fa75c4c2a83..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e81ab4954ae..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 19b7d879065..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-22 5:50 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-22 5:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:87f139aae746c657c417d0fb34c425d335a8ead3
commit 87f139aae746c657c417d0fb34c425d335a8ead3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sat Apr 22 01:50:18 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d088936915d..60f47d748a6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4083,12 +4083,12 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4097,8 +4097,7 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 23:07 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 23:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:70ee48b31d4b97b697212187efafe8fa9ed71559
commit 70ee48b31d4b97b697212187efafe8fa9ed71559
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 19:07:56 2023 -0400
Revert patches
Diff:
---
gcc/ChangeLog.meissner | 58 +++++++++++++++++++++++++++++++++++++++++++++---
gcc/config/rs6000/vsx.md | 38 +++++++------------------------
2 files changed, 63 insertions(+), 33 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c157e73db69..61634f875b1 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,8 +1,60 @@
-==================== Branch work119, patch #52 was reverted ====================
+==================== Branch work119, patch #52 ====================
-==================== Branch work119, patch #51 was reverted ====================
+Improve vec_extract of V4SF with variable element number.
-==================== Branch work119, patch #50 was reverted ====================
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is variable combined with a conversion to DFmode.
+
+I also modified the insn for vec_extract of V4SFmode where the element number is
+variable to split before register allocation.
+
+2023-04-21 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
+ register allocation.
+ (vsx_extract_v4sf_var_load_to_df): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
+
+==================== Branch work119, patch #51 ====================
+
+Combine vec_extract of V4SF with DF convert.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is constant combined with a conversion to DFmode.
+
+In addition, I changed the vec_extract of V4SFmode where the element number is
+constant without conversion to do the split before register allocation. I also
+simplified the alternatives.
+
+2023-04-21 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
+ register allocation.
+ (vsx_extract_v4sf_to_df_load): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.
+
+==================== Branch work119, patch #50 ====================
+
+Allow vec_extract support functions to be called before reload.
+
+2023-04-21 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
+ register allocation.
+ (adjust_vec_address_pcrel): Likewise.
+ (rs6000_adjust_vec_address): Likewise.
==================== Branch work119, patch #49 was reverted ====================
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 17e56ab1ce4..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,45 +3549,23 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory convert to DFmode with constant element number. If
-;; the element number is 0, we don't need a temporary register.
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q")
- (parallel
- [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))
- (clobber (match_scratch:P 3 "=X,&b,X,&b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,fpload,load,load")
- (set_attr "length" "4,8,4,8")])
-
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=wa,wa")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:P 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 23:05 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 23:05 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7c4f1f61b3521c4050ff8c0d85fadbfd8adea8aa
commit 7c4f1f61b3521c4050ff8c0d85fadbfd8adea8aa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 19:05:19 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 +++++++-------------
gcc/config/rs6000/vsx.md | 59 ++++------------------
| 31 ------------
| 24 ---------
4 files changed, 26 insertions(+), 144 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1141e7b9fa7..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,45 +3549,23 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory convert to DFmode with constant element number. If
-;; the element number is 0, we don't need a temporary register.
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q")
- (parallel
- [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))
- (clobber (match_scratch:P 3 "=X,&b,X,&b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,fpload,load,load")
- (set_attr "length" "4,8,4,8")])
-
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=wa,wa")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:P 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3616,7 +3594,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 34ebc574339..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-
-void
-extract_float_0_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-void
-extract_float_1_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
-/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 65107ee0c74..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_float_0_gpr (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
-/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 20:19 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 20:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9eb96727093ab020f0930ce4258c1a5e719853a2
commit 9eb96727093ab020f0930ce4258c1a5e719853a2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 16:19:53 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 49 ++--------------------
| 36 ----------------
| 30 -------------
3 files changed, 3 insertions(+), 112 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4eba8c5ebef..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory convert to DFmode with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p7v,p9v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3607,7 +3585,7 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3622,28 +3600,7 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,load")
- (set_attr "length" "12")])
-
-;; V4SF extract from memory and convert to DFmode with variable element number.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
+ [(set_attr "type" "fpload,load")])
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index e110d308307..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS.
-
- Target LP64 and power8 vector are needed because the compiler only does the
- vec_extract optimizations on 64-bit machines that have direct move support.
- On earlier machines, vec_extract is done by storing the V4SF value into
- memory, and just doing the load from memory. */
-
-#include <altivec.h>
-
-float
-extract_float_0_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-float
-extract_float_3_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 3);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
-/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 7070bd24265..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float (SF) variables directly using a single LFSX or LXSSPX instruction.
- This includes loading a float and converting it to double. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-extern vector float global;
-
-float
-extract_float_var (size_t n)
-{
- return vec_extract (global, n); /* lfsx or lxsspx. */
-}
-
-double
-extract_float_to_double_var (size_t n)
-{
- return vec_extract (global, n); /* lfsx or lxsspx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */
-/* { dg-final { scan-assembler-not {\mvslo\M} } } */
-/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 19:50 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 19:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a456d1d3ed62f2659381ee32be723dbc73ae6f03
commit a456d1d3ed62f2659381ee32be723dbc73ae6f03
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 15:50:38 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 55 +++-------------------
| 31 ------------
| 28 -----------
3 files changed, 6 insertions(+), 108 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ea29df72ccc..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory convert to DFmode with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p7v,p9v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3607,43 +3585,22 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,load")
- (set_attr "length" "12")])
-
-;; V4SF extract from memory and convert to DFmode with variable element number.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:P 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
+ [(set_attr "type" "fpload,load")])
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index cc10fb41894..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-
-float
-extract_float_0_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-float
-extract_float_3_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 3);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
-/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index a621e45e1ad..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float (SF) variables directly using a single LFSX or LXSSPX instruction.
- This includes loading a float and converting it to double. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-float
-extract_float_var (vector float *p, size_t n)
-{
- return vec_extract (*p, n); /* lfsx or lxsspx. */
-}
-
-double
-extract_float_to_double_var (vector float *p, size_t n)
-{
- return vec_extract (*p, n); /* lfsx or lxsspx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */
-/* { dg-final { scan-assembler-not {\mvslo\M} } } */
-/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 19:36 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 19:36 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f5002e5626c8c6502fc6a377965a9424aa6160bc
commit f5002e5626c8c6502fc6a377965a9424aa6160bc
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 15:36:32 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 55 +++-------------------
| 29 ------------
| 27 -----------
3 files changed, 6 insertions(+), 105 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ea29df72ccc..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory convert to DFmode with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p7v,p9v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3607,43 +3585,22 @@
DONE;
})
-;; V4SF extract from memory with variable element number.
+;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,load")
- (set_attr "length" "12")])
-
-;; V4SF extract from memory and convert to DFmode with variable element number.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:P 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
+ [(set_attr "type" "fpload,load")])
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index eab7892ed80..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-
-float
-extract_float_0_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-float
-extract_float_3_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 3);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index af66fd20c21..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float (SF) variables directly using a single LFSX or LXSSPX instruction. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-float
-extract_float_var (vector float *p, size_t n)
-{
- return vec_extract (*p, n); /* lfsx or lxsspx. */
-}
-
-double
-extract_float_to_double_var (vector float *p, size_t n)
-{
- return vec_extract (*p, n); /* lfsx or lxsspx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */
-/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */
-/* { dg-final { scan-assembler-not {\mvslo\M} } } */
-/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 19:03 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 19:03 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:dc3ebbcf2cfdc4503916ba505712a3e1c93da64d
commit dc3ebbcf2cfdc4503916ba505712a3e1c93da64d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 15:03:16 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 24 +-----------------
| 29 ----------------------
2 files changed, 1 insertion(+), 52 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 84a41158d6b..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,6 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory and convert to DFmode with constant element number
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3558,7 +3557,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3568,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,Z,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p7v,p9v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index eab7892ed80..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float (SF) variables into a GPR without doing a LFS or STFS. */
-
-#include <altivec.h>
-
-float
-extract_float_0_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-float
-extract_float_3_gpr (vector float *p, float *q)
-{
- float x = vec_extract (*p, 3);
- __asm__ ("# %0" : "+r" (x)); /* lwz. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 18:10 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 18:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5c39e42356b13392ac03dc4a73dc4a7ea2e2e3cf
commit 5c39e42356b13392ac03dc4a73dc4a7ea2e2e3cf
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 14:10:45 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 ++--
gcc/config/rs6000/vsx.md | 290 ++-------------------
| 22 --
| 17 --
| 37 ---
| 38 ---
| 30 ---
| 27 --
| 37 ---
| 26 --
10 files changed, 33 insertions(+), 547 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 457513a4eaa..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,10 +207,6 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
-;; Iterator for vector extract/insert of small integer vectors that can be sign
-;; extended with the load.
-(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
-
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -227,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -251,10 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
- (unsigned_float "ZERO_EXTEND")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3581,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
- [(set (match_operand:DF 0 "register_operand" "=f,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3637,27 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; Combine V4SF extract from memory with a variable element number with
-;; conversion to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3986,124 +3930,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. If the element number is 0, we don't need to do a load immediate
-;; operation. Likewise for GPRs with offsettable loads, we can fold the offset
-;; into the address. For loading to vector registers, we are limited to X-FORM
-;; memory addresses. We need TARGET_POWERPC64 because we are creating a DI
-;; base register temporary.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a constant element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
- (any_extend:SI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")
- (set_attr "isa" "*,p8v")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
@@ -4127,122 +3970,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI/V4SI element from memory with a variable element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a variable element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
- (any_extend:SI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,16,20")
- (set_attr "isa" "*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with variable element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "20")
- (set_attr "isa" "*,p8v")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index fa75c4c2a83..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index ee6fb79993a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- QImode and fold the zero extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-unsigned long long
-extract_uns_var_v16qi (vector unsigned char *p, size_t n)
-{
- return vec_extract (*p, n); /* lbzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e81ab4954ae..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 91e85bf5a5b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-float
-extract_float_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-double
-extract_double_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index c4413fc158f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-
-/* There are 2 rldicl's to ensure the variable element number is between 0..3,
- but there is not a third one to do the zero extension after the unsigned
- int load. */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 415dee36d8a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-float
-extract_float_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 19b7d879065..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index efb5447f11b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_var (vector unsigned short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlhzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 15:37 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 15:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:57672ca1115864a05acfdd195a88b077d75d16ae
commit 57672ca1115864a05acfdd195a88b077d75d16ae
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 11:37:19 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 69 ----------------------
| 17 ------
| 26 --------
| 26 --------
4 files changed, 138 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3364a0791c2..d6b72a2fe33 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4145,75 +4145,6 @@
(set_attr "length" "12,16,12,16")
(set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI/V4SI element from memory with a variable element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a variable element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
- (any_extend:SI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,16,20")
- (set_attr "isa" "*,*,p9v,p9v")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index ee6fb79993a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- QImode and fold the zero extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-unsigned long long
-extract_uns_var_v16qi (vector unsigned char *p, size_t n)
-{
- return vec_extract (*p, n); /* lbzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index 437001a6177..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index efb5447f11b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_var (vector unsigned short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlhzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 15:36 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 15:36 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a1f248363949c5533957524329b5a600f06c1dac
commit a1f248363949c5533957524329b5a600f06c1dac
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 11:36:14 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 30 ----------------------
| 5 +---
| 27 -------------------
3 files changed, 1 insertion(+), 61 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 457513a4eaa..3364a0791c2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4214,36 +4214,6 @@
(set_attr "length" "12,16,16,20")
(set_attr "isa" "*,*,p9v,p9v")])
-;; Extract a V4SI element from memory with variable element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "20")
- (set_attr "isa" "*,p8v")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index 17db9bbe107..437001a6177 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -22,8 +22,5 @@ extract_uns_v4si_var (vector unsigned int *p, size_t n)
/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-
-/* There are 2 rldicl's to make the variable element number, but there is not a
- third one to do the zero extension. */
/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 415dee36d8a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-float
-extract_float_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 15:27 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 15:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8a5380ecb2383fdf55b67c30fcbb8225e4083b14
commit 8a5380ecb2383fdf55b67c30fcbb8225e4083b14
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 11:27:06 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 99 ----------------------
| 17 ----
| 26 ------
| 27 ------
| 26 ------
5 files changed, 195 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 457513a4eaa..d6b72a2fe33 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4145,105 +4145,6 @@
(set_attr "length" "12,16,12,16")
(set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI/V4SI element from memory with a variable element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,12,16")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a variable element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
- (any_extend:SI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "12,16,16,20")
- (set_attr "isa" "*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with variable element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "20")
- (set_attr "isa" "*,p8v")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index ee6fb79993a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- QImode and fold the zero extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-unsigned long long
-extract_uns_var_v16qi (vector unsigned char *p, size_t n)
-{
- return vec_extract (*p, n); /* lbzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f89eb617770..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 415dee36d8a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-float
-extract_float_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index efb5447f11b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_var (vector unsigned short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlhzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 15:09 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 15:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:08586c25674ae828f8132efb6a5e7ebb085dc9e9
commit 08586c25674ae828f8132efb6a5e7ebb085dc9e9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 11:09:25 2023 -0400
Revert patches
Diff:
---
| 2 +-
| 3 ++-
| 3 ++-
| 2 +-
| 3 ++-
| 2 +-
| 3 ++-
| 2 +-
8 files changed, 12 insertions(+), 8 deletions(-)
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
index 42599c214e4..29a8aa84db2 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
@@ -11,7 +11,7 @@
/* one extsb (extend sign-bit) instruction generated for each test against
unsigned types */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 } } */
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* -m32 target uses rlwinm in place of rldicl. */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index cbf6cffbeba..3cae644b90b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,7 +13,8 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index c9abb6c1f35..59a4979457d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,7 +12,8 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index 68eeeede4b3..4b1d75ee26d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
#include <altivec.h>
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 418762e3948..3729a1646e9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,7 +10,8 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
/* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
index d1e3b62373f..75eaf25943b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
@@ -30,7 +30,7 @@
/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
index 46e943faa6a..a495d9f3928 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
@@ -10,7 +10,8 @@
// P7 (be) constants: li, addi, stxvw4x, lha/lhz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */
/* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
index 00685aca136..0ddecb4e4b5 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
@@ -32,7 +32,7 @@
/* add and rlwinm instructions only on the variable tests. */
/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 3:57 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 3:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:39cca051d2019c5e2482c403fad2200e00e86560
commit 39cca051d2019c5e2482c403fad2200e00e86560
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 23:57:34 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c5c2920fcd1..bb06abceb00 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3637,24 +3637,6 @@
}
[(set_attr "type" "fpload,load")])
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 3:45 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 3:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f28af2061dadc51d25e9eab33226ce214226f194
commit f28af2061dadc51d25e9eab33226ce214226f194
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 23:45:10 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 204 +--------------------
| 22 ---
| 17 --
| 37 ----
| 38 ----
| 26 ---
| 37 ----
| 26 ---
8 files changed, 6 insertions(+), 401 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 778d067e533..63f31980806 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,10 +207,6 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
-;; Iterator for vector extract/insert of small integer vectors that can be sign
-;; extended with the load.
-(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
-
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -251,10 +247,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
- (unsigned_float "ZERO_EXTEND")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3637,24 +3629,6 @@
}
[(set_attr "type" "fpload,load")])
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -4007,101 +3981,6 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a constant element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
- (any_extend:SI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")
- (set_attr "isa" "*,p8v")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
@@ -4124,92 +4003,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI/V4SI element from memory with a variable element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_var_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,8,12")
- (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a variable element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,v,v")
- (any_extend:SI
- (unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
- (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,8,12")
- (set_attr "isa" "*,*,p9v,p9v")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index a392e4322bb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index ee6fb79993a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- QImode and fold the zero extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-unsigned long long
-extract_uns_var_v16qi (vector unsigned char *p, size_t n)
-{
- return vec_extract (*p, n); /* lbzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e81ab4954ae..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 91e85bf5a5b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-float
-extract_float_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-double
-extract_double_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f89eb617770..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 3c834a77948..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
deleted file mode 100644
index efb5447f11b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_var (vector unsigned short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlhax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlhzx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-21 3:09 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-21 3:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ce7a90c0c0b37c320993c5ccab8f6de271a9be09
commit ce7a90c0c0b37c320993c5ccab8f6de271a9be09
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 23:09:14 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d4d00a3d637..c5c2920fcd1 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4124,23 +4124,21 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-20 23:41 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-20 23:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:145825e9ca83c97f515bb612db37523072e72587
commit 145825e9ca83c97f515bb612db37523072e72587
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 19:41:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 153 ++-------------------
| 22 ---
| 37 -----
| 38 -----
| 37 -----
5 files changed, 10 insertions(+), 277 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c55ad502962..ebc986fc6ac 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,10 +207,6 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
-;; Iterator for vector extract/insert of small integer vectors that can be sign
-;; extended with the load.
-(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
-
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -227,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p8v")
- (V4SI "p7v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -251,10 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
- (unsigned_float "ZERO_EXTEND")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3637,24 +3623,6 @@
}
[(set_attr "type" "fpload,load")])
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3983,124 +3951,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
-;; number. If the element number is 0, we don't need to do a load immediate
-;; operation. Likewise for GPRs with offsettable loads, we can fold the offset
-;; into the address. For loading to vector registers, we are limited to X-FORM
-;; memory addresses. We need TARGET_POWERPC64 because we are creating a DI
-;; base register temporary.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a constant element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
- (any_extend:SI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")
- (set_attr "isa" "*,p8v")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index a392e4322bb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index e81ab4954ae..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 91e85bf5a5b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-float
-extract_float_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-double
-extract_double_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index 3c834a77948..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 22:11 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 22:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b0e1fd58c357da10aeba32663ceaf3d9a23c345b
commit b0e1fd58c357da10aeba32663ceaf3d9a23c345b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 18:11:19 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 103 ---------------------
| 22 -----
| 37 --------
| 38 --------
| 37 --------
5 files changed, 237 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4ed577a9e6c..cac0bda2b2c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -207,10 +207,6 @@
(define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI])
(define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI])
-;; Iterator for vector extract/insert of small integer vectors that can be sign
-;; extended with the load.
-(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI])
-
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
@@ -251,10 +247,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
- (unsigned_float "ZERO_EXTEND")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3989,101 +3981,6 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and zero extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number
-;; and sign extend it to DImode.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
- (sign_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
-
-;; Extract a V8HI element from memory with a constant element number
-;; and zero or sign extend it to SImode.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_<su>si"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v")
- (any_extend:SI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_extend:SI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,12,8,12")
- (set_attr "isa" "*,*,*,p9v,p9v")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode or DFmode using either signed or unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")
- (set_attr "isa" "*,p8v")])
-
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index f3cfb933789..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target vsx } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 79cfba6f7f1..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target vsx } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 91e85bf5a5b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-float
-extract_float_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-double
-extract_double_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index e03ab6893a1..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target vsx } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lwz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lwz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 21:47 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 21:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:316f0a0520bc3013b26af83d6968b5ecf8a8db62
commit 316f0a0520bc3013b26af83d6968b5ecf8a8db62
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 17:47:47 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 40 ----------------------
| 38 --------------------
| 26 --------------
3 files changed, 104 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9c486a0cc79..9be15b02af2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -251,17 +251,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Constraint to use for floating point types that a direct conversion
-;; from 64-bit integer to floating point.
-(define_mode_attr FL_CONSTRAINT [(SF "wa")
- (DF "wa")
- (KF "v")
- (TF "v")])
-
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND")
- (unsigned_float "ZERO_EXTEND")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -4062,35 +4051,6 @@
(set_attr "length" "4,4,12,8,12")
(set_attr "isa" "*,*,*,p9v,p9v")])
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
-;; unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>,<FL_CONSTRAINT>")
- (any_float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
- (clobber (match_scratch:DI 3 "=&b,&b"))
- (clobber (match_scratch:DI 4 "=f,v"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (any_float:FL_CONV (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")
- (set_attr "isa" "*,p8v")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index 86077a060a1..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, and double by loading the value
- directly into a vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-double
-extract_double_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index 9e46caa8277..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target float128_hw } */
-/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value _Float128 by loading the value directly into a
- vector register, and not loading up the GPRs first. */
-
-#include <altivec.h>
-
-_Float128
-extract_ieee_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lxsiwzx. */
-}
-
-_Float128
-extract_ieee_uns_v4si_3 (vector unsigned int *p)
-{
- return vec_extract (*p, 3); /* lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 19:28 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 19:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3058f66c544ee6cf4da56620644d603fe02e3c42
commit 3058f66c544ee6cf4da56620644d603fe02e3c42
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 15:28:22 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 ++++++++++++++-------------------------------
gcc/config/rs6000/vsx.md | 50 ++++++++--------------------------------
2 files changed, 26 insertions(+), 80 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c3b870640ed..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3573,27 +3567,6 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
-;; V4SF extract from memory and convert to DFmode with constant element number.
-(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
- [(set (match_operand:DF 0 "register_operand" "=f,v,v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "m,m,m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
- (clobber (match_scratch:P 3 "=&b,&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")
- (set_attr "isa" "*,p8v,p9v")])
-
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
@@ -3957,28 +3930,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
-;; If the element number is 0, we don't need to do a load immediate operation.
-;; Likewise for GPRs with offsettable loads, we can fold the offset into the
-;; address. For vector registers, we are limited to X-FORM memory addresses.
-;; PowerPC64 is needed because we need a DI temporary base register.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 19:21 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 19:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5da57dff3157bed9513718a9a2fe9e41d3764a49
commit 5da57dff3157bed9513718a9a2fe9e41d3764a49
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 15:21:31 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.cc | 56 ++++++++++++++-------------------------------
gcc/config/rs6000/vsx.md | 29 ++++++++---------------
2 files changed, 26 insertions(+), 59 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 65295dbaf81..3be5860dd9b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (CONST_INT_P (element))
return GEN_INT (INTVAL (element) * scalar_size);
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
- /* After register allocation, all insns should use the 'Q' constraint
- (address is a single register) if the element number is not a
- constant. */
- gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem));
+ /* All insns should use the 'Q' constraint (address is a single register) if
+ the element number is not a constant. */
+ gcc_assert (satisfies_constraint_Q (mem));
/* Mask the element to make sure the element number is between 0 and the
maximum number of elements - 1 so that we don't generate an address
@@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
if (shift > 0)
{
rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
- if (can_create_pseudo_p ())
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, shift_op));
}
@@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
temporary (BASE_TMP) to fixup the address. Return the new memory address
that is valid for reads or writes to a given register (SCALAR_REG).
- The temporary BASE_TMP might be set multiple times with this code if this is
- called after register allocation. */
+ This function is expected to be called after reload is completed when we are
+ splitting insns. The temporary BASE_TMP might be set multiple times with
+ this code. */
rtx
rs6000_adjust_vec_address (rtx scalar_reg,
@@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg,
rtx addr = XEXP (mem, 0);
rtx new_addr;
- if (GET_CODE (base_tmp) != SCRATCH)
- {
- gcc_assert (!reg_mentioned_p (base_tmp, addr));
- gcc_assert (!reg_mentioned_p (base_tmp, element));
- }
+ gcc_assert (!reg_mentioned_p (base_tmp, addr));
+ gcc_assert (!reg_mentioned_p (base_tmp, element));
/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
@@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg,
offset, it has the benefit that if D-FORM instructions are
allowed, the offset is part of the memory access to the vector
element. */
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
@@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg,
else
{
- if (GET_CODE (base_tmp) == SCRATCH)
- base_tmp = gen_reg_rtx (Pmode);
-
emit_move_insn (base_tmp, addr);
new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
}
- /* If register allocation has been done and the address isn't valid, move
- the address into the temporary base register. Some reasons it could not
- be valid include:
+ /* If the address isn't valid, move the address into the temporary base
+ register. Some reasons it could not be valid include:
The address offset overflowed the 16 or 34 bit offset size;
We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
We need to use a DQ-FORM load, and the bottom 4 bits are non-zero;
Only X_FORM loads can be done, and the address is D_FORM. */
- if (!can_create_pseudo_p ())
- {
- enum insn_form iform
- = address_to_insn_form (new_addr, scalar_mode,
- reg_to_non_prefixed (scalar_reg, scalar_mode));
+ enum insn_form iform
+ = address_to_insn_form (new_addr, scalar_mode,
+ reg_to_non_prefixed (scalar_reg, scalar_mode));
- if (iform == INSN_FORM_BAD)
- {
- emit_move_insn (base_tmp, new_addr);
- new_addr = base_tmp;
- }
+ if (iform == INSN_FORM_BAD)
+ {
+ emit_move_insn (base_tmp, new_addr);
+ new_addr = base_tmp;
}
return change_address (mem, scalar_mode, new_addr);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c3b870640ed..0e681844243 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3957,28 +3951,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
-;; If the element number is 0, we don't need to do a load immediate operation.
-;; Likewise for GPRs with offsettable loads, we can fold the offset into the
-;; address. For vector registers, we are limited to X-FORM memory addresses.
-;; PowerPC64 is needed because we need a DI temporary base register.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 19:14 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 19:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5e229034bf8bb04c66b694f108a8eeaa05a72160
commit 5e229034bf8bb04c66b694f108a8eeaa05a72160
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 15:14:09 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 28 +++++++++-------------------
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 533216321c4..0e681844243 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p8v")
- (V4SI "p7v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3957,27 +3951,23 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
-;; If the element number is 0, we don't need to do a load immediate operation.
-;; Likewise for GPRs with offsettable loads, we can fold the offset into the
-;; address. For vector registers, we are limited to X-FORM memory addresses.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& 1"
+ "&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,load,fpload,fpload")
- (set_attr "length" "4,4,8,4,8")
- (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 16:36 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 16:36 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:596fd7c7522ba0942e447084e8460cb7843d956a
commit 596fd7c7522ba0942e447084e8460cb7843d956a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 12:36:17 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..d615474df01 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,7 +3549,7 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-(define_insn_and_split "*vsx_extract_v4sf_load"
+(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-19 16:22 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-19 16:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f26f6724ef0f75cfebc84434f4c1fbfbd0ff2154
commit f26f6724ef0f75cfebc84434f4c1fbfbd0ff2154
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 19 12:22:53 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 139 ++-------------------
| 24 ----
| 44 -------
| 37 ------
| 40 ------
| 37 ------
6 files changed, 7 insertions(+), 314 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e3466f3aa74..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -241,17 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Constraint to use for floating point types that a direct conversion
-;; from 64-bit integer to floating point.
-(define_mode_attr FL_CONSTRAINT [(SF "wa")
- (DF "wa")
- (KF "v")
- (TF "v")])
-
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO [(float "SIGN")
- (unsigned_float "ZERO")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3941,126 +3930,13 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V4SI element from memory with constant element number.
-(define_insn_and_split "*vsx_extract_v4si_load"
- [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 4))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to DImode with zero or sign extension.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number and
-;; convert it to DImode with zero extension.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,v,v")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "YZ,m,Z,Q")
- (parallel
- [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
-
-;; Extract a V8HI element from memory with constant element number and
-;; convert it to DImode with sign extension.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "YZ,m")
- (parallel
- [(match_operand:QI 2 "const_0_to_7_operand" "0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
-;; unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>")
- (any_float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<FL_CONSTRAINT>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (any_float:FL_CONV (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO>_EXTEND (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4069,9 +3945,8 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
deleted file mode 100644
index e57dd0e8bb9..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-unsigned long long
-extract_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lbz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lbz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlbz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsb\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 209ca926b97..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode directly into vector registers. */
-
-#include <altivec.h>
-
-void
-extract_sign_v4si_0 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_sign_v4si_1 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_v4si_1 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlfiw[az]x\M|\mlxsiw[az]x\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index bf135789bf8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index edaa2ccc9bf..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, double, and _Float128 by loading the
- value directly into a vector register, and not loading up the GPRs
- first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-_Float128
-extract_ieee_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index a2c482f556e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lha, no extsh. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lha, no extsh. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lhz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lhz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-18 22:13 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-18 22:13 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6c962c52b0efac580f75aadbc02717ee5859f3e8
commit 6c962c52b0efac580f75aadbc02717ee5859f3e8
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 18 18:13:56 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 45 ----------------------
| 37 ------------------
2 files changed, 82 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e3466f3aa74..49da544bf28 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3980,51 +3980,6 @@
[(set_attr "type" "load,load,fpload,fpload")
(set_attr "length" "4,8,4,8")])
-;; Extract a V8HI/V16QI element from memory with constant element number and
-;; convert it to DImode with zero extension.
-(define_insn_and_split "*vsx_extract_<mode>_load_to_udi"
- [(set (match_operand:DI 0 "register_operand" "=r,r,v,v")
- (zero_extend:DI
- (vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "YZ,m,Z,Q")
- (parallel
- [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
-
-;; Extract a V8HI element from memory with constant element number and
-;; convert it to DImode with sign extension.
-(define_insn_and_split "*vsx_extract_v8hi_load_to_sdi"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI
- (vec_select:HI
- (match_operand:V8HI 1 "memory_operand" "YZ,m")
- (parallel
- [(match_operand:QI 2 "const_0_to_7_operand" "0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], HImode);
-}
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
-
;; Extract a V4SI element from memory with constant element number and convert
;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
;; unsigned conversion.
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
deleted file mode 100644
index a2c482f556e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v8hi_0 (vector short *p)
-{
- return vec_extract (*p, 0); /* lha, no extsh. */
-}
-
-long long
-extract_sign_v8hi_1 (vector short *p)
-{
- return vec_extract (*p, 1); /* lha, no extsh. */
-}
-
-unsigned long long
-extract_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lhz, no rlwinm. */
-}
-
-unsigned long long
-extract_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lhz, no rlwinm. */
-}
-
-/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
-/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-18 5:37 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-18 5:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7af88e27233ed36c98bf6f0e706e7769195646b6
commit 7af88e27233ed36c98bf6f0e706e7769195646b6
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 18 01:37:20 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 94 ++--------------------
| 44 ----------
| 37 ---------
| 40 ---------
4 files changed, 7 insertions(+), 208 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 49da544bf28..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -241,17 +241,6 @@
(TF "TARGET_FLOAT128_HW
&& FLOAT128_IEEE_P (TFmode)")])
-;; Constraint to use for floating point types that a direct conversion
-;; from 64-bit integer to floating point.
-(define_mode_attr FL_CONSTRAINT [(SF "wa")
- (DF "wa")
- (KF "v")
- (TF "v")])
-
-;; Whether to use SIGN or ZERO when depending on the floating point conversion.
-(define_code_attr SIGN_ZERO [(float "SIGN")
- (unsigned_float "ZERO")])
-
;; Iterator for the 2 short vector types to do a splat from an integer
(define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
@@ -3941,81 +3930,13 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V4SI element from memory with constant element number.
-(define_insn_and_split "*vsx_extract_v4si_load"
- [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 4))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to DImode with zero or sign extension.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to SFmode, DFmode, KFmode, or possibly TFmode using either signed or
-;; unsigned conversion.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:FL_CONV 0 "register_operand" "=<FL_CONSTRAINT>")
- (any_float:FL_CONV
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=<FL_CONSTRAINT>"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (match_dup 5))
- (set (match_dup 0)
- (any_float:FL_CONV (match_dup 4)))]
-{
- if (GET_CODE (operands[4]) == SCRATCH)
- operands[4] = gen_reg_rtx (DImode);
-
- rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
- operands[3], SImode);
- operands[5] = gen_rtx_<SIGN_ZERO>_EXTEND (DImode, new_mem);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "12")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -4024,9 +3945,8 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index 0be1d471ac5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode directly into vector registers. */
-
-#include <altivec.h>
-
-void
-extract_sign_v4si_0 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_sign_v4si_1 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_v4si_1 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\ml(f|xs)iw[az]x\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index bf135789bf8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index 5dfd94832a4..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert the value to float, double, and _Float128 by loading the
- value directly into a vector register, and not loading up the GPRs
- first. */
-
-#include <altivec.h>
-
-float
-extract_float_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwax or lxsiwax. */
-}
-
-double
-extract_double_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */
-}
-
-_Float128
-extract_ieee_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx or lxsiwzx. */
-}
-
-/* { dg-final { scan-assembler-times {\ml(f|xs)iwax\M} 2 } } */
-/* { dg-final { scan-assembler-times {\ml(f|xs)iwzx\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 55+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Revert patches
@ 2023-04-17 22:28 Michael Meissner
0 siblings, 0 replies; 55+ messages in thread
From: Michael Meissner @ 2023-04-17 22:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:42e15b30179325a78a4786e5a22046e7c2b9a547
commit 42e15b30179325a78a4786e5a22046e7c2b9a547
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 17 18:28:54 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 54 +++-------------------
| 43 -----------------
| 37 ---------------
3 files changed, 7 insertions(+), 127 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1c926158eb4..417aff5e24b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3930,52 +3930,13 @@
}
[(set_attr "type" "mfvsr")])
-;; Extract a V4SI element from memory with constant element number.
-(define_insn_and_split "*vsx_extract_v4si_load"
- [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 4))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V4SI element from memory with constant element number and convert
-;; it to DImode with zero or sign extension.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
- [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa")
- (any_extend:DI
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "YZ,m,Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SImode);
-}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")])
-
-;; Extract a V8HI/V16QI element from memory with constant element number.
+;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
- [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
+ [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
(vec_select:<VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
- (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
- (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+ (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
@@ -3984,9 +3945,8 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load,load,fpload,fpload")
- (set_attr "length" "4,8,4,8")
- (set_attr "isa" "*,*,p9v,p9v")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
deleted file mode 100644
index db7ea3300e7..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode directly into vector registers. */
-
-#include <altivec.h>
-
-void
-extract_sign_v4si_0 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_sign_v4si_1 (vector int *p, int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 0);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-void
-extract_v4si_1 (vector unsigned int *p, unsigned int *q)
-{
- int x = vec_extract (*p, 1);
- __asm__ (" # %x0" : "+wa" (x)); /* lfiwzx or lfiwax. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlfiw[az]x\M} 4 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
deleted file mode 100644
index e5452818b0f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-/* { dg-require-effective-target p8vector_hw } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and fold the sign/extension into the load. */
-
-#include <altivec.h>
-
-long long
-extract_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lwa, no extsw. */
-}
-
-long long
-extract_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lwa, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-unsigned long long
-extract_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lwz, no rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
-/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
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