[PATCH 00/14] Support RISC-V Vector Cryptography Extensions

[PATCH 00/14] Support RISC-V Vector Cryptography Extensions

[Nathan Huckleberry]

This patchset adds support for the RISC-V Vector Cryptography extensions.  These
are: Zvbb, Zvbc, Zvkg, Zkvned, Zvknh[a,b], Zvkn, Zvkng, Zvknc, Zvksed, Zvksh,
Zvks, Zvksg, Zvksc.

This is based off the v20230620 version of the Vector Cryptography
specification.  The specification is frozen.

https://github.com/riscv/riscv-crypto/releases/tag/v20230620

Christoph Müllner (8):
  Add support for the Zvbb ISA extension.
  Add support for the Zvkg ISA extension.
  Add support for the Zvkned ISA extension.
  Add support for the Zvknh[a,b] ISA extensions.
  Add support for the Zvksed ISA extension.
  Adds support for the Zvksh ISA extension.
  Add support for the Zvkn ISA extension.
  Add support for the Zvks ISA extension.

Nathan Huckleberry (6):
  Add support for the Zvbc ISA extension.
  Allow nested implications for extensions.
  Add support for the Zvkng ISA extension.
  Add support for the Zvksg ISA extension.
  Add support for the Zvknc ISA extension.
  Add support for the Zvksc ISA extension.

 bfd/elfxx-riscv.c                       |  80 +++++++++++++-
 gas/config/tc-riscv.c                   |  13 +++
 gas/testsuite/gas/riscv/zvbb.d          |  43 ++++++++
 gas/testsuite/gas/riscv/zvbb.s          |  34 ++++++
 gas/testsuite/gas/riscv/zvbc.d          |  16 +++
 gas/testsuite/gas/riscv/zvbc.s          |   8 ++
 gas/testsuite/gas/riscv/zvkg.d          |  10 ++
 gas/testsuite/gas/riscv/zvkg.s          |   2 +
 gas/testsuite/gas/riscv/zvkn.d          |  45 ++++++++
 gas/testsuite/gas/riscv/zvkn.s          |  36 +++++++
 gas/testsuite/gas/riscv/zvknc.d         |  18 ++++
 gas/testsuite/gas/riscv/zvknc.s         |  10 ++
 gas/testsuite/gas/riscv/zvkned.d        |  21 ++++
 gas/testsuite/gas/riscv/zvkned.s        |  13 +++
 gas/testsuite/gas/riscv/zvkng.d         |  12 +++
 gas/testsuite/gas/riscv/zvkng.s         |   4 +
 gas/testsuite/gas/riscv/zvknha.d        |  12 +++
 gas/testsuite/gas/riscv/zvknha_zvknhb.s |   3 +
 gas/testsuite/gas/riscv/zvknhb.d        |  12 +++
 gas/testsuite/gas/riscv/zvks.d          |  45 ++++++++
 gas/testsuite/gas/riscv/zvks.s          |  36 +++++++
 gas/testsuite/gas/riscv/zvksc.d         |  18 ++++
 gas/testsuite/gas/riscv/zvksc.s         |  10 ++
 gas/testsuite/gas/riscv/zvksed.d        |  12 +++
 gas/testsuite/gas/riscv/zvksed.s        |   4 +
 gas/testsuite/gas/riscv/zvksg.d         |  12 +++
 gas/testsuite/gas/riscv/zvksg.s         |   4 +
 gas/testsuite/gas/riscv/zvksh.d         |  11 ++
 gas/testsuite/gas/riscv/zvksh.s         |   3 +
 include/opcode/riscv-opc.h              | 137 ++++++++++++++++++++++++
 include/opcode/riscv.h                  |  13 +++
 opcodes/riscv-dis.c                     |   4 +
 opcodes/riscv-opc.c                     |  55 ++++++++++
 33 files changed, 754 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zvbb.d
 create mode 100644 gas/testsuite/gas/riscv/zvbb.s
 create mode 100644 gas/testsuite/gas/riscv/zvbc.d
 create mode 100644 gas/testsuite/gas/riscv/zvbc.s
 create mode 100644 gas/testsuite/gas/riscv/zvkg.d
 create mode 100644 gas/testsuite/gas/riscv/zvkg.s
 create mode 100644 gas/testsuite/gas/riscv/zvkn.d
 create mode 100644 gas/testsuite/gas/riscv/zvkn.s
 create mode 100644 gas/testsuite/gas/riscv/zvknc.d
 create mode 100644 gas/testsuite/gas/riscv/zvknc.s
 create mode 100644 gas/testsuite/gas/riscv/zvkned.d
 create mode 100644 gas/testsuite/gas/riscv/zvkned.s
 create mode 100644 gas/testsuite/gas/riscv/zvkng.d
 create mode 100644 gas/testsuite/gas/riscv/zvkng.s
 create mode 100644 gas/testsuite/gas/riscv/zvknha.d
 create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
 create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
 create mode 100644 gas/testsuite/gas/riscv/zvks.d
 create mode 100644 gas/testsuite/gas/riscv/zvks.s
 create mode 100644 gas/testsuite/gas/riscv/zvksc.d
 create mode 100644 gas/testsuite/gas/riscv/zvksc.s
 create mode 100644 gas/testsuite/gas/riscv/zvksed.d
 create mode 100644 gas/testsuite/gas/riscv/zvksed.s
 create mode 100644 gas/testsuite/gas/riscv/zvksg.d
 create mode 100644 gas/testsuite/gas/riscv/zvksg.s
 create mode 100644 gas/testsuite/gas/riscv/zvksh.d
 create mode 100644 gas/testsuite/gas/riscv/zvksh.s

-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 01/14] Add support for the Zvbb ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvbb is part of the vector crypto extensions.

This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c              |  5 ++++
 gas/config/tc-riscv.c          | 13 +++++++++
 gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
 include/opcode/riscv-opc.h     | 50 ++++++++++++++++++++++++++++++++++
 include/opcode/riscv.h         |  5 ++++
 opcodes/riscv-dis.c            |  4 +++
 opcodes/riscv-opc.c            | 18 ++++++++++++
 8 files changed, 172 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvbb.d
 create mode 100644 gas/testsuite/gas/riscv/zvbb.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 7f453246449..8342b4fb3cc 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1259,6 +1259,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64x",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2411,6 +2412,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve64d")
 	      || riscv_subset_supports (rps, "zve64f")
 	      || riscv_subset_supports (rps, "zve32f"));
+    case INSN_CLASS_ZVBB:
+      return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2571,6 +2574,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64x' or `zve32x");
     case INSN_CLASS_ZVEF:
       return _("v' or `zve64d' or `zve64f' or `zve32f");
+    case INSN_CLASS_ZVBB:
+      return _("zvbb");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index fceb53e54a6..3adf5966175 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1326,6 +1326,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    case 'i':
 	    case 'j':
 	    case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
+	    case 'l': used_bits |= ENCODE_RVV_VI_UIMM6 (-1U); break;
 	    case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
 	    case 'M': break; /* Macro operand, must be a mask register.  */
 	    case 'T': break; /* Macro operand, must be a vector register.  */
@@ -3042,6 +3043,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  asarg = expr_parse_end;
 		  continue;
 
+		case 'l': /* 6-bit vector arith unsigned immediate */
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  if (imm_expr->X_add_number < 0
+		      || imm_expr->X_add_number >= 64)
+		    as_bad (_("bad value for vector immediate field, "
+			      "value must be 0...63"));
+		  ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number);
+		  imm_expr->X_op = O_absent;
+		  asarg = expr_parse_end;
+		  continue;
+
 		case 'm': /* optional vector mask */
 		  if (*asarg == '\0')
 		    {
diff --git a/gas/testsuite/gas/riscv/zvbb.d b/gas/testsuite/gas/riscv/zvbb.d
new file mode 100644
index 00000000000..c6c9df5c681
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbb.d
@@ -0,0 +1,43 @@
+#as: -march=rv64gc_zvbb
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+06860257[ 	]+vandn.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+04860257[ 	]+vandn.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0685c257[ 	]+vandn.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0485c257[ 	]+vandn.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a852257[ 	]+vbrev.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48852257[ 	]+vbrev.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a842257[ 	]+vbrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48842257[ 	]+vbrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a862257[ 	]+vclz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48862257[ 	]+vclz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a86a257[ 	]+vctz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4886a257[ 	]+vctz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a872257[ 	]+vcpop.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48872257[ 	]+vcpop.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+56860257[ 	]+vrol.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+54860257[ 	]+vrol.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5685c257[ 	]+vrol.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5485c257[ 	]+vrol.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52860257[ 	]+vror.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+50860257[ 	]+vror.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5285c257[ 	]+vror.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5085c257[ 	]+vror.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52803257[ 	]+vror.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+548fb257[ 	]+vror.vi[ 	]+v4,v8,63,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6860257[ 	]+vwsll.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+d4860257[ 	]+vwsll.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d685c257[ 	]+vwsll.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+d485c257[ 	]+vwsll.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6803257[ 	]+vwsll.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+d48fb257[ 	]+vwsll.vi[ 	]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvbb.s b/gas/testsuite/gas/riscv/zvbb.s
new file mode 100644
index 00000000000..7a666ff959b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbb.s
@@ -0,0 +1,34 @@
+	vandn.vv v4, v8, v12
+	vandn.vv v4, v8, v12, v0.t
+	vandn.vx v4, v8, a1
+	vandn.vx v4, v8, a1, v0.t
+	vbrev.v v4, v8
+	vbrev.v v4, v8, v0.t
+	vbrev8.v v4, v8
+	vbrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vclz.v v4, v8
+	vclz.v v4, v8, v0.t
+	vctz.v v4, v8
+	vctz.v v4, v8, v0.t
+	vcpop.v v4, v8
+	vcpop.v v4, v8, v0.t
+	vrol.vv v4, v8, v12
+	vrol.vv v4, v8, v12, v0.t
+	vrol.vx v4, v8, a1
+	vrol.vx v4, v8, a1, v0.t
+	vror.vv v4, v8, v12
+	vror.vv v4, v8, v12, v0.t
+	vror.vx v4, v8, a1
+	vror.vx v4, v8, a1, v0.t
+	vror.vi v4, v8, 0
+	vror.vi v4, v8, 63, v0.t
+	vwsll.vv v4, v8, v12
+	vwsll.vv v4, v8, v12, v0.t
+	vwsll.vx v4, v8, a1
+	vwsll.vx v4, v8, a1, v0.t
+	vwsll.vi v4, v8, 0
+	vwsll.vi v4, v8, 31, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 91e56c03191..cde8c341b6b 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2055,6 +2055,39 @@
 #define MASK_VDOTUVV  0xfc00707f
 #define MATCH_VFDOTVV  0xe4001057
 #define MASK_VFDOTVV  0xfc00707f
+/* Zvbb instructions.  */
+#define MATCH_VANDN_VV 0x4000057
+#define MASK_VANDN_VV 0xfc00707f
+#define MATCH_VANDN_VX 0x4004057
+#define MASK_VANDN_VX 0xfc00707f
+#define MATCH_VBREV8_V 0x48042057
+#define MASK_VBREV8_V 0xfc0ff07f
+#define MATCH_VBREV_V 0x48052057
+#define MASK_VBREV_V 0xfc0ff07f
+#define MATCH_VCLZ_V 0x48062057
+#define MASK_VCLZ_V 0xfc0ff07f
+#define MATCH_VCPOP_V 0x48072057
+#define MASK_VCPOP_V 0xfc0ff07f
+#define MATCH_VCTZ_V 0x4806a057
+#define MASK_VCTZ_V 0xfc0ff07f
+#define MATCH_VREV8_V 0x4804a057
+#define MASK_VREV8_V 0xfc0ff07f
+#define MATCH_VROL_VV 0x54000057
+#define MASK_VROL_VV 0xfc00707f
+#define MATCH_VROL_VX 0x54004057
+#define MASK_VROL_VX 0xfc00707f
+#define MATCH_VROR_VI 0x50003057
+#define MASK_VROR_VI 0xf800707f
+#define MATCH_VROR_VV 0x50000057
+#define MASK_VROR_VV 0xfc00707f
+#define MATCH_VROR_VX 0x50004057
+#define MASK_VROR_VX 0xfc00707f
+#define MATCH_VWSLL_VI 0xd4003057
+#define MASK_VWSLL_VI 0xfc00707f
+#define MATCH_VWSLL_VV 0xd4000057
+#define MASK_VWSLL_VV 0xfc00707f
+#define MATCH_VWSLL_VX 0xd4004057
+#define MASK_VWSLL_VX 0xfc00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3123,6 +3156,23 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zvbb instructions.  */
+DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
+DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
+DECLARE_INSN(vbrev8_v, MATCH_VBREV8_V, MASK_VBREV8_V)
+DECLARE_INSN(vbrev_v, MATCH_VBREV_V, MASK_VBREV_V)
+DECLARE_INSN(vclz_v, MATCH_VCLZ_V, MASK_VCLZ_V)
+DECLARE_INSN(vcpop_v, MATCH_VCPOP_V, MASK_VCPOP_V)
+DECLARE_INSN(vctz_v, MATCH_VCTZ_V, MASK_VCTZ_V)
+DECLARE_INSN(vrev8_v, MATCH_VREV8_V, MASK_VREV8_V)
+DECLARE_INSN(vrol_vv, MATCH_VROL_VV, MASK_VROL_VV)
+DECLARE_INSN(vrol_vx, MATCH_VROL_VX, MASK_VROL_VX)
+DECLARE_INSN(vror_vi, MATCH_VROR_VI, MASK_VROR_VI)
+DECLARE_INSN(vror_vv, MATCH_VROR_VV, MASK_VROR_VV)
+DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
+DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
+DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
+DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index e86a1bd0824..296fbe2640c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
 #define EXTRACT_RVV_VI_UIMM(x) \
   (RV_X(x, 15, 5))
+#define EXTRACT_RVV_VI_UIMM6(x) \
+  (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
 #define EXTRACT_RVV_OFFSET(x) \
   (RV_X(x, 29, 3))
 #define EXTRACT_RVV_VB_IMM(x) \
@@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 10) << 20)
 #define ENCODE_RVV_VC_IMM(x) \
   (RV_X(x, 0, 11) << 20)
+#define ENCODE_RVV_VI_UIMM6(x) \
+  (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -405,6 +409,7 @@ enum riscv_insn_class
   INSN_CLASS_ZKND_OR_ZKNE,
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
+  INSN_CLASS_ZVBB,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 108baeb32ef..92d3197c639 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -400,6 +400,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      print (info->stream, dis_style_immediate, "%d",
 		     (int)EXTRACT_RVV_OFFSET (l));
 	      break;
+	    case 'l':
+	      print (info->stream, dis_style_immediate, "%d",
+		     (int)EXTRACT_RVV_VI_UIMM6 (l));
+	      break;
 	    case 'm':
 	      if (!EXTRACT_OPERAND (VMASK, l))
 		{
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1c3d9b0903e..763d42db4d0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1815,6 +1815,24 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
 {"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
 
+/* Zvbb instructions.  */
+{"vandn.vv",   0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
+{"vandn.vx",   0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
+{"vbrev.v",   0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV_V, MASK_VBREV_V, match_opcode, 0},
+{"vbrev8.v",   0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV8_V, MASK_VBREV8_V, match_opcode, 0},
+{"vrev8.v",   0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VREV8_V, MASK_VREV8_V, match_opcode, 0},
+{"vclz.v",   0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCLZ_V, MASK_VCLZ_V, match_opcode, 0},
+{"vctz.v",   0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCTZ_V, MASK_VCTZ_V, match_opcode, 0},
+{"vcpop.v",   0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCPOP_V, MASK_VCPOP_V, match_opcode, 0},
+{"vrol.vv",    0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VROL_VV, MASK_VROL_VV, match_opcode, 0},
+{"vrol.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VROL_VX, MASK_VROL_VX, match_opcode, 0},
+{"vror.vv",    0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VROR_VV, MASK_VROR_VV, match_opcode, 0},
+{"vror.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VROR_VX, MASK_VROR_VX, match_opcode, 0},
+{"vror.vi",    0, INSN_CLASS_ZVBB, "Vd,Vt,VlVm", MATCH_VROR_VI, MASK_VROR_VI, match_opcode, 0},
+{"vwsll.vv",    0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VWSLL_VV, MASK_VWSLL_VV, match_opcode, 0},
+{"vwsll.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
+{"vwsll.vi",    0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 02/14] Add support for the Zvbc ISA extension.

[Nathan Huckleberry]

Zvbc is part of the crypto vector extensions.

This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c              |  5 +++++
 gas/testsuite/gas/riscv/zvbc.d | 16 ++++++++++++++++
 gas/testsuite/gas/riscv/zvbc.s |  8 ++++++++
 include/opcode/riscv-opc.h     | 14 ++++++++++++++
 include/opcode/riscv.h         |  1 +
 opcodes/riscv-opc.c            |  6 ++++++
 6 files changed, 50 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvbc.d
 create mode 100644 gas/testsuite/gas/riscv/zvbc.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8342b4fb3cc..a56b2b840b6 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1260,6 +1260,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2414,6 +2415,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve32f"));
     case INSN_CLASS_ZVBB:
       return riscv_subset_supports (rps, "zvbb");
+    case INSN_CLASS_ZVBC:
+      return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2576,6 +2579,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
+    case INSN_CLASS_ZVBC:
+      return _("zvbc");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvbc.d b/gas/testsuite/gas/riscv/zvbc.d
new file mode 100644
index 00000000000..d9213b25b01
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.d
@@ -0,0 +1,16 @@
+#as: -march=rv64gc_zvbc
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+32862257[ 	]+vclmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+30862257[ 	]+vclmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3285e257[ 	]+vclmul.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3085e257[ 	]+vclmul.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+36862257[ 	]+vclmulh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+34862257[ 	]+vclmulh.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3685e257[ 	]+vclmulh.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3485e257[ 	]+vclmulh.vx[ 	]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvbc.s b/gas/testsuite/gas/riscv/zvbc.s
new file mode 100644
index 00000000000..c302d1eb011
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.s
@@ -0,0 +1,8 @@
+	vclmul.vv v4, v8, v12
+	vclmul.vv v4, v8, v12, v0.t
+	vclmul.vx v4, v8, a1
+	vclmul.vx v4, v8, a1, v0.t
+	vclmulh.vv v4, v8, v12
+	vclmulh.vv v4, v8, v12, v0.t
+	vclmulh.vx v4, v8, a1
+	vclmulh.vx v4, v8, a1, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cde8c341b6b..e1f2966499a 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2088,6 +2088,15 @@
 #define MASK_VWSLL_VV 0xfc00707f
 #define MATCH_VWSLL_VX 0xd4004057
 #define MASK_VWSLL_VX 0xfc00707f
+/* Zvbc instructions. */
+#define MATCH_VCLMUL_VV 0x30002057
+#define MASK_VCLMUL_VV 0xfc00707f
+#define MATCH_VCLMUL_VX 0x30006057
+#define MASK_VCLMUL_VX 0xfc00707f
+#define MATCH_VCLMULH_VV 0x34002057
+#define MASK_VCLMULH_VV 0xfc00707f
+#define MATCH_VCLMULH_VX 0x34006057
+#define MASK_VCLMULH_VX 0xfc00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3173,6 +3182,11 @@ DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
 DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
 DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
 DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
+/* Zvbc instructions.  */
+DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
+DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
+DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
+DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 296fbe2640c..0f00bc2e6fb 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -410,6 +410,7 @@ enum riscv_insn_class
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
+  INSN_CLASS_ZVBC,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 763d42db4d0..79a5e2c694a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1833,6 +1833,12 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vwsll.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
 {"vwsll.vi",    0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
 
+/* Zvbc instructions.  */
+{"vclmul.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
+{"vclmul.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
+{"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
+{"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 03/14] Add support for the Zvkg ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvkg is part of the vector crypto extensions.

This extension adds the following instructions:
- vghsh.vv
- vgmul.vv

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c              |  5 +++++
 gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++
 gas/testsuite/gas/riscv/zvkg.s |  2 ++
 include/opcode/riscv-opc.h     |  8 ++++++++
 include/opcode/riscv.h         |  1 +
 opcodes/riscv-opc.c            |  4 ++++
 6 files changed, 30 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkg.d
 create mode 100644 gas/testsuite/gas/riscv/zvkg.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a56b2b840b6..b51d4f4438f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1261,6 +1261,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2417,6 +2418,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
       return riscv_subset_supports (rps, "zvbc");
+    case INSN_CLASS_ZVKG:
+      return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2581,6 +2584,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbb");
     case INSN_CLASS_ZVBC:
       return _("zvbc");
+    case INSN_CLASS_ZVKG:
+      return _("zvkg");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644
index 00000000000..7f898d377b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+b2862277[ 	]+vghsh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+a2c8a277[ 	]+vgmul.vv[ 	]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644
index 00000000000..b802d6add39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1,2 @@
+	vghsh.vv v4, v8, v12
+	vgmul.vv v4, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index e1f2966499a..9bc75fd0e59 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2097,6 +2097,11 @@
 #define MASK_VCLMULH_VV 0xfc00707f
 #define MATCH_VCLMULH_VX 0x34006057
 #define MASK_VCLMULH_VX 0xfc00707f
+/* Zvkg instructions.  */
+#define MATCH_VGHSH_VV 0xb2002077
+#define MASK_VGHSH_VV 0xfe00707f
+#define MATCH_VGMUL_VV 0xa208a077
+#define MASK_VGMUL_VV 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3187,6 +3192,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
 DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
 DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
 DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
+/* Zvkg instructions.  */
+DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
+DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0f00bc2e6fb..ae13dc17022 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -411,6 +411,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
+  INSN_CLASS_ZVKG,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 79a5e2c694a..09c8444ee74 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1839,6 +1839,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
 {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
 
+/* Zvkg instructions.  */
+{"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
+{"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 04/14] Add support for the Zvkned ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvkned is part of the vector crypto extensions.

This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c                |  5 +++++
 gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
 gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
 include/opcode/riscv-opc.h       | 35 ++++++++++++++++++++++++++++++++
 include/opcode/riscv.h           |  1 +
 opcodes/riscv-opc.c              | 13 ++++++++++++
 6 files changed, 88 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkned.d
 create mode 100644 gas/testsuite/gas/riscv/zvkned.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b51d4f4438f..cb3420540e9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1262,6 +1262,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2420,6 +2421,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
+    case INSN_CLASS_ZVKNED:
+      return riscv_subset_supports (rps, "zvkned");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2586,6 +2589,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbc");
     case INSN_CLASS_ZVKG:
       return _("zvkg");
+    case INSN_CLASS_ZVKNED:
+      return _("zvkned");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkned.d b/gas/testsuite/gas/riscv/zvkned.d
new file mode 100644
index 00000000000..0b09da9dbc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.d
@@ -0,0 +1,21 @@
+#as: -march=rv64gc_zvkned
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a680a277[ 	]+vaesdf.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a2802277[ 	]+vaesdm.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6802277[ 	]+vaesdm.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a281a277[ 	]+vaesef.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a681a277[ 	]+vaesef.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a2812277[ 	]+vaesem.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6812277[ 	]+vaesem.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a812277[ 	]+vaeskf1.vi[ 	]+v4,v8,2
+[ 	]+[0-9a-f]+:[ 	]+8a872277[ 	]+vaeskf1.vi[ 	]+v4,v8,14
+[ 	]+[0-9a-f]+:[ 	]+aa812277[ 	]+vaeskf2.vi[ 	]+v4,v8,2
+[ 	]+[0-9a-f]+:[ 	]+aa872277[ 	]+vaeskf2.vi[ 	]+v4,v8,14
+[ 	]+[0-9a-f]+:[ 	]+a683a277[ 	]+vaesz.vs[ 	]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkned.s b/gas/testsuite/gas/riscv/zvkned.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.s
@@ -0,0 +1,13 @@
+	vaesdf.vv v4, v8
+	vaesdf.vs v4, v8
+	vaesdm.vv v4, v8
+	vaesdm.vs v4, v8
+	vaesef.vv v4, v8
+	vaesef.vs v4, v8
+	vaesem.vv v4, v8
+	vaesem.vs v4, v8
+	vaeskf1.vi v4, v8, 2
+	vaeskf1.vi v4, v8, 14
+	vaeskf2.vi v4, v8, 2
+	vaeskf2.vi v4, v8, 14
+	vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9bc75fd0e59..48ba80cda63 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2102,6 +2102,29 @@
 #define MASK_VGHSH_VV 0xfe00707f
 #define MATCH_VGMUL_VV 0xa208a077
 #define MASK_VGMUL_VV 0xfe0ff07f
+/* Zvkned instructions.  */
+#define MATCH_VAESDF_VS 0xa600a077
+#define MASK_VAESDF_VS 0xfe0ff07f
+#define MATCH_VAESDF_VV 0xa200a077
+#define MASK_VAESDF_VV 0xfe0ff07f
+#define MATCH_VAESDM_VS 0xa6002077
+#define MASK_VAESDM_VS 0xfe0ff07f
+#define MATCH_VAESDM_VV 0xa2002077
+#define MASK_VAESDM_VV 0xfe0ff07f
+#define MATCH_VAESEF_VS 0xa601a077
+#define MASK_VAESEF_VS 0xfe0ff07f
+#define MATCH_VAESEF_VV 0xa201a077
+#define MASK_VAESEF_VV 0xfe0ff07f
+#define MATCH_VAESEM_VS 0xa6012077
+#define MASK_VAESEM_VS 0xfe0ff07f
+#define MATCH_VAESEM_VV 0xa2012077
+#define MASK_VAESEM_VV 0xfe0ff07f
+#define MATCH_VAESKF1_VI 0x8a002077
+#define MASK_VAESKF1_VI 0xfe00707f
+#define MATCH_VAESKF2_VI 0xaa002077
+#define MASK_VAESKF2_VI 0xfe00707f
+#define MATCH_VAESZ_VS 0xa603a077
+#define MASK_VAESZ_VS 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3195,6 +3218,18 @@ DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
 DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
+/* Zvkned instructions.  */
+DECLARE_INSN(vaesdf_vs, MATCH_VAESDF_VS, MASK_VAESDF_VS)
+DECLARE_INSN(vaesdf_vv, MATCH_VAESDF_VV, MASK_VAESDF_VV)
+DECLARE_INSN(vaesdm_vs, MATCH_VAESDM_VS, MASK_VAESDM_VS)
+DECLARE_INSN(vaesdm_vv, MATCH_VAESDM_VV, MASK_VAESDM_VV)
+DECLARE_INSN(vaesef_vs, MATCH_VAESEF_VS, MASK_VAESEF_VS)
+DECLARE_INSN(vaesef_vv, MATCH_VAESEF_VV, MASK_VAESEF_VV)
+DECLARE_INSN(vaesem_vs, MATCH_VAESEM_VS, MASK_VAESEM_VS)
+DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
+DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
+DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
+DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index ae13dc17022..e921e1b8a2a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -412,6 +412,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVKG,
+  INSN_CLASS_ZVKNED,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 09c8444ee74..7e73c1a739d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1843,6 +1843,19 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
 
+/* Zvkned instructions.  */
+{"vaesdf.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VV, MASK_VAESDF_VV, match_opcode, 0},
+{"vaesdf.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VS, MASK_VAESDF_VV, match_opcode, 0},
+{"vaesdm.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VV, MASK_VAESDM_VV, match_opcode, 0},
+{"vaesdm.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VS, MASK_VAESDM_VV, match_opcode, 0},
+{"vaesef.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VV, MASK_VAESEF_VV, match_opcode, 0},
+{"vaesef.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VS, MASK_VAESEF_VV, match_opcode, 0},
+{"vaesem.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VV, MASK_VAESEM_VV, match_opcode, 0},
+{"vaesem.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VS, MASK_VAESEM_VV, match_opcode, 0},
+{"vaeskf1.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1_VI, MASK_VAESKF1_VI, match_opcode, 0},
+{"vaeskf2.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
+{"vaesz.vs",     0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 05/14] Add support for the Zvknh[a,b] ISA extensions.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvknh[a,b] are parts of the vector crypto extensions.

This extension adds the following instructions:
- vsha2ms.vv
- vsha2c[hl].vv

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c                       | 13 +++++++++++++
 gas/testsuite/gas/riscv/zvknha.d        | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvknha_zvknhb.s |  3 +++
 gas/testsuite/gas/riscv/zvknhb.d        | 12 ++++++++++++
 include/opcode/riscv-opc.h              | 11 +++++++++++
 include/opcode/riscv.h                  |  3 +++
 opcodes/riscv-opc.c                     |  5 +++++
 7 files changed, 59 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvknha.d
 create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
 create mode 100644 gas/testsuite/gas/riscv/zvknhb.d

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb3420540e9..adcc606fe7e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1263,6 +1263,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2423,6 +2425,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_ZVKNED:
       return riscv_subset_supports (rps, "zvkned");
+    case INSN_CLASS_ZVKNHA:
+      return riscv_subset_supports (rps, "zvknha");
+    case INSN_CLASS_ZVKNHB:
+      return riscv_subset_supports (rps, "zvknhb");
+    case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
+      return (riscv_subset_supports (rps, "zvknha")
+	      || riscv_subset_supports (rps, "zvknhb"));
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2591,6 +2600,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvkg");
     case INSN_CLASS_ZVKNED:
       return _("zvkned");
+    case INSN_CLASS_ZVKNHA:
+      return _("zvknha");
+    case INSN_CLASS_ZVKNHB:
+      return _("zvknhb");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/zvknha.d
new file mode 100644
index 00000000000..36d660f634f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknha.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvknha
+#source: zvknha_zvknhb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be862277[ 	]+vsha2cl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b6862277[ 	]+vsha2ms.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
new file mode 100644
index 00000000000..d20e6310531
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
@@ -0,0 +1,3 @@
+	vsha2ch.vv v4, v8, v12
+	vsha2cl.vv v4, v8, v12
+	vsha2ms.vv v4, v8, v12
diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/zvknhb.d
new file mode 100644
index 00000000000..ab0f035889e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknhb.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvknhb
+#source: zvknha_zvknhb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be862277[ 	]+vsha2cl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b6862277[ 	]+vsha2ms.vv[ 	]+v4,v8,v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 48ba80cda63..5590dc3b014 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2125,6 +2125,13 @@
 #define MASK_VAESKF2_VI 0xfe00707f
 #define MATCH_VAESZ_VS 0xa603a077
 #define MASK_VAESZ_VS 0xfe0ff07f
+/* Zvknh[a,b] instructions.  */
+#define MATCH_VSHA2CH_VV 0xba002077
+#define MASK_VSHA2CH_VV 0xfe00707f
+#define MATCH_VSHA2CL_VV 0xbe002077
+#define MASK_VSHA2CL_VV 0xfe00707f
+#define MATCH_VSHA2MS_VV 0xb6002077
+#define MASK_VSHA2MS_VV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3230,6 +3237,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
 DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
 DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
 DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
+/* Zvknh[a,b] instructions.  */
+DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
+DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
+DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index e921e1b8a2a..4ceb191ab07 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -413,6 +413,9 @@ enum riscv_insn_class
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
+  INSN_CLASS_ZVKNHA,
+  INSN_CLASS_ZVKNHB,
+  INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7e73c1a739d..d7d3f1c1cd2 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1856,6 +1856,11 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vaeskf2.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
 {"vaesz.vs",     0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
 
+/* Zvknh[a,b] instructions.  */
+{"vsha2ch.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV, match_opcode, 0},
+{"vsha2cl.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
+{"vsha2ms.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 06/14] Add support for the Zvksed ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvksed is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c                |  5 +++++
 gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvksed.s |  4 ++++
 include/opcode/riscv-opc.h       | 11 +++++++++++
 include/opcode/riscv.h           |  1 +
 opcodes/riscv-opc.c              |  5 +++++
 6 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksed.d
 create mode 100644 gas/testsuite/gas/riscv/zvksed.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index adcc606fe7e..0ec2552bfb9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1265,6 +1265,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2432,6 +2433,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
       return (riscv_subset_supports (rps, "zvknha")
 	      || riscv_subset_supports (rps, "zvknhb"));
+    case INSN_CLASS_ZVKSED:
+      return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2604,6 +2607,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknha");
     case INSN_CLASS_ZVKNHB:
       return _("zvknhb");
+    case INSN_CLASS_ZVKSED:
+      return _("zvksed");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d
new file mode 100644
index 00000000000..48b4aafdbb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksed
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+8683a277[ 	]+vsm4k.vi[ 	]+v4,v8,7
+[ 	]+[0-9a-f]+:[ 	]+a2882277[ 	]+vsm4r.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6882277[ 	]+vsm4r.vs[ 	]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s
new file mode 100644
index 00000000000..754b4646adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.s
@@ -0,0 +1,4 @@
+	vsm4k.vi v4, v8, 0
+	vsm4k.vi v4, v8, 7
+	vsm4r.vv v4, v8
+	vsm4r.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 5590dc3b014..415930d0e3e 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2132,6 +2132,13 @@
 #define MASK_VSHA2CL_VV 0xfe00707f
 #define MATCH_VSHA2MS_VV 0xb6002077
 #define MASK_VSHA2MS_VV 0xfe00707f
+/* Zvksed instructions.  */
+#define MATCH_VSM4K_VI 0x86002077
+#define MASK_VSM4K_VI 0xfe00707f
+#define MATCH_VSM4R_VS 0xa6082077
+#define MASK_VSM4R_VS 0xfe0ff07f
+#define MATCH_VSM4R_VV 0xa2082077
+#define MASK_VSM4R_VV 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3241,6 +3248,10 @@ DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
 DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
 DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
 DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
+/* Zvksed instructions.  */
+DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
+DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
+DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 4ceb191ab07..df807fe8f79 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHA,
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
+  INSN_CLASS_ZVKSED,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index d7d3f1c1cd2..cb164169f92 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1861,6 +1861,11 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vsha2cl.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
 {"vsha2ms.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
 
+/* Zvksed instructions.  */
+{"vsm4k.vi",     0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4K_VI, MASK_VSM4K_VI, match_opcode, 0},
+{"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
+{"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 07/14] Adds support for the Zvksh ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvksh is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm3me.vv
- vsm3c.vi

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c               |  5 +++++
 gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
 gas/testsuite/gas/riscv/zvksh.s |  3 +++
 include/opcode/riscv-opc.h      |  8 ++++++++
 include/opcode/riscv.h          |  1 +
 opcodes/riscv-opc.c             |  4 ++++
 6 files changed, 32 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksh.d
 create mode 100644 gas/testsuite/gas/riscv/zvksh.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0ec2552bfb9..77ef99d02cf 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1266,6 +1266,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2435,6 +2436,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zvknhb"));
     case INSN_CLASS_ZVKSED:
       return riscv_subset_supports (rps, "zvksed");
+    case INSN_CLASS_ZVKSH:
+      return riscv_subset_supports (rps, "zvksh");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2609,6 +2612,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknhb");
     case INSN_CLASS_ZVKSED:
       return _("zvksed");
+    case INSN_CLASS_ZVKSH:
+      return _("zvksh");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvksh.d
new file mode 100644
index 00000000000..b24d126ed7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvksh
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae8fa277[ 	]+vsm3c.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+82862277[ 	]+vsm3me.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvksh.s
new file mode 100644
index 00000000000..bde705c5e33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.s
@@ -0,0 +1,3 @@
+	vsm3c.vi v4, v8, 0
+	vsm3c.vi v4, v8, 31
+	vsm3me.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 415930d0e3e..142fa0f2660 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2139,6 +2139,11 @@
 #define MASK_VSM4R_VS 0xfe0ff07f
 #define MATCH_VSM4R_VV 0xa2082077
 #define MASK_VSM4R_VV 0xfe0ff07f
+/* Zvksh instructions.  */
+#define MATCH_VSM3C_VI 0xae002077
+#define MASK_VSM3C_VI 0xfe00707f
+#define MATCH_VSM3ME_VV 0x82002077
+#define MASK_VSM3ME_VV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3252,6 +3257,9 @@ DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
 DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
 DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
 DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
+/* Zvksh instructions.  */
+DECLARE_INSN(vsm3c_vi, MATCH_VSM3C_VI, MASK_VSM3C_VI)
+DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index df807fe8f79..338f58b4fae 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -417,6 +417,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
+  INSN_CLASS_ZVKSH,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index cb164169f92..e3235393e98 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1866,6 +1866,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
 {"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
 
+/* Zvksh instructions.  */
+{"vsm3c.vi",     0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0},
+{"vsm3me.vv",    0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 08/14] Add support for the Zvkn ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvkn is part of the vector crypto extensions.

Zvkn is shorthand for the following set of extensions:
- Zvkned
- Zvknhb
- Zvbb
- Zvkt

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c              |  5 ++++
 gas/testsuite/gas/riscv/zvkn.d | 45 ++++++++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zvkn.s | 36 +++++++++++++++++++++++++++
 3 files changed, 86 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkn.d
 create mode 100644 gas/testsuite/gas/riscv/zvkn.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 77ef99d02cf..890e10d1812 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1155,6 +1155,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zks", "zbkx",	check_implicit_always},
   {"zks", "zksed",	check_implicit_always},
   {"zks", "zksh",	check_implicit_always},
+  {"zvkn", "zvkned",	check_implicit_always},
+  {"zvkn", "zvknha",	check_implicit_always},
+  {"zvkn", "zvknhb",	check_implicit_always},
+  {"zvkn", "zvbb",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1262,6 +1266,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d
new file mode 100644
index 00000000000..abb92b9f001
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.d
@@ -0,0 +1,45 @@
+#as: -march=rv64gc_zvkn
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+06860257[ 	]+vandn.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+04860257[ 	]+vandn.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0685c257[ 	]+vandn.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0485c257[ 	]+vandn.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a852257[ 	]+vbrev.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48852257[ 	]+vbrev.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a842257[ 	]+vbrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48842257[ 	]+vbrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a862257[ 	]+vclz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48862257[ 	]+vclz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a86a257[ 	]+vctz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4886a257[ 	]+vctz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a872257[ 	]+vcpop.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48872257[ 	]+vcpop.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+56860257[ 	]+vrol.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+54860257[ 	]+vrol.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5685c257[ 	]+vrol.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5485c257[ 	]+vrol.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52860257[ 	]+vror.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+50860257[ 	]+vror.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5285c257[ 	]+vror.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5085c257[ 	]+vror.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52803257[ 	]+vror.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+548fb257[ 	]+vror.vi[ 	]+v4,v8,63,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6860257[ 	]+vwsll.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+d4860257[ 	]+vwsll.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d685c257[ 	]+vwsll.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+d485c257[ 	]+vwsll.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6803257[ 	]+vwsll.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+d48fb257[ 	]+vwsll.vi[ 	]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s
new file mode 100644
index 00000000000..44e8f1769ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.s
@@ -0,0 +1,36 @@
+	vaesdf.vv v4, v8
+	vsha2ch.vv v4, v8, v12
+	vandn.vv v4, v8, v12
+	vandn.vv v4, v8, v12, v0.t
+	vandn.vx v4, v8, a1
+	vandn.vx v4, v8, a1, v0.t
+	vbrev.v v4, v8
+	vbrev.v v4, v8, v0.t
+	vbrev8.v v4, v8
+	vbrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vclz.v v4, v8
+	vclz.v v4, v8, v0.t
+	vctz.v v4, v8
+	vctz.v v4, v8, v0.t
+	vcpop.v v4, v8
+	vcpop.v v4, v8, v0.t
+	vrol.vv v4, v8, v12
+	vrol.vv v4, v8, v12, v0.t
+	vrol.vx v4, v8, a1
+	vrol.vx v4, v8, a1, v0.t
+	vror.vv v4, v8, v12
+	vror.vv v4, v8, v12, v0.t
+	vror.vx v4, v8, a1
+	vror.vx v4, v8, a1, v0.t
+	vror.vi v4, v8, 0
+	vror.vi v4, v8, 63, v0.t
+	vwsll.vv v4, v8, v12
+	vwsll.vv v4, v8, v12, v0.t
+	vwsll.vx v4, v8, a1
+	vwsll.vx v4, v8, a1, v0.t
+	vwsll.vi v4, v8, 0
+	vwsll.vi v4, v8, 31, v0.t
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 09/14] Allow nested implications for extensions.

[Nathan Huckleberry]

Certain extensions require two levels of implications.  For example,
zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
enable zvkned.

This patch fixes this behavior.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 890e10d1812..8bb77db5528 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1870,15 +1870,27 @@ static void
 riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
 {
   struct riscv_implicit_subset *t = riscv_implicit_subsets;
-  for (; t->subset_name; t++)
+  bool finished = false;
+  while (!finished) {
+    finished = true;
+    for (; t->subset_name; t++)
     {
       riscv_subset_t *subset = NULL;
+      riscv_subset_t *implicit_subset = NULL;
       if (riscv_lookup_subset (rps->subset_list, t->subset_name, &subset)
-	  && t->check_func (t->implicit_name, subset))
+	  && !riscv_lookup_subset (rps->subset_list, t->implicit_name, &implicit_subset)
+	  && t->check_func (t->implicit_name, subset)) {
 	riscv_parse_add_subset (rps, t->implicit_name,
 				RISCV_UNKNOWN_VERSION,
 				RISCV_UNKNOWN_VERSION, true);
+
+	// Restart the loop and pick up any new implications.
+	finished = false;
+	t = riscv_implicit_subsets;
+	break;
+      }
     }
+  }
 }
 
 /* Check extensions conflicts.  */
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 10/14] Add support for the Zvkng ISA extension.

[Nathan Huckleberry]

Zvkng is part of the vector crypto extensions.

Zvkng is shorthand for the following set of extensions:
- Zvkn
- Zvkg

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c               |  3 +++
 gas/testsuite/gas/riscv/zvkng.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvkng.s |  4 ++++
 3 files changed, 19 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkng.d
 create mode 100644 gas/testsuite/gas/riscv/zvkng.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8bb77db5528..1540f2748ac 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1159,6 +1159,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvkn", "zvknha",	check_implicit_always},
   {"zvkn", "zvknhb",	check_implicit_always},
   {"zvkn", "zvbb",	check_implicit_always},
+  {"zvkng", "zvkn",	check_implicit_always},
+  {"zvkng", "zvkg",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1267,6 +1269,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkng",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvkng.d b/gas/testsuite/gas/riscv/zvkng.d
new file mode 100644
index 00000000000..1206350c7e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkng.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvkng
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b2862277[ 	]+vghsh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+a2c8a277[ 	]+vgmul.vv[ 	]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkng.s b/gas/testsuite/gas/riscv/zvkng.s
new file mode 100644
index 00000000000..5c24ffd63c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkng.s
@@ -0,0 +1,4 @@
+	vaesdf.vv v4, v8
+	vsha2ch.vv v4, v8, v12
+	vghsh.vv v4, v8, v12
+	vgmul.vv v4, v12
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 11/14] Add support for the Zvks ISA extension.

[Nathan Huckleberry]

From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvks is part of the vector crypto extensions.

Zvks is shorthand for the following set of extensions:
- Zvksed
- Zvksh
- Zvbb
- Zvkt

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c              |  4 +++
 gas/testsuite/gas/riscv/zvks.d | 45 ++++++++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zvks.s | 36 +++++++++++++++++++++++++++
 3 files changed, 85 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvks.d
 create mode 100644 gas/testsuite/gas/riscv/zvks.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 1540f2748ac..eba3ef654e9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1161,6 +1161,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvkn", "zvbb",	check_implicit_always},
   {"zvkng", "zvkn",	check_implicit_always},
   {"zvkng", "zvkg",	check_implicit_always},
+  {"zvks", "zvksed",	check_implicit_always},
+  {"zvks", "zvksh",	check_implicit_always},
+  {"zvks", "zvbb",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1275,6 +1278,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvks",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvks.d b/gas/testsuite/gas/riscv/zvks.d
new file mode 100644
index 00000000000..2f55630f505
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvks.d
@@ -0,0 +1,45 @@
+#as: -march=rv64gc_zvks
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+06860257[ 	]+vandn.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+04860257[ 	]+vandn.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0685c257[ 	]+vandn.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0485c257[ 	]+vandn.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a852257[ 	]+vbrev.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48852257[ 	]+vbrev.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a842257[ 	]+vbrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48842257[ 	]+vbrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a862257[ 	]+vclz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48862257[ 	]+vclz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a86a257[ 	]+vctz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4886a257[ 	]+vctz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a872257[ 	]+vcpop.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48872257[ 	]+vcpop.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+56860257[ 	]+vrol.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+54860257[ 	]+vrol.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5685c257[ 	]+vrol.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5485c257[ 	]+vrol.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52860257[ 	]+vror.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+50860257[ 	]+vror.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5285c257[ 	]+vror.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5085c257[ 	]+vror.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52803257[ 	]+vror.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+548fb257[ 	]+vror.vi[ 	]+v4,v8,63,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6860257[ 	]+vwsll.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+d4860257[ 	]+vwsll.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d685c257[ 	]+vwsll.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+d485c257[ 	]+vwsll.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6803257[ 	]+vwsll.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+d48fb257[ 	]+vwsll.vi[ 	]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvks.s b/gas/testsuite/gas/riscv/zvks.s
new file mode 100644
index 00000000000..b0d3d824f3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvks.s
@@ -0,0 +1,36 @@
+	vsm4k.vi v4, v8, 0
+	vsm3c.vi v4, v8, 0
+	vandn.vv v4, v8, v12
+	vandn.vv v4, v8, v12, v0.t
+	vandn.vx v4, v8, a1
+	vandn.vx v4, v8, a1, v0.t
+	vbrev.v v4, v8
+	vbrev.v v4, v8, v0.t
+	vbrev8.v v4, v8
+	vbrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vclz.v v4, v8
+	vclz.v v4, v8, v0.t
+	vctz.v v4, v8
+	vctz.v v4, v8, v0.t
+	vcpop.v v4, v8
+	vcpop.v v4, v8, v0.t
+	vrol.vv v4, v8, v12
+	vrol.vv v4, v8, v12, v0.t
+	vrol.vx v4, v8, a1
+	vrol.vx v4, v8, a1, v0.t
+	vror.vv v4, v8, v12
+	vror.vv v4, v8, v12, v0.t
+	vror.vx v4, v8, a1
+	vror.vx v4, v8, a1, v0.t
+	vror.vi v4, v8, 0
+	vror.vi v4, v8, 63, v0.t
+	vwsll.vv v4, v8, v12
+	vwsll.vv v4, v8, v12, v0.t
+	vwsll.vx v4, v8, a1
+	vwsll.vx v4, v8, a1, v0.t
+	vwsll.vi v4, v8, 0
+	vwsll.vi v4, v8, 31, v0.t
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 12/14] Add support for the Zvksg ISA extension.

[Nathan Huckleberry]

Zvksg is part of the vector crypto extensions.

Zvksg is shorthand for the following set of extensions:
- Zvks
- Zvkg

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c               |  3 +++
 gas/testsuite/gas/riscv/zvksg.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvksg.s |  4 ++++
 3 files changed, 19 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksg.d
 create mode 100644 gas/testsuite/gas/riscv/zvksg.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index eba3ef654e9..a1a60d5d4b4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1164,6 +1164,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvks", "zvksed",	check_implicit_always},
   {"zvks", "zvksh",	check_implicit_always},
   {"zvks", "zvbb",	check_implicit_always},
+  {"zvksg", "zvks",	check_implicit_always},
+  {"zvksg", "zvkg",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1279,6 +1281,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvks",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvksg.d b/gas/testsuite/gas/riscv/zvksg.d
new file mode 100644
index 00000000000..24a7126e9a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksg.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksg
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+b2862277[ 	]+vghsh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+a2c8a277[ 	]+vgmul.vv[ 	]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvksg.s b/gas/testsuite/gas/riscv/zvksg.s
new file mode 100644
index 00000000000..8da053e1d6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksg.s
@@ -0,0 +1,4 @@
+	vsm4k.vi v4, v8, 0
+	vsm3c.vi v4, v8, 0
+	vghsh.vv v4, v8, v12
+	vgmul.vv v4, v12
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 13/14] Add support for the Zvknc ISA extension.

[Nathan Huckleberry]

Zvknc is part of the vector crypto extensions.

Zvknc is shorthand for the following set of extensxions:
- Zvkn
- Zvbc

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c               |  3 +++
 gas/testsuite/gas/riscv/zvknc.d | 18 ++++++++++++++++++
 gas/testsuite/gas/riscv/zvknc.s | 10 ++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvknc.d
 create mode 100644 gas/testsuite/gas/riscv/zvknc.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a1a60d5d4b4..e62508af014 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1161,6 +1161,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvkn", "zvbb",	check_implicit_always},
   {"zvkng", "zvkn",	check_implicit_always},
   {"zvkng", "zvkg",	check_implicit_always},
+  {"zvknc", "zvkn",	check_implicit_always},
+  {"zvknc", "zvbc",	check_implicit_always},
   {"zvks", "zvksed",	check_implicit_always},
   {"zvks", "zvksh",	check_implicit_always},
   {"zvks", "zvbb",	check_implicit_always},
@@ -1275,6 +1277,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkng",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvknc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvknc.d b/gas/testsuite/gas/riscv/zvknc.d
new file mode 100644
index 00000000000..f68103b129e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknc.d
@@ -0,0 +1,18 @@
+#as: -march=rv64gc_zvknc
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+32862257[ 	+vclmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+30862257[ 	]+vclmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3285e257[ 	 ]+vclmul.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3085e257[ 	 ]+vclmul.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+36862257[ 	 ]+vclmulh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+34862257[ 	 ]+vclmulh.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3685e257[ 	 ]+vclmulh.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3485e257[ 	 ]+vclmulh.vx[ 	]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvknc.s b/gas/testsuite/gas/riscv/zvknc.s
new file mode 100644
index 00000000000..60b10d8b8b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknc.s
@@ -0,0 +1,10 @@
+	vaesdf.vv v4, v8
+	vsha2ch.vv v4, v8, v12
+	vclmul.vv v4, v8, v12
+	vclmul.vv v4, v8, v12, v0.t
+	vclmul.vx v4, v8, a1
+	vclmul.vx v4, v8, a1, v0.t
+	vclmulh.vv v4, v8, v12
+	vclmulh.vv v4, v8, v12, v0.t
+	vclmulh.vx v4, v8, a1
+	vclmulh.vx v4, v8, a1, v0.t
-- 
2.41.0.255.g8b1d071c50-goog

[PATCH 14/14] Add support for the Zvksc ISA extension.

[Nathan Huckleberry]

Zvksc is part of the vector crypto extensions.

Zvksc is shorthand for the following set of extensions:
- Zvks
- Zvbc

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c               |  3 +++
 gas/testsuite/gas/riscv/zvksc.d | 18 ++++++++++++++++++
 gas/testsuite/gas/riscv/zvksc.s | 10 ++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksc.d
 create mode 100644 gas/testsuite/gas/riscv/zvksc.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e62508af014..95e079eeceb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1168,6 +1168,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvks", "zvbb",	check_implicit_always},
   {"zvksg", "zvks",	check_implicit_always},
   {"zvksg", "zvkg",	check_implicit_always},
+  {"zvksc", "zvks",	check_implicit_always},
+  {"zvksc", "zvbc",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1285,6 +1287,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvks",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvksc.d b/gas/testsuite/gas/riscv/zvksc.d
new file mode 100644
index 00000000000..8614ede5ccf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksc.d
@@ -0,0 +1,18 @@
+#as: -march=rv64gc_zvksc
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+32862257[ 	]+vclmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+30862257[ 	]+vclmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3285e257[ 	 ]+vclmul.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3085e257[ 	 ]+vclmul.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+36862257[ 	 ]+vclmulh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+34862257[ 	 ]+vclmulh.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3685e257[ 	 ]+vclmulh.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3485e257[ 	 ]+vclmulh.vx[ 	]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvksc.s b/gas/testsuite/gas/riscv/zvksc.s
new file mode 100644
index 00000000000..aed60105c69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksc.s
@@ -0,0 +1,10 @@
+	vsm4k.vi v4, v8, 0
+	vsm3c.vi v4, v8, 0
+	vclmul.vv v4, v8, v12
+	vclmul.vv v4, v8, v12, v0.t
+	vclmul.vx v4, v8, a1
+	vclmul.vx v4, v8, a1, v0.t
+	vclmulh.vv v4, v8, v12
+	vclmulh.vv v4, v8, v12, v0.t
+	vclmulh.vx v4, v8, a1
+	vclmulh.vx v4, v8, a1, v0.t
-- 
2.41.0.255.g8b1d071c50-goog

Re: [PATCH 01/14] Add support for the Zvbb ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvbb is part of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vandn.[vv,vx]
> - vbrev.v
> - vbrev8.v
> - vrev8.v
> - vclz.v
> - vctz.v
> - vcpop.v
> - vrol.[vv,vx]
> - vror.[vv,vx,vi]
> - vwsll.[vv,vx,vi]
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c              |  5 ++++
>   gas/config/tc-riscv.c          | 13 +++++++++
>   gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
>   gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
>   include/opcode/riscv-opc.h     | 50 ++++++++++++++++++++++++++++++++++
>   include/opcode/riscv.h         |  5 ++++
>   opcodes/riscv-dis.c            |  4 +++
>   opcodes/riscv-opc.c            | 18 ++++++++++++
>   8 files changed, 172 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvbb.d
>   create mode 100644 gas/testsuite/gas/riscv/zvbb.s
This needs appropriate ChangeLog entries as well as an update to the 
binutils/NEWS file.  With those missing pieces this will be OK for the 
trunk.

Sometimes I'm willing to cobble together ChangeLogs, but with 14 patches 
in the kit, I'm not going to have the time.  If a suitable ChangeLog and 
NEWS file is provided today, I can go ahead and push it to the trunk.  I 
might be able to do that Sat/Sun as well, but I can't commit to that.

I don't offhand know Nick's policy WRT patches going into a release 
branch.  So while I can ACK this for the trunk with a suitable 
ChangeLog/NEWS file entry, I don't know if that ACK will apply to the 
upcoming 2.41 branch if this doesn't get pushed to the trunk before Nick 
makes the branch (Sunday, July 2).


Jeff

Re: [PATCH 02/14] Add support for the Zvbc ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> Zvbc is part of the crypto vector extensions.
> 
> This extension adds the following instructions:
> - vclmul.[vv,vx]
> - vclmulh.[vv,vx]
> 
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c              |  5 +++++
>   gas/testsuite/gas/riscv/zvbc.d | 16 ++++++++++++++++
>   gas/testsuite/gas/riscv/zvbc.s |  8 ++++++++
>   include/opcode/riscv-opc.h     | 14 ++++++++++++++
>   include/opcode/riscv.h         |  1 +
>   opcodes/riscv-opc.c            |  6 ++++++
>   6 files changed, 50 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvbc.d
>   create mode 100644 gas/testsuite/gas/riscv/zvbc.s
Same as patch 01/14 in this series.  Needs ChangeLog & NEWS entries.

jeff

Re: [PATCH 04/14] Add support for the Zvkned ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvkned is part of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vaesef.[vv,vs]
> - vaesem.[vv,vs]
> - vaesdf.[vv,vs]
> - vaesdm.[vv,vs]
> - vaeskf1.vi
> - vaeskf2.vi
> - vaesz.vs
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c                |  5 +++++
>   gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
>   gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
>   include/opcode/riscv-opc.h       | 35 ++++++++++++++++++++++++++++++++
>   include/opcode/riscv.h           |  1 +
>   opcodes/riscv-opc.c              | 13 ++++++++++++
>   6 files changed, 88 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvkned.d
>   create mode 100644 gas/testsuite/gas/riscv/zvkned.s
Same as 01-03 in this series.  Just needs ChangeLog and NEWS entries and 
it's OK for the trunk.

Thanks,
jeff

Re: [PATCH 05/14] Add support for the Zvknh[a,b] ISA extensions.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvknh[a,b] are parts of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vsha2ms.vv
> - vsha2c[hl].vv
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c                       | 13 +++++++++++++
>   gas/testsuite/gas/riscv/zvknha.d        | 12 ++++++++++++
>   gas/testsuite/gas/riscv/zvknha_zvknhb.s |  3 +++
>   gas/testsuite/gas/riscv/zvknhb.d        | 12 ++++++++++++
>   include/opcode/riscv-opc.h              | 11 +++++++++++
>   include/opcode/riscv.h                  |  3 +++
>   opcodes/riscv-opc.c                     |  5 +++++
>   7 files changed, 59 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvknha.d
>   create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
>   create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
Same as 01-04 in this kit.  Just needs ChangeLog and NEWS entries.

jeff

Re: [PATCH 06/14] Add support for the Zvksed ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvksed is part of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vsm4k.vi
> - vsm4r.[vv,vs]
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c                |  5 +++++
>   gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
>   gas/testsuite/gas/riscv/zvksed.s |  4 ++++
>   include/opcode/riscv-opc.h       | 11 +++++++++++
>   include/opcode/riscv.h           |  1 +
>   opcodes/riscv-opc.c              |  5 +++++
>   6 files changed, 38 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvksed.d
>   create mode 100644 gas/testsuite/gas/riscv/zvksed.s
Same as 01-05, OK with ChangeLog and NEWS entries.
jeff

Re: [PATCH 07/14] Adds support for the Zvksh ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvksh is part of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vsm3me.vv
> - vsm3c.vi
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c               |  5 +++++
>   gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
>   gas/testsuite/gas/riscv/zvksh.s |  3 +++
>   include/opcode/riscv-opc.h      |  8 ++++++++
>   include/opcode/riscv.h          |  1 +
>   opcodes/riscv-opc.c             |  4 ++++
>   6 files changed, 32 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvksh.d
>   create mode 100644 gas/testsuite/gas/riscv/zvksh.s
Same as 01-06 in the kit.  OK with ChangeLog and NEWS entries.
jeff

Re: [PATCH 08/14] Add support for the Zvkn ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvkn is part of the vector crypto extensions.
> 
> Zvkn is shorthand for the following set of extensions:
> - Zvkned
> - Zvknhb
> - Zvbb
> - Zvkt
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c              |  5 ++++
>   gas/testsuite/gas/riscv/zvkn.d | 45 ++++++++++++++++++++++++++++++++++
>   gas/testsuite/gas/riscv/zvkn.s | 36 +++++++++++++++++++++++++++
>   3 files changed, 86 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvkn.d
>   create mode 100644 gas/testsuite/gas/riscv/zvkn.s
Same as 01-07, OK with ChangeLog and NEWS entries.
jeff

Re: [PATCH 10/14] Add support for the Zvkng ISA extension.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> Zvkng is part of the vector crypto extensions.
> 
> Zvkng is shorthand for the following set of extensions:
> - Zvkn
> - Zvkg
> 
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c               |  3 +++
>   gas/testsuite/gas/riscv/zvkng.d | 12 ++++++++++++
>   gas/testsuite/gas/riscv/zvkng.s |  4 ++++
>   3 files changed, 19 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvkng.d
>   create mode 100644 gas/testsuite/gas/riscv/zvkng.s
10-14 are the same state as 01-08, OK with ChangeLog and NEWS entries. 
I'll go back and look at #9 in a bit.
jeff

Re: [PATCH 01/14] Add support for the Zvbb ISA extension.

[Christoph Müllner]

On Fri, Jun 30, 2023 at 7:51 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > Zvbb is part of the vector crypto extensions.
> >
> > This extension adds the following instructions:
> > - vandn.[vv,vx]
> > - vbrev.v
> > - vbrev8.v
> > - vrev8.v
> > - vclz.v
> > - vctz.v
> > - vcpop.v
> > - vrol.[vv,vx]
> > - vror.[vv,vx,vi]
> > - vwsll.[vv,vx,vi]
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > [Updated to newest version of RISC-V spec]
> > Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> > ---
> >   bfd/elfxx-riscv.c              |  5 ++++
> >   gas/config/tc-riscv.c          | 13 +++++++++
> >   gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
> >   gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
> >   include/opcode/riscv-opc.h     | 50 ++++++++++++++++++++++++++++++++++
> >   include/opcode/riscv.h         |  5 ++++
> >   opcodes/riscv-dis.c            |  4 +++
> >   opcodes/riscv-opc.c            | 18 ++++++++++++
> >   8 files changed, 172 insertions(+)
> >   create mode 100644 gas/testsuite/gas/riscv/zvbb.d
> >   create mode 100644 gas/testsuite/gas/riscv/zvbb.s
> This needs appropriate ChangeLog entries as well as an update to the
> binutils/NEWS file.  With those missing pieces this will be OK for the
> trunk.

I will provide that:
* Adding ChangLog entries to the commit messages
* Adding a commit that updates binutils/NEWS

I will send a new version on the list within the next hour.

>
> Sometimes I'm willing to cobble together ChangeLogs, but with 14 patches
> in the kit, I'm not going to have the time.  If a suitable ChangeLog and
> NEWS file is provided today, I can go ahead and push it to the trunk.  I
> might be able to do that Sat/Sun as well, but I can't commit to that.
>
> I don't offhand know Nick's policy WRT patches going into a release
> branch.  So while I can ACK this for the trunk with a suitable
> ChangeLog/NEWS file entry, I don't know if that ACK will apply to the
> upcoming 2.41 branch if this doesn't get pushed to the trunk before Nick
> makes the branch (Sunday, July 2).
>
>
> Jeff

Re: [PATCH 09/14] Allow nested implications for extensions.

[Jeff Law]

On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> Certain extensions require two levels of implications.  For example,
> zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
> enable zvkned.
> 
> This patch fixes this behavior.
> 
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c | 16 ++++++++++++++--
>   1 file changed, 14 insertions(+), 2 deletions(-)
No problem with the actual code.  I would suggest a comment explicitly 
stating this only allows two levels rather than arbitrary levels of nesting.

As with the others, it needs ChangeLog and NEWS entries.

With those changes it'll be fine for the trunk.

Thanks,
jeff

Re: [PATCH 01/14] Add support for the Zvbb ISA extension.

[Jeff Law]

On 6/30/23 14:29, Christoph Müllner wrote:
> On Fri, Jun 30, 2023 at 7:51 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
>>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>>
>>> Zvbb is part of the vector crypto extensions.
>>>
>>> This extension adds the following instructions:
>>> - vandn.[vv,vx]
>>> - vbrev.v
>>> - vbrev8.v
>>> - vrev8.v
>>> - vclz.v
>>> - vctz.v
>>> - vcpop.v
>>> - vrol.[vv,vx]
>>> - vror.[vv,vx,vi]
>>> - vwsll.[vv,vx,vi]
>>>
>>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>>> [Updated to newest version of RISC-V spec]
>>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
>>> ---
>>>    bfd/elfxx-riscv.c              |  5 ++++
>>>    gas/config/tc-riscv.c          | 13 +++++++++
>>>    gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
>>>    gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
>>>    include/opcode/riscv-opc.h     | 50 ++++++++++++++++++++++++++++++++++
>>>    include/opcode/riscv.h         |  5 ++++
>>>    opcodes/riscv-dis.c            |  4 +++
>>>    opcodes/riscv-opc.c            | 18 ++++++++++++
>>>    8 files changed, 172 insertions(+)
>>>    create mode 100644 gas/testsuite/gas/riscv/zvbb.d
>>>    create mode 100644 gas/testsuite/gas/riscv/zvbb.s
>> This needs appropriate ChangeLog entries as well as an update to the
>> binutils/NEWS file.  With those missing pieces this will be OK for the
>> trunk.
> 
> I will provide that:
> * Adding ChangLog entries to the commit messages
> * Adding a commit that updates binutils/NEWS
> 
> I will send a new version on the list within the next hour.
Sounds good.  Feel free to push them yourself.   Or if you don't have 
time, I'll get to them at some point before Nick branches on Sunday :-)

jeff

Re: [PATCH 09/14] Allow nested implications for extensions.

[Christoph Müllner]

On Fri, Jun 30, 2023 at 10:45 PM Jeff Law via Binutils
<binutils@sourceware.org> wrote:
>
>
>
> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> > Certain extensions require two levels of implications.  For example,
> > zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
> > enable zvkned.
> >
> > This patch fixes this behavior.
> >
> > Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> > ---
> >   bfd/elfxx-riscv.c | 16 ++++++++++++++--
> >   1 file changed, 14 insertions(+), 2 deletions(-)
> No problem with the actual code.  I would suggest a comment explicitly
> stating this only allows two levels rather than arbitrary levels of nesting.

If I read the resulting code correctly, then arbitrary nesting should
be possible.
Whenever an implicit subset is found and added, `finished` will be set to false,
`t` will be reset to the initial value and the inner loop will terminate.
The outer loop will start over because `finished` is false.
Do I miss something?

BR
Christoph

>
> As with the others, it needs ChangeLog and NEWS entries.
>
> With those changes it'll be fine for the trunk.
>
> Thanks,
> jeff

Re: [PATCH 01/14] Add support for the Zvbb ISA extension.

[Christoph Müllner]

On Fri, Jun 30, 2023 at 10:57 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 6/30/23 14:29, Christoph Müllner wrote:
> > On Fri, Jun 30, 2023 at 7:51 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
> >>
> >>
> >>
> >> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> >>> From: Christoph Müllner <christoph.muellner@vrull.eu>
> >>>
> >>> Zvbb is part of the vector crypto extensions.
> >>>
> >>> This extension adds the following instructions:
> >>> - vandn.[vv,vx]
> >>> - vbrev.v
> >>> - vbrev8.v
> >>> - vrev8.v
> >>> - vclz.v
> >>> - vctz.v
> >>> - vcpop.v
> >>> - vrol.[vv,vx]
> >>> - vror.[vv,vx,vi]
> >>> - vwsll.[vv,vx,vi]
> >>>
> >>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> >>> [Updated to newest version of RISC-V spec]
> >>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> >>> ---
> >>>    bfd/elfxx-riscv.c              |  5 ++++
> >>>    gas/config/tc-riscv.c          | 13 +++++++++
> >>>    gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
> >>>    gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
> >>>    include/opcode/riscv-opc.h     | 50 ++++++++++++++++++++++++++++++++++
> >>>    include/opcode/riscv.h         |  5 ++++
> >>>    opcodes/riscv-dis.c            |  4 +++
> >>>    opcodes/riscv-opc.c            | 18 ++++++++++++
> >>>    8 files changed, 172 insertions(+)
> >>>    create mode 100644 gas/testsuite/gas/riscv/zvbb.d
> >>>    create mode 100644 gas/testsuite/gas/riscv/zvbb.s
> >> This needs appropriate ChangeLog entries as well as an update to the
> >> binutils/NEWS file.  With those missing pieces this will be OK for the
> >> trunk.
> >
> > I will provide that:
> > * Adding ChangLog entries to the commit messages
> > * Adding a commit that updates binutils/NEWS
> >
> > I will send a new version on the list within the next hour.
> Sounds good.  Feel free to push them yourself.   Or if you don't have
> time, I'll get to them at some point before Nick branches on Sunday :-)

I have sent out v5, but I need someone else to push as I don't have
write access.
For convenience the changes can be found here as well:
  https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v5

Thanks,
Christoph

Re: [PATCH 01/14] Add support for the Zvbb ISA extension.

[Palmer Dabbelt]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 2485 bytes --]

On Fri, 30 Jun 2023 15:01:43 PDT (-0700), christoph.muellner@vrull.eu wrote:
> On Fri, Jun 30, 2023 at 10:57 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 6/30/23 14:29, Christoph Müllner wrote:
>> > On Fri, Jun 30, 2023 at 7:51 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>> >>
>> >>
>> >>
>> >> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
>> >>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>> >>>
>> >>> Zvbb is part of the vector crypto extensions.
>> >>>
>> >>> This extension adds the following instructions:
>> >>> - vandn.[vv,vx]
>> >>> - vbrev.v
>> >>> - vbrev8.v
>> >>> - vrev8.v
>> >>> - vclz.v
>> >>> - vctz.v
>> >>> - vcpop.v
>> >>> - vrol.[vv,vx]
>> >>> - vror.[vv,vx,vi]
>> >>> - vwsll.[vv,vx,vi]
>> >>>
>> >>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> >>> [Updated to newest version of RISC-V spec]
>> >>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
>> >>> ---
>> >>>    bfd/elfxx-riscv.c              |  5 ++++
>> >>>    gas/config/tc-riscv.c          | 13 +++++++++
>> >>>    gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
>> >>>    gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
>> >>>    include/opcode/riscv-opc.h     | 50 ++++++++++++++++++++++++++++++++++
>> >>>    include/opcode/riscv.h         |  5 ++++
>> >>>    opcodes/riscv-dis.c            |  4 +++
>> >>>    opcodes/riscv-opc.c            | 18 ++++++++++++
>> >>>    8 files changed, 172 insertions(+)
>> >>>    create mode 100644 gas/testsuite/gas/riscv/zvbb.d
>> >>>    create mode 100644 gas/testsuite/gas/riscv/zvbb.s
>> >> This needs appropriate ChangeLog entries as well as an update to the
>> >> binutils/NEWS file.  With those missing pieces this will be OK for the
>> >> trunk.
>> >
>> > I will provide that:
>> > * Adding ChangLog entries to the commit messages
>> > * Adding a commit that updates binutils/NEWS
>> >
>> > I will send a new version on the list within the next hour.
>> Sounds good.  Feel free to push them yourself.   Or if you don't have
>> time, I'll get to them at some point before Nick branches on Sunday :-)
>
> I have sent out v5, but I need someone else to push as I don't have
> write access.
> For convenience the changes can be found here as well:
>   https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v5

I just kicked off a test suite run, if it all passes I'll commit it -- 
but if I forget then someone else is welcome to ;)

>
> Thanks,
> Christoph

Re: [PATCH 09/14] Allow nested implications for extensions.

[Jeff Law]

On 6/30/23 15:53, Christoph Müllner wrote:
> On Fri, Jun 30, 2023 at 10:45 PM Jeff Law via Binutils
> <binutils@sourceware.org> wrote:
>>
>>
>>
>> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
>>> Certain extensions require two levels of implications.  For example,
>>> zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
>>> enable zvkned.
>>>
>>> This patch fixes this behavior.
>>>
>>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
>>> ---
>>>    bfd/elfxx-riscv.c | 16 ++++++++++++++--
>>>    1 file changed, 14 insertions(+), 2 deletions(-)
>> No problem with the actual code.  I would suggest a comment explicitly
>> stating this only allows two levels rather than arbitrary levels of nesting.
> 
> If I read the resulting code correctly, then arbitrary nesting should
> be possible.
> Whenever an implicit subset is found and added, `finished` will be set to false,
> `t` will be reset to the initial value and the inner loop will terminate.
> The outer loop will start over because `finished` is false.
> Do I miss something?
This is making my brain hurt, too late on a Friday afternoon to think. 
I should just put it under the debugger (the downside of trying to 
review code for a hands-on learner), but I don't have the time right 
now.  ISTM there needs to be a worklist of things we've found that we 
then need to scan.

But I'll trust you on this, you're a lot more familiar with this code in 
general than I am.

I wouldn't lose any sleep if you fixed formatting in this code.  We're 
supposed to be using GNU style.  So the open curley on the IF statement 
should be on its own line, indented twice (which implies the code in the 
TRUE arm ought to be reindented) and the close curley should line up 
with the open curley.

Jeff

Re: [PATCH 09/14] Allow nested implications for extensions.

[Nathan Huckleberry]

> > Whenever an implicit subset is found and added, `finished` will be set to false,
> > `t` will be reset to the initial value and the inner loop will terminate.
> > The outer loop will start over because `finished` is false.
> > Do I miss something?

This is correct. The code essentially does a BFS on the implications.

Thanks,
Huck

Re: [PATCH 09/14] Allow nested implications for extensions.

[Christoph Müllner]

On Sat, Jul 1, 2023 at 12:24 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 6/30/23 15:53, Christoph Müllner wrote:
> > On Fri, Jun 30, 2023 at 10:45 PM Jeff Law via Binutils
> > <binutils@sourceware.org> wrote:
> >>
> >>
> >>
> >> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> >>> Certain extensions require two levels of implications.  For example,
> >>> zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
> >>> enable zvkned.
> >>>
> >>> This patch fixes this behavior.
> >>>
> >>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> >>> ---
> >>>    bfd/elfxx-riscv.c | 16 ++++++++++++++--
> >>>    1 file changed, 14 insertions(+), 2 deletions(-)
> >> No problem with the actual code.  I would suggest a comment explicitly
> >> stating this only allows two levels rather than arbitrary levels of nesting.
> >
> > If I read the resulting code correctly, then arbitrary nesting should
> > be possible.
> > Whenever an implicit subset is found and added, `finished` will be set to false,
> > `t` will be reset to the initial value and the inner loop will terminate.
> > The outer loop will start over because `finished` is false.
> > Do I miss something?
> This is making my brain hurt, too late on a Friday afternoon to think.
> I should just put it under the debugger (the downside of trying to
> review code for a hands-on learner), but I don't have the time right
> now.  ISTM there needs to be a worklist of things we've found that we
> then need to scan.
>
> But I'll trust you on this, you're a lot more familiar with this code in
> general than I am.
>
> I wouldn't lose any sleep if you fixed formatting in this code.  We're
> supposed to be using GNU style.  So the open curley on the IF statement
> should be on its own line, indented twice (which implies the code in the
> TRUE arm ought to be reindented) and the close curley should line up
> with the open curley.

I tested all patches with check_GNU_style.sh and it only found
what you have commented here.

Since nobody has pushed this series so far, I have updated the code
and sent out a v6
which can also be found here:
  https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v6

Thanks,
Christoph

>
>
>
>

Re: [PATCH 09/14] Allow nested implications for extensions.

[Jeff Law]

On 6/30/23 23:22, Christoph Müllner wrote:
> On Sat, Jul 1, 2023 at 12:24 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 6/30/23 15:53, Christoph Müllner wrote:
>>> On Fri, Jun 30, 2023 at 10:45 PM Jeff Law via Binutils
>>> <binutils@sourceware.org> wrote:
>>>>
>>>>
>>>>
>>>> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
>>>>> Certain extensions require two levels of implications.  For example,
>>>>> zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
>>>>> enable zvkned.
>>>>>
>>>>> This patch fixes this behavior.
>>>>>
>>>>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
>>>>> ---
>>>>>     bfd/elfxx-riscv.c | 16 ++++++++++++++--
>>>>>     1 file changed, 14 insertions(+), 2 deletions(-)
>>>> No problem with the actual code.  I would suggest a comment explicitly
>>>> stating this only allows two levels rather than arbitrary levels of nesting.
>>>
>>> If I read the resulting code correctly, then arbitrary nesting should
>>> be possible.
>>> Whenever an implicit subset is found and added, `finished` will be set to false,
>>> `t` will be reset to the initial value and the inner loop will terminate.
>>> The outer loop will start over because `finished` is false.
>>> Do I miss something?
>> This is making my brain hurt, too late on a Friday afternoon to think.
>> I should just put it under the debugger (the downside of trying to
>> review code for a hands-on learner), but I don't have the time right
>> now.  ISTM there needs to be a worklist of things we've found that we
>> then need to scan.
>>
>> But I'll trust you on this, you're a lot more familiar with this code in
>> general than I am.
>>
>> I wouldn't lose any sleep if you fixed formatting in this code.  We're
>> supposed to be using GNU style.  So the open curley on the IF statement
>> should be on its own line, indented twice (which implies the code in the
>> TRUE arm ought to be reindented) and the close curley should line up
>> with the open curley.
> 
> I tested all patches with check_GNU_style.sh and it only found
> what you have commented here.
> 
> Since nobody has pushed this series so far, I have updated the code
> and sent out a v6
> which can also be found here:
>    https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v6
Thank you!  That'll be so much easier than applying things by hand! 
Fetching that remote now ;-)

jeff

Re: [PATCH 09/14] Allow nested implications for extensions.

[Jeff Law]

On 6/30/23 23:22, Christoph Müllner wrote:
> On Sat, Jul 1, 2023 at 12:24 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 6/30/23 15:53, Christoph Müllner wrote:
>>> On Fri, Jun 30, 2023 at 10:45 PM Jeff Law via Binutils
>>> <binutils@sourceware.org> wrote:
>>>>
>>>>
>>>>
>>>> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
>>>>> Certain extensions require two levels of implications.  For example,
>>>>> zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
>>>>> enable zvkned.
>>>>>
>>>>> This patch fixes this behavior.
>>>>>
>>>>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
>>>>> ---
>>>>>     bfd/elfxx-riscv.c | 16 ++++++++++++++--
>>>>>     1 file changed, 14 insertions(+), 2 deletions(-)
>>>> No problem with the actual code.  I would suggest a comment explicitly
>>>> stating this only allows two levels rather than arbitrary levels of nesting.
>>>
>>> If I read the resulting code correctly, then arbitrary nesting should
>>> be possible.
>>> Whenever an implicit subset is found and added, `finished` will be set to false,
>>> `t` will be reset to the initial value and the inner loop will terminate.
>>> The outer loop will start over because `finished` is false.
>>> Do I miss something?
>> This is making my brain hurt, too late on a Friday afternoon to think.
>> I should just put it under the debugger (the downside of trying to
>> review code for a hands-on learner), but I don't have the time right
>> now.  ISTM there needs to be a worklist of things we've found that we
>> then need to scan.
>>
>> But I'll trust you on this, you're a lot more familiar with this code in
>> general than I am.
>>
>> I wouldn't lose any sleep if you fixed formatting in this code.  We're
>> supposed to be using GNU style.  So the open curley on the IF statement
>> should be on its own line, indented twice (which implies the code in the
>> TRUE arm ought to be reindented) and the close curley should line up
>> with the open curley.
> 
> I tested all patches with check_GNU_style.sh and it only found
> what you have commented here.
> 
> Since nobody has pushed this series so far, I have updated the code
> and sent out a v6
> which can also be found here:
>    https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v6
I had to fix Nathan's email address in various commits to satisfy the 
commit hooks.  So while the git hashes have changed, the actual source 
contents pushed to the trunk are the same.

Thanks!

jeff

Re: [PATCH 09/14] Allow nested implications for extensions.

[Christoph Müllner]

On Sat, Jul 1, 2023 at 3:33 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 6/30/23 23:22, Christoph Müllner wrote:
> > On Sat, Jul 1, 2023 at 12:24 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
> >>
> >>
> >>
> >> On 6/30/23 15:53, Christoph Müllner wrote:
> >>> On Fri, Jun 30, 2023 at 10:45 PM Jeff Law via Binutils
> >>> <binutils@sourceware.org> wrote:
> >>>>
> >>>>
> >>>>
> >>>> On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> >>>>> Certain extensions require two levels of implications.  For example,
> >>>>> zvkng implies zvkn and zvkn implies zvkned.  Enabling zvkng should also
> >>>>> enable zvkned.
> >>>>>
> >>>>> This patch fixes this behavior.
> >>>>>
> >>>>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> >>>>> ---
> >>>>>     bfd/elfxx-riscv.c | 16 ++++++++++++++--
> >>>>>     1 file changed, 14 insertions(+), 2 deletions(-)
> >>>> No problem with the actual code.  I would suggest a comment explicitly
> >>>> stating this only allows two levels rather than arbitrary levels of nesting.
> >>>
> >>> If I read the resulting code correctly, then arbitrary nesting should
> >>> be possible.
> >>> Whenever an implicit subset is found and added, `finished` will be set to false,
> >>> `t` will be reset to the initial value and the inner loop will terminate.
> >>> The outer loop will start over because `finished` is false.
> >>> Do I miss something?
> >> This is making my brain hurt, too late on a Friday afternoon to think.
> >> I should just put it under the debugger (the downside of trying to
> >> review code for a hands-on learner), but I don't have the time right
> >> now.  ISTM there needs to be a worklist of things we've found that we
> >> then need to scan.
> >>
> >> But I'll trust you on this, you're a lot more familiar with this code in
> >> general than I am.
> >>
> >> I wouldn't lose any sleep if you fixed formatting in this code.  We're
> >> supposed to be using GNU style.  So the open curley on the IF statement
> >> should be on its own line, indented twice (which implies the code in the
> >> TRUE arm ought to be reindented) and the close curley should line up
> >> with the open curley.
> >
> > I tested all patches with check_GNU_style.sh and it only found
> > what you have commented here.
> >
> > Since nobody has pushed this series so far, I have updated the code
> > and sent out a v6
> > which can also be found here:
> >    https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v6
> I had to fix Nathan's email address in various commits to satisfy the
> commit hooks.  So while the git hashes have changed, the actual source
> contents pushed to the trunk are the same.

Sorry for missing that!
I just downloaded the emails and applied them.
I did go through all commit messages, added the ChangeLog and cleaned
them up, but I did not look at the author line.
Thanks for fixing and pushing!

Re: [PATCH 09/14] Allow nested implications for extensions.

[Jeff Law]

On 7/2/23 14:01, Christoph Müllner wrote:

> 
> Sorry for missing that!
> I just downloaded the emails and applied them.
> I did go through all commit messages, added the ChangeLog and cleaned
> them up, but I did not look at the author line.
> Thanks for fixing and pushing!
No worries.  I didn't know the email addresses had been munged or that 
the hooks would test for that!

Jeff