* [PATCH 0/5] ppc/svp64: support SVP64 and its first insns
@ 2022-06-17 19:08 Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
` (5 more replies)
0 siblings, 6 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-17 19:08 UTC (permalink / raw)
To: binutils; +Cc: amodra, luke.leighton, Dmitry Selyutin
These patches introduce SVP64 extension and LibreSOC CPU which supports
this extension. We also provide the first 32-bit instructions, namely
setvl, svstep, svshape and svremap, plus the corresponding tests.
Dmitry Selyutin (5):
svp64: support LibreSOC architecture
ppc/svp64: support setvl instructions
ppc/svp64: support svstep instructions
ppc/svp64: support svshape instruction
ppc/svp64: support svremap instruction
gas/config/tc-ppc.c | 2 +
gas/testsuite/gas/ppc/ppc.exp | 5 +
gas/testsuite/gas/ppc/setvl.d | 2408 +++++++
gas/testsuite/gas/ppc/setvl.s | 2400 +++++++
gas/testsuite/gas/ppc/svremap.d | 10248 ++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 10240 +++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svshape.d | 1736 +++++
gas/testsuite/gas/ppc/svshape.s | 1728 +++++
gas/testsuite/gas/ppc/svstep.d | 128 +
gas/testsuite/gas/ppc/svstep.s | 120 +
include/opcode/ppc.h | 3 +
opcodes/ppc-dis.c | 5 +
opcodes/ppc-opc.c | 168 +
13 files changed, 29191 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH 1/5] svp64: support LibreSOC architecture
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-06-17 19:08 ` Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
` (4 subsequent siblings)
5 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-17 19:08 UTC (permalink / raw)
To: binutils; +Cc: amodra, luke.leighton, Dmitry Selyutin
---
gas/config/tc-ppc.c | 2 ++
include/opcode/ppc.h | 3 +++
opcodes/ppc-dis.c | 5 +++++
opcodes/ppc-opc.c | 1 +
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4d789fd16a..76bdfb2e35 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e..d5752a42e6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5..f61e6518f1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5bd6dac50..fe2fcaeb1d 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH 2/5] ppc/svp64: support setvl instructions
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
@ 2022-06-17 19:08 ` Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
` (3 subsequent siblings)
5 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-17 19:08 UTC (permalink / raw)
To: binutils; +Cc: amodra, luke.leighton, Dmitry Selyutin
---
gas/testsuite/gas/ppc/ppc.exp | 2 +
gas/testsuite/gas/ppc/setvl.d | 2408 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 2400 ++++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 42 +
4 files changed, 4852 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6a..cd4dd658ce 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..46c6d9bbc0
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,2408 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 36 00 00 58 setvl r0,r0,1,0,0,0
+ 4: 36 01 00 58 setvl r0,r0,1,0,0,1
+ 8: b6 00 00 58 setvl r0,r0,1,0,1,0
+ c: b6 01 00 58 setvl r0,r0,1,0,1,1
+ 10: 76 00 00 58 setvl r0,r0,1,1,0,0
+ 14: 76 01 00 58 setvl r0,r0,1,1,0,1
+ 18: f6 00 00 58 setvl r0,r0,1,1,1,0
+ 1c: f6 01 00 58 setvl r0,r0,1,1,1,1
+ 20: 36 28 00 58 setvl r0,r0,21,0,0,0
+ 24: 36 29 00 58 setvl r0,r0,21,0,0,1
+ 28: b6 28 00 58 setvl r0,r0,21,0,1,0
+ 2c: b6 29 00 58 setvl r0,r0,21,0,1,1
+ 30: 76 28 00 58 setvl r0,r0,21,1,0,0
+ 34: 76 29 00 58 setvl r0,r0,21,1,0,1
+ 38: f6 28 00 58 setvl r0,r0,21,1,1,0
+ 3c: f6 29 00 58 setvl r0,r0,21,1,1,1
+ 40: 36 52 00 58 setvl r0,r0,42,0,0,0
+ 44: 36 53 00 58 setvl r0,r0,42,0,0,1
+ 48: b6 52 00 58 setvl r0,r0,42,0,1,0
+ 4c: b6 53 00 58 setvl r0,r0,42,0,1,1
+ 50: 76 52 00 58 setvl r0,r0,42,1,0,0
+ 54: 76 53 00 58 setvl r0,r0,42,1,0,1
+ 58: f6 52 00 58 setvl r0,r0,42,1,1,0
+ 5c: f6 53 00 58 setvl r0,r0,42,1,1,1
+ 60: 36 64 00 58 setvl r0,r0,51,0,0,0
+ 64: 36 65 00 58 setvl r0,r0,51,0,0,1
+ 68: b6 64 00 58 setvl r0,r0,51,0,1,0
+ 6c: b6 65 00 58 setvl r0,r0,51,0,1,1
+ 70: 76 64 00 58 setvl r0,r0,51,1,0,0
+ 74: 76 65 00 58 setvl r0,r0,51,1,0,1
+ 78: f6 64 00 58 setvl r0,r0,51,1,1,0
+ 7c: f6 65 00 58 setvl r0,r0,51,1,1,1
+ 80: 36 7c 00 58 setvl r0,r0,63,0,0,0
+ 84: 36 7d 00 58 setvl r0,r0,63,0,0,1
+ 88: b6 7c 00 58 setvl r0,r0,63,0,1,0
+ 8c: b6 7d 00 58 setvl r0,r0,63,0,1,1
+ 90: 76 7c 00 58 setvl r0,r0,63,1,0,0
+ 94: 76 7d 00 58 setvl r0,r0,63,1,0,1
+ 98: f6 7c 00 58 setvl r0,r0,63,1,1,0
+ 9c: f6 7d 00 58 setvl r0,r0,63,1,1,1
+ a0: 36 3e 00 58 setvl r0,r0,32,0,0,0
+ a4: 36 3f 00 58 setvl r0,r0,32,0,0,1
+ a8: b6 3e 00 58 setvl r0,r0,32,0,1,0
+ ac: b6 3f 00 58 setvl r0,r0,32,0,1,1
+ b0: 76 3e 00 58 setvl r0,r0,32,1,0,0
+ b4: 76 3f 00 58 setvl r0,r0,32,1,0,1
+ b8: f6 3e 00 58 setvl r0,r0,32,1,1,0
+ bc: f6 3f 00 58 setvl r0,r0,32,1,1,1
+ c0: 36 00 0a 58 setvl r0,r10,1,0,0,0
+ c4: 36 01 0a 58 setvl r0,r10,1,0,0,1
+ c8: b6 00 0a 58 setvl r0,r10,1,0,1,0
+ cc: b6 01 0a 58 setvl r0,r10,1,0,1,1
+ d0: 76 00 0a 58 setvl r0,r10,1,1,0,0
+ d4: 76 01 0a 58 setvl r0,r10,1,1,0,1
+ d8: f6 00 0a 58 setvl r0,r10,1,1,1,0
+ dc: f6 01 0a 58 setvl r0,r10,1,1,1,1
+ e0: 36 28 0a 58 setvl r0,r10,21,0,0,0
+ e4: 36 29 0a 58 setvl r0,r10,21,0,0,1
+ e8: b6 28 0a 58 setvl r0,r10,21,0,1,0
+ ec: b6 29 0a 58 setvl r0,r10,21,0,1,1
+ f0: 76 28 0a 58 setvl r0,r10,21,1,0,0
+ f4: 76 29 0a 58 setvl r0,r10,21,1,0,1
+ f8: f6 28 0a 58 setvl r0,r10,21,1,1,0
+ fc: f6 29 0a 58 setvl r0,r10,21,1,1,1
+ 100: 36 52 0a 58 setvl r0,r10,42,0,0,0
+ 104: 36 53 0a 58 setvl r0,r10,42,0,0,1
+ 108: b6 52 0a 58 setvl r0,r10,42,0,1,0
+ 10c: b6 53 0a 58 setvl r0,r10,42,0,1,1
+ 110: 76 52 0a 58 setvl r0,r10,42,1,0,0
+ 114: 76 53 0a 58 setvl r0,r10,42,1,0,1
+ 118: f6 52 0a 58 setvl r0,r10,42,1,1,0
+ 11c: f6 53 0a 58 setvl r0,r10,42,1,1,1
+ 120: 36 64 0a 58 setvl r0,r10,51,0,0,0
+ 124: 36 65 0a 58 setvl r0,r10,51,0,0,1
+ 128: b6 64 0a 58 setvl r0,r10,51,0,1,0
+ 12c: b6 65 0a 58 setvl r0,r10,51,0,1,1
+ 130: 76 64 0a 58 setvl r0,r10,51,1,0,0
+ 134: 76 65 0a 58 setvl r0,r10,51,1,0,1
+ 138: f6 64 0a 58 setvl r0,r10,51,1,1,0
+ 13c: f6 65 0a 58 setvl r0,r10,51,1,1,1
+ 140: 36 7c 0a 58 setvl r0,r10,63,0,0,0
+ 144: 36 7d 0a 58 setvl r0,r10,63,0,0,1
+ 148: b6 7c 0a 58 setvl r0,r10,63,0,1,0
+ 14c: b6 7d 0a 58 setvl r0,r10,63,0,1,1
+ 150: 76 7c 0a 58 setvl r0,r10,63,1,0,0
+ 154: 76 7d 0a 58 setvl r0,r10,63,1,0,1
+ 158: f6 7c 0a 58 setvl r0,r10,63,1,1,0
+ 15c: f6 7d 0a 58 setvl r0,r10,63,1,1,1
+ 160: 36 3e 0a 58 setvl r0,r10,32,0,0,0
+ 164: 36 3f 0a 58 setvl r0,r10,32,0,0,1
+ 168: b6 3e 0a 58 setvl r0,r10,32,0,1,0
+ 16c: b6 3f 0a 58 setvl r0,r10,32,0,1,1
+ 170: 76 3e 0a 58 setvl r0,r10,32,1,0,0
+ 174: 76 3f 0a 58 setvl r0,r10,32,1,0,1
+ 178: f6 3e 0a 58 setvl r0,r10,32,1,1,0
+ 17c: f6 3f 0a 58 setvl r0,r10,32,1,1,1
+ 180: 36 00 15 58 setvl r0,r21,1,0,0,0
+ 184: 36 01 15 58 setvl r0,r21,1,0,0,1
+ 188: b6 00 15 58 setvl r0,r21,1,0,1,0
+ 18c: b6 01 15 58 setvl r0,r21,1,0,1,1
+ 190: 76 00 15 58 setvl r0,r21,1,1,0,0
+ 194: 76 01 15 58 setvl r0,r21,1,1,0,1
+ 198: f6 00 15 58 setvl r0,r21,1,1,1,0
+ 19c: f6 01 15 58 setvl r0,r21,1,1,1,1
+ 1a0: 36 28 15 58 setvl r0,r21,21,0,0,0
+ 1a4: 36 29 15 58 setvl r0,r21,21,0,0,1
+ 1a8: b6 28 15 58 setvl r0,r21,21,0,1,0
+ 1ac: b6 29 15 58 setvl r0,r21,21,0,1,1
+ 1b0: 76 28 15 58 setvl r0,r21,21,1,0,0
+ 1b4: 76 29 15 58 setvl r0,r21,21,1,0,1
+ 1b8: f6 28 15 58 setvl r0,r21,21,1,1,0
+ 1bc: f6 29 15 58 setvl r0,r21,21,1,1,1
+ 1c0: 36 52 15 58 setvl r0,r21,42,0,0,0
+ 1c4: 36 53 15 58 setvl r0,r21,42,0,0,1
+ 1c8: b6 52 15 58 setvl r0,r21,42,0,1,0
+ 1cc: b6 53 15 58 setvl r0,r21,42,0,1,1
+ 1d0: 76 52 15 58 setvl r0,r21,42,1,0,0
+ 1d4: 76 53 15 58 setvl r0,r21,42,1,0,1
+ 1d8: f6 52 15 58 setvl r0,r21,42,1,1,0
+ 1dc: f6 53 15 58 setvl r0,r21,42,1,1,1
+ 1e0: 36 64 15 58 setvl r0,r21,51,0,0,0
+ 1e4: 36 65 15 58 setvl r0,r21,51,0,0,1
+ 1e8: b6 64 15 58 setvl r0,r21,51,0,1,0
+ 1ec: b6 65 15 58 setvl r0,r21,51,0,1,1
+ 1f0: 76 64 15 58 setvl r0,r21,51,1,0,0
+ 1f4: 76 65 15 58 setvl r0,r21,51,1,0,1
+ 1f8: f6 64 15 58 setvl r0,r21,51,1,1,0
+ 1fc: f6 65 15 58 setvl r0,r21,51,1,1,1
+ 200: 36 7c 15 58 setvl r0,r21,63,0,0,0
+ 204: 36 7d 15 58 setvl r0,r21,63,0,0,1
+ 208: b6 7c 15 58 setvl r0,r21,63,0,1,0
+ 20c: b6 7d 15 58 setvl r0,r21,63,0,1,1
+ 210: 76 7c 15 58 setvl r0,r21,63,1,0,0
+ 214: 76 7d 15 58 setvl r0,r21,63,1,0,1
+ 218: f6 7c 15 58 setvl r0,r21,63,1,1,0
+ 21c: f6 7d 15 58 setvl r0,r21,63,1,1,1
+ 220: 36 3e 15 58 setvl r0,r21,32,0,0,0
+ 224: 36 3f 15 58 setvl r0,r21,32,0,0,1
+ 228: b6 3e 15 58 setvl r0,r21,32,0,1,0
+ 22c: b6 3f 15 58 setvl r0,r21,32,0,1,1
+ 230: 76 3e 15 58 setvl r0,r21,32,1,0,0
+ 234: 76 3f 15 58 setvl r0,r21,32,1,0,1
+ 238: f6 3e 15 58 setvl r0,r21,32,1,1,0
+ 23c: f6 3f 15 58 setvl r0,r21,32,1,1,1
+ 240: 36 00 1b 58 setvl r0,r27,1,0,0,0
+ 244: 36 01 1b 58 setvl r0,r27,1,0,0,1
+ 248: b6 00 1b 58 setvl r0,r27,1,0,1,0
+ 24c: b6 01 1b 58 setvl r0,r27,1,0,1,1
+ 250: 76 00 1b 58 setvl r0,r27,1,1,0,0
+ 254: 76 01 1b 58 setvl r0,r27,1,1,0,1
+ 258: f6 00 1b 58 setvl r0,r27,1,1,1,0
+ 25c: f6 01 1b 58 setvl r0,r27,1,1,1,1
+ 260: 36 28 1b 58 setvl r0,r27,21,0,0,0
+ 264: 36 29 1b 58 setvl r0,r27,21,0,0,1
+ 268: b6 28 1b 58 setvl r0,r27,21,0,1,0
+ 26c: b6 29 1b 58 setvl r0,r27,21,0,1,1
+ 270: 76 28 1b 58 setvl r0,r27,21,1,0,0
+ 274: 76 29 1b 58 setvl r0,r27,21,1,0,1
+ 278: f6 28 1b 58 setvl r0,r27,21,1,1,0
+ 27c: f6 29 1b 58 setvl r0,r27,21,1,1,1
+ 280: 36 52 1b 58 setvl r0,r27,42,0,0,0
+ 284: 36 53 1b 58 setvl r0,r27,42,0,0,1
+ 288: b6 52 1b 58 setvl r0,r27,42,0,1,0
+ 28c: b6 53 1b 58 setvl r0,r27,42,0,1,1
+ 290: 76 52 1b 58 setvl r0,r27,42,1,0,0
+ 294: 76 53 1b 58 setvl r0,r27,42,1,0,1
+ 298: f6 52 1b 58 setvl r0,r27,42,1,1,0
+ 29c: f6 53 1b 58 setvl r0,r27,42,1,1,1
+ 2a0: 36 64 1b 58 setvl r0,r27,51,0,0,0
+ 2a4: 36 65 1b 58 setvl r0,r27,51,0,0,1
+ 2a8: b6 64 1b 58 setvl r0,r27,51,0,1,0
+ 2ac: b6 65 1b 58 setvl r0,r27,51,0,1,1
+ 2b0: 76 64 1b 58 setvl r0,r27,51,1,0,0
+ 2b4: 76 65 1b 58 setvl r0,r27,51,1,0,1
+ 2b8: f6 64 1b 58 setvl r0,r27,51,1,1,0
+ 2bc: f6 65 1b 58 setvl r0,r27,51,1,1,1
+ 2c0: 36 7c 1b 58 setvl r0,r27,63,0,0,0
+ 2c4: 36 7d 1b 58 setvl r0,r27,63,0,0,1
+ 2c8: b6 7c 1b 58 setvl r0,r27,63,0,1,0
+ 2cc: b6 7d 1b 58 setvl r0,r27,63,0,1,1
+ 2d0: 76 7c 1b 58 setvl r0,r27,63,1,0,0
+ 2d4: 76 7d 1b 58 setvl r0,r27,63,1,0,1
+ 2d8: f6 7c 1b 58 setvl r0,r27,63,1,1,0
+ 2dc: f6 7d 1b 58 setvl r0,r27,63,1,1,1
+ 2e0: 36 3e 1b 58 setvl r0,r27,32,0,0,0
+ 2e4: 36 3f 1b 58 setvl r0,r27,32,0,0,1
+ 2e8: b6 3e 1b 58 setvl r0,r27,32,0,1,0
+ 2ec: b6 3f 1b 58 setvl r0,r27,32,0,1,1
+ 2f0: 76 3e 1b 58 setvl r0,r27,32,1,0,0
+ 2f4: 76 3f 1b 58 setvl r0,r27,32,1,0,1
+ 2f8: f6 3e 1b 58 setvl r0,r27,32,1,1,0
+ 2fc: f6 3f 1b 58 setvl r0,r27,32,1,1,1
+ 300: 36 00 1f 58 setvl r0,r31,1,0,0,0
+ 304: 36 01 1f 58 setvl r0,r31,1,0,0,1
+ 308: b6 00 1f 58 setvl r0,r31,1,0,1,0
+ 30c: b6 01 1f 58 setvl r0,r31,1,0,1,1
+ 310: 76 00 1f 58 setvl r0,r31,1,1,0,0
+ 314: 76 01 1f 58 setvl r0,r31,1,1,0,1
+ 318: f6 00 1f 58 setvl r0,r31,1,1,1,0
+ 31c: f6 01 1f 58 setvl r0,r31,1,1,1,1
+ 320: 36 28 1f 58 setvl r0,r31,21,0,0,0
+ 324: 36 29 1f 58 setvl r0,r31,21,0,0,1
+ 328: b6 28 1f 58 setvl r0,r31,21,0,1,0
+ 32c: b6 29 1f 58 setvl r0,r31,21,0,1,1
+ 330: 76 28 1f 58 setvl r0,r31,21,1,0,0
+ 334: 76 29 1f 58 setvl r0,r31,21,1,0,1
+ 338: f6 28 1f 58 setvl r0,r31,21,1,1,0
+ 33c: f6 29 1f 58 setvl r0,r31,21,1,1,1
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+ 112c: b6 3f f5 5b setvl r31,r21,32,0,1,1
+ 1130: 76 3e f5 5b setvl r31,r21,32,1,0,0
+ 1134: 76 3f f5 5b setvl r31,r21,32,1,0,1
+ 1138: f6 3e f5 5b setvl r31,r21,32,1,1,0
+ 113c: f6 3f f5 5b setvl r31,r21,32,1,1,1
+ 1140: 36 00 fb 5b setvl r31,r27,1,0,0,0
+ 1144: 36 01 fb 5b setvl r31,r27,1,0,0,1
+ 1148: b6 00 fb 5b setvl r31,r27,1,0,1,0
+ 114c: b6 01 fb 5b setvl r31,r27,1,0,1,1
+ 1150: 76 00 fb 5b setvl r31,r27,1,1,0,0
+ 1154: 76 01 fb 5b setvl r31,r27,1,1,0,1
+ 1158: f6 00 fb 5b setvl r31,r27,1,1,1,0
+ 115c: f6 01 fb 5b setvl r31,r27,1,1,1,1
+ 1160: 36 28 fb 5b setvl r31,r27,21,0,0,0
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+ 1168: b6 28 fb 5b setvl r31,r27,21,0,1,0
+ 116c: b6 29 fb 5b setvl r31,r27,21,0,1,1
+ 1170: 76 28 fb 5b setvl r31,r27,21,1,0,0
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+ 1178: f6 28 fb 5b setvl r31,r27,21,1,1,0
+ 117c: f6 29 fb 5b setvl r31,r27,21,1,1,1
+ 1180: 36 52 fb 5b setvl r31,r27,42,0,0,0
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+ 1188: b6 52 fb 5b setvl r31,r27,42,0,1,0
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+ 1190: 76 52 fb 5b setvl r31,r27,42,1,0,0
+ 1194: 76 53 fb 5b setvl r31,r27,42,1,0,1
+ 1198: f6 52 fb 5b setvl r31,r27,42,1,1,0
+ 119c: f6 53 fb 5b setvl r31,r27,42,1,1,1
+ 11a0: 36 64 fb 5b setvl r31,r27,51,0,0,0
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+ 11a8: b6 64 fb 5b setvl r31,r27,51,0,1,0
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+ 11c8: b6 7c fb 5b setvl r31,r27,63,0,1,0
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+ 11d0: 76 7c fb 5b setvl r31,r27,63,1,0,0
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+ 11d8: f6 7c fb 5b setvl r31,r27,63,1,1,0
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+ 11e0: 36 3e fb 5b setvl r31,r27,32,0,0,0
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+ 11e8: b6 3e fb 5b setvl r31,r27,32,0,1,0
+ 11ec: b6 3f fb 5b setvl r31,r27,32,0,1,1
+ 11f0: 76 3e fb 5b setvl r31,r27,32,1,0,0
+ 11f4: 76 3f fb 5b setvl r31,r27,32,1,0,1
+ 11f8: f6 3e fb 5b setvl r31,r27,32,1,1,0
+ 11fc: f6 3f fb 5b setvl r31,r27,32,1,1,1
+ 1200: 36 00 ff 5b setvl r31,r31,1,0,0,0
+ 1204: 36 01 ff 5b setvl r31,r31,1,0,0,1
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+ 120c: b6 01 ff 5b setvl r31,r31,1,0,1,1
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+ 122c: b6 29 ff 5b setvl r31,r31,21,0,1,1
+ 1230: 76 28 ff 5b setvl r31,r31,21,1,0,0
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+ 1238: f6 28 ff 5b setvl r31,r31,21,1,1,0
+ 123c: f6 29 ff 5b setvl r31,r31,21,1,1,1
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+ 1248: b6 52 ff 5b setvl r31,r31,42,0,1,0
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+ 1254: 76 53 ff 5b setvl r31,r31,42,1,0,1
+ 1258: f6 52 ff 5b setvl r31,r31,42,1,1,0
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+ 1268: b6 64 ff 5b setvl r31,r31,51,0,1,0
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+ 1298: f6 7c ff 5b setvl r31,r31,63,1,1,0
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+ 12bc: f6 3f ff 5b setvl r31,r31,32,1,1,1
+ 12c0: 37 00 00 58 setvl\. r0,r0,1,0,0,0
+ 12c4: 37 01 00 58 setvl\. r0,r0,1,0,0,1
+ 12c8: b7 00 00 58 setvl\. r0,r0,1,0,1,0
+ 12cc: b7 01 00 58 setvl\. r0,r0,1,0,1,1
+ 12d0: 77 00 00 58 setvl\. r0,r0,1,1,0,0
+ 12d4: 77 01 00 58 setvl\. r0,r0,1,1,0,1
+ 12d8: f7 00 00 58 setvl\. r0,r0,1,1,1,0
+ 12dc: f7 01 00 58 setvl\. r0,r0,1,1,1,1
+ 12e0: 37 28 00 58 setvl\. r0,r0,21,0,0,0
+ 12e4: 37 29 00 58 setvl\. r0,r0,21,0,0,1
+ 12e8: b7 28 00 58 setvl\. r0,r0,21,0,1,0
+ 12ec: b7 29 00 58 setvl\. r0,r0,21,0,1,1
+ 12f0: 77 28 00 58 setvl\. r0,r0,21,1,0,0
+ 12f4: 77 29 00 58 setvl\. r0,r0,21,1,0,1
+ 12f8: f7 28 00 58 setvl\. r0,r0,21,1,1,0
+ 12fc: f7 29 00 58 setvl\. r0,r0,21,1,1,1
+ 1300: 37 52 00 58 setvl\. r0,r0,42,0,0,0
+ 1304: 37 53 00 58 setvl\. r0,r0,42,0,0,1
+ 1308: b7 52 00 58 setvl\. r0,r0,42,0,1,0
+ 130c: b7 53 00 58 setvl\. r0,r0,42,0,1,1
+ 1310: 77 52 00 58 setvl\. r0,r0,42,1,0,0
+ 1314: 77 53 00 58 setvl\. r0,r0,42,1,0,1
+ 1318: f7 52 00 58 setvl\. r0,r0,42,1,1,0
+ 131c: f7 53 00 58 setvl\. r0,r0,42,1,1,1
+ 1320: 37 64 00 58 setvl\. r0,r0,51,0,0,0
+ 1324: 37 65 00 58 setvl\. r0,r0,51,0,0,1
+ 1328: b7 64 00 58 setvl\. r0,r0,51,0,1,0
+ 132c: b7 65 00 58 setvl\. r0,r0,51,0,1,1
+ 1330: 77 64 00 58 setvl\. r0,r0,51,1,0,0
+ 1334: 77 65 00 58 setvl\. r0,r0,51,1,0,1
+ 1338: f7 64 00 58 setvl\. r0,r0,51,1,1,0
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+ 1340: 37 7c 00 58 setvl\. r0,r0,63,0,0,0
+ 1344: 37 7d 00 58 setvl\. r0,r0,63,0,0,1
+ 1348: b7 7c 00 58 setvl\. r0,r0,63,0,1,0
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+ 1350: 77 7c 00 58 setvl\. r0,r0,63,1,0,0
+ 1354: 77 7d 00 58 setvl\. r0,r0,63,1,0,1
+ 1358: f7 7c 00 58 setvl\. r0,r0,63,1,1,0
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+ 1368: b7 3e 00 58 setvl\. r0,r0,32,0,1,0
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+ 1374: 77 3f 00 58 setvl\. r0,r0,32,1,0,1
+ 1378: f7 3e 00 58 setvl\. r0,r0,32,1,1,0
+ 137c: f7 3f 00 58 setvl\. r0,r0,32,1,1,1
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+ 1384: 37 01 0a 58 setvl\. r0,r10,1,0,0,1
+ 1388: b7 00 0a 58 setvl\. r0,r10,1,0,1,0
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+ 1390: 77 00 0a 58 setvl\. r0,r10,1,1,0,0
+ 1394: 77 01 0a 58 setvl\. r0,r10,1,1,0,1
+ 1398: f7 00 0a 58 setvl\. r0,r10,1,1,1,0
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+ 13b8: f7 28 0a 58 setvl\. r0,r10,21,1,1,0
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+ 13c8: b7 52 0a 58 setvl\. r0,r10,42,0,1,0
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+ 13d8: f7 52 0a 58 setvl\. r0,r10,42,1,1,0
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+ 13e8: b7 64 0a 58 setvl\. r0,r10,51,0,1,0
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+ 1418: f7 7c 0a 58 setvl\. r0,r10,63,1,1,0
+ 141c: f7 7d 0a 58 setvl\. r0,r10,63,1,1,1
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+ 1428: b7 3e 0a 58 setvl\. r0,r10,32,0,1,0
+ 142c: b7 3f 0a 58 setvl\. r0,r10,32,0,1,1
+ 1430: 77 3e 0a 58 setvl\. r0,r10,32,1,0,0
+ 1434: 77 3f 0a 58 setvl\. r0,r10,32,1,0,1
+ 1438: f7 3e 0a 58 setvl\. r0,r10,32,1,1,0
+ 143c: f7 3f 0a 58 setvl\. r0,r10,32,1,1,1
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+ 1448: b7 00 15 58 setvl\. r0,r21,1,0,1,0
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+ 1450: 77 00 15 58 setvl\. r0,r21,1,1,0,0
+ 1454: 77 01 15 58 setvl\. r0,r21,1,1,0,1
+ 1458: f7 00 15 58 setvl\. r0,r21,1,1,1,0
+ 145c: f7 01 15 58 setvl\. r0,r21,1,1,1,1
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+ 1468: b7 28 15 58 setvl\. r0,r21,21,0,1,0
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+ 1498: f7 52 15 58 setvl\. r0,r21,42,1,1,0
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+ 14d0: 77 7c 15 58 setvl\. r0,r21,63,1,0,0
+ 14d4: 77 7d 15 58 setvl\. r0,r21,63,1,0,1
+ 14d8: f7 7c 15 58 setvl\. r0,r21,63,1,1,0
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+ 14e8: b7 3e 15 58 setvl\. r0,r21,32,0,1,0
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+ 14f0: 77 3e 15 58 setvl\. r0,r21,32,1,0,0
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+ 14f8: f7 3e 15 58 setvl\. r0,r21,32,1,1,0
+ 14fc: f7 3f 15 58 setvl\. r0,r21,32,1,1,1
+ 1500: 37 00 1b 58 setvl\. r0,r27,1,0,0,0
+ 1504: 37 01 1b 58 setvl\. r0,r27,1,0,0,1
+ 1508: b7 00 1b 58 setvl\. r0,r27,1,0,1,0
+ 150c: b7 01 1b 58 setvl\. r0,r27,1,0,1,1
+ 1510: 77 00 1b 58 setvl\. r0,r27,1,1,0,0
+ 1514: 77 01 1b 58 setvl\. r0,r27,1,1,0,1
+ 1518: f7 00 1b 58 setvl\. r0,r27,1,1,1,0
+ 151c: f7 01 1b 58 setvl\. r0,r27,1,1,1,1
+ 1520: 37 28 1b 58 setvl\. r0,r27,21,0,0,0
+ 1524: 37 29 1b 58 setvl\. r0,r27,21,0,0,1
+ 1528: b7 28 1b 58 setvl\. r0,r27,21,0,1,0
+ 152c: b7 29 1b 58 setvl\. r0,r27,21,0,1,1
+ 1530: 77 28 1b 58 setvl\. r0,r27,21,1,0,0
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+ 1538: f7 28 1b 58 setvl\. r0,r27,21,1,1,0
+ 153c: f7 29 1b 58 setvl\. r0,r27,21,1,1,1
+ 1540: 37 52 1b 58 setvl\. r0,r27,42,0,0,0
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+ 1548: b7 52 1b 58 setvl\. r0,r27,42,0,1,0
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+ 1580: 37 7c 1b 58 setvl\. r0,r27,63,0,0,0
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+ 1588: b7 7c 1b 58 setvl\. r0,r27,63,0,1,0
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+ 1590: 77 7c 1b 58 setvl\. r0,r27,63,1,0,0
+ 1594: 77 7d 1b 58 setvl\. r0,r27,63,1,0,1
+ 1598: f7 7c 1b 58 setvl\. r0,r27,63,1,1,0
+ 159c: f7 7d 1b 58 setvl\. r0,r27,63,1,1,1
+ 15a0: 37 3e 1b 58 setvl\. r0,r27,32,0,0,0
+ 15a4: 37 3f 1b 58 setvl\. r0,r27,32,0,0,1
+ 15a8: b7 3e 1b 58 setvl\. r0,r27,32,0,1,0
+ 15ac: b7 3f 1b 58 setvl\. r0,r27,32,0,1,1
+ 15b0: 77 3e 1b 58 setvl\. r0,r27,32,1,0,0
+ 15b4: 77 3f 1b 58 setvl\. r0,r27,32,1,0,1
+ 15b8: f7 3e 1b 58 setvl\. r0,r27,32,1,1,0
+ 15bc: f7 3f 1b 58 setvl\. r0,r27,32,1,1,1
+ 15c0: 37 00 1f 58 setvl\. r0,r31,1,0,0,0
+ 15c4: 37 01 1f 58 setvl\. r0,r31,1,0,0,1
+ 15c8: b7 00 1f 58 setvl\. r0,r31,1,0,1,0
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+ 2308: b7 7c ea 5b setvl\. r31,r10,63,0,1,0
+ 230c: b7 7d ea 5b setvl\. r31,r10,63,0,1,1
+ 2310: 77 7c ea 5b setvl\. r31,r10,63,1,0,0
+ 2314: 77 7d ea 5b setvl\. r31,r10,63,1,0,1
+ 2318: f7 7c ea 5b setvl\. r31,r10,63,1,1,0
+ 231c: f7 7d ea 5b setvl\. r31,r10,63,1,1,1
+ 2320: 37 3e ea 5b setvl\. r31,r10,32,0,0,0
+ 2324: 37 3f ea 5b setvl\. r31,r10,32,0,0,1
+ 2328: b7 3e ea 5b setvl\. r31,r10,32,0,1,0
+ 232c: b7 3f ea 5b setvl\. r31,r10,32,0,1,1
+ 2330: 77 3e ea 5b setvl\. r31,r10,32,1,0,0
+ 2334: 77 3f ea 5b setvl\. r31,r10,32,1,0,1
+ 2338: f7 3e ea 5b setvl\. r31,r10,32,1,1,0
+ 233c: f7 3f ea 5b setvl\. r31,r10,32,1,1,1
+ 2340: 37 00 f5 5b setvl\. r31,r21,1,0,0,0
+ 2344: 37 01 f5 5b setvl\. r31,r21,1,0,0,1
+ 2348: b7 00 f5 5b setvl\. r31,r21,1,0,1,0
+ 234c: b7 01 f5 5b setvl\. r31,r21,1,0,1,1
+ 2350: 77 00 f5 5b setvl\. r31,r21,1,1,0,0
+ 2354: 77 01 f5 5b setvl\. r31,r21,1,1,0,1
+ 2358: f7 00 f5 5b setvl\. r31,r21,1,1,1,0
+ 235c: f7 01 f5 5b setvl\. r31,r21,1,1,1,1
+ 2360: 37 28 f5 5b setvl\. r31,r21,21,0,0,0
+ 2364: 37 29 f5 5b setvl\. r31,r21,21,0,0,1
+ 2368: b7 28 f5 5b setvl\. r31,r21,21,0,1,0
+ 236c: b7 29 f5 5b setvl\. r31,r21,21,0,1,1
+ 2370: 77 28 f5 5b setvl\. r31,r21,21,1,0,0
+ 2374: 77 29 f5 5b setvl\. r31,r21,21,1,0,1
+ 2378: f7 28 f5 5b setvl\. r31,r21,21,1,1,0
+ 237c: f7 29 f5 5b setvl\. r31,r21,21,1,1,1
+ 2380: 37 52 f5 5b setvl\. r31,r21,42,0,0,0
+ 2384: 37 53 f5 5b setvl\. r31,r21,42,0,0,1
+ 2388: b7 52 f5 5b setvl\. r31,r21,42,0,1,0
+ 238c: b7 53 f5 5b setvl\. r31,r21,42,0,1,1
+ 2390: 77 52 f5 5b setvl\. r31,r21,42,1,0,0
+ 2394: 77 53 f5 5b setvl\. r31,r21,42,1,0,1
+ 2398: f7 52 f5 5b setvl\. r31,r21,42,1,1,0
+ 239c: f7 53 f5 5b setvl\. r31,r21,42,1,1,1
+ 23a0: 37 64 f5 5b setvl\. r31,r21,51,0,0,0
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+ 23a8: b7 64 f5 5b setvl\. r31,r21,51,0,1,0
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+ 23b0: 77 64 f5 5b setvl\. r31,r21,51,1,0,0
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+ 23b8: f7 64 f5 5b setvl\. r31,r21,51,1,1,0
+ 23bc: f7 65 f5 5b setvl\. r31,r21,51,1,1,1
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+ 23d4: 77 7d f5 5b setvl\. r31,r21,63,1,0,1
+ 23d8: f7 7c f5 5b setvl\. r31,r21,63,1,1,0
+ 23dc: f7 7d f5 5b setvl\. r31,r21,63,1,1,1
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+ 23e8: b7 3e f5 5b setvl\. r31,r21,32,0,1,0
+ 23ec: b7 3f f5 5b setvl\. r31,r21,32,0,1,1
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+ 23f8: f7 3e f5 5b setvl\. r31,r21,32,1,1,0
+ 23fc: f7 3f f5 5b setvl\. r31,r21,32,1,1,1
+ 2400: 37 00 fb 5b setvl\. r31,r27,1,0,0,0
+ 2404: 37 01 fb 5b setvl\. r31,r27,1,0,0,1
+ 2408: b7 00 fb 5b setvl\. r31,r27,1,0,1,0
+ 240c: b7 01 fb 5b setvl\. r31,r27,1,0,1,1
+ 2410: 77 00 fb 5b setvl\. r31,r27,1,1,0,0
+ 2414: 77 01 fb 5b setvl\. r31,r27,1,1,0,1
+ 2418: f7 00 fb 5b setvl\. r31,r27,1,1,1,0
+ 241c: f7 01 fb 5b setvl\. r31,r27,1,1,1,1
+ 2420: 37 28 fb 5b setvl\. r31,r27,21,0,0,0
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+ 2428: b7 28 fb 5b setvl\. r31,r27,21,0,1,0
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+ 2438: f7 28 fb 5b setvl\. r31,r27,21,1,1,0
+ 243c: f7 29 fb 5b setvl\. r31,r27,21,1,1,1
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+ 2458: f7 52 fb 5b setvl\. r31,r27,42,1,1,0
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+ 2468: b7 64 fb 5b setvl\. r31,r27,51,0,1,0
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+ 2488: b7 7c fb 5b setvl\. r31,r27,63,0,1,0
+ 248c: b7 7d fb 5b setvl\. r31,r27,63,0,1,1
+ 2490: 77 7c fb 5b setvl\. r31,r27,63,1,0,0
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+ 2498: f7 7c fb 5b setvl\. r31,r27,63,1,1,0
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+ 24c0: 37 00 ff 5b setvl\. r31,r31,1,0,0,0
+ 24c4: 37 01 ff 5b setvl\. r31,r31,1,0,0,1
+ 24c8: b7 00 ff 5b setvl\. r31,r31,1,0,1,0
+ 24cc: b7 01 ff 5b setvl\. r31,r31,1,0,1,1
+ 24d0: 77 00 ff 5b setvl\. r31,r31,1,1,0,0
+ 24d4: 77 01 ff 5b setvl\. r31,r31,1,1,0,1
+ 24d8: f7 00 ff 5b setvl\. r31,r31,1,1,1,0
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+ 24f8: f7 28 ff 5b setvl\. r31,r31,21,1,1,0
+ 24fc: f7 29 ff 5b setvl\. r31,r31,21,1,1,1
+ 2500: 37 52 ff 5b setvl\. r31,r31,42,0,0,0
+ 2504: 37 53 ff 5b setvl\. r31,r31,42,0,0,1
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+ 253c: f7 65 ff 5b setvl\. r31,r31,51,1,1,1
+ 2540: 37 7c ff 5b setvl\. r31,r31,63,0,0,0
+ 2544: 37 7d ff 5b setvl\. r31,r31,63,0,0,1
+ 2548: b7 7c ff 5b setvl\. r31,r31,63,0,1,0
+ 254c: b7 7d ff 5b setvl\. r31,r31,63,0,1,1
+ 2550: 77 7c ff 5b setvl\. r31,r31,63,1,0,0
+ 2554: 77 7d ff 5b setvl\. r31,r31,63,1,0,1
+ 2558: f7 7c ff 5b setvl\. r31,r31,63,1,1,0
+ 255c: f7 7d ff 5b setvl\. r31,r31,63,1,1,1
+ 2560: 37 3e ff 5b setvl\. r31,r31,32,0,0,0
+ 2564: 37 3f ff 5b setvl\. r31,r31,32,0,0,1
+ 2568: b7 3e ff 5b setvl\. r31,r31,32,0,1,0
+ 256c: b7 3f ff 5b setvl\. r31,r31,32,0,1,1
+ 2570: 77 3e ff 5b setvl\. r31,r31,32,1,0,0
+ 2574: 77 3f ff 5b setvl\. r31,r31,32,1,0,1
+ 2578: f7 3e ff 5b setvl\. r31,r31,32,1,1,0
+ 257c: f7 3f ff 5b setvl\. r31,r31,32,1,1,1
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..944f8afc08
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,2400 @@
+setvl 0,0,1,0,0,0
+setvl 0,0,1,0,0,1
+setvl 0,0,1,0,1,0
+setvl 0,0,1,0,1,1
+setvl 0,0,1,1,0,0
+setvl 0,0,1,1,0,1
+setvl 0,0,1,1,1,0
+setvl 0,0,1,1,1,1
+setvl 0,0,21,0,0,0
+setvl 0,0,21,0,0,1
+setvl 0,0,21,0,1,0
+setvl 0,0,21,0,1,1
+setvl 0,0,21,1,0,0
+setvl 0,0,21,1,0,1
+setvl 0,0,21,1,1,0
+setvl 0,0,21,1,1,1
+setvl 0,0,42,0,0,0
+setvl 0,0,42,0,0,1
+setvl 0,0,42,0,1,0
+setvl 0,0,42,0,1,1
+setvl 0,0,42,1,0,0
+setvl 0,0,42,1,0,1
+setvl 0,0,42,1,1,0
+setvl 0,0,42,1,1,1
+setvl 0,0,51,0,0,0
+setvl 0,0,51,0,0,1
+setvl 0,0,51,0,1,0
+setvl 0,0,51,0,1,1
+setvl 0,0,51,1,0,0
+setvl 0,0,51,1,0,1
+setvl 0,0,51,1,1,0
+setvl 0,0,51,1,1,1
+setvl 0,0,63,0,0,0
+setvl 0,0,63,0,0,1
+setvl 0,0,63,0,1,0
+setvl 0,0,63,0,1,1
+setvl 0,0,63,1,0,0
+setvl 0,0,63,1,0,1
+setvl 0,0,63,1,1,0
+setvl 0,0,63,1,1,1
+setvl 0,0,32,0,0,0
+setvl 0,0,32,0,0,1
+setvl 0,0,32,0,1,0
+setvl 0,0,32,0,1,1
+setvl 0,0,32,1,0,0
+setvl 0,0,32,1,0,1
+setvl 0,0,32,1,1,0
+setvl 0,0,32,1,1,1
+setvl 0,10,1,0,0,0
+setvl 0,10,1,0,0,1
+setvl 0,10,1,0,1,0
+setvl 0,10,1,0,1,1
+setvl 0,10,1,1,0,0
+setvl 0,10,1,1,0,1
+setvl 0,10,1,1,1,0
+setvl 0,10,1,1,1,1
+setvl 0,10,21,0,0,0
+setvl 0,10,21,0,0,1
+setvl 0,10,21,0,1,0
+setvl 0,10,21,0,1,1
+setvl 0,10,21,1,0,0
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+setvl 0,10,42,0,0,0
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+setvl 0,10,42,0,1,1
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+setvl 0,10,42,1,0,1
+setvl 0,10,42,1,1,0
+setvl 0,10,42,1,1,1
+setvl 0,10,51,0,0,0
+setvl 0,10,51,0,0,1
+setvl 0,10,51,0,1,0
+setvl 0,10,51,0,1,1
+setvl 0,10,51,1,0,0
+setvl 0,10,51,1,0,1
+setvl 0,10,51,1,1,0
+setvl 0,10,51,1,1,1
+setvl 0,10,63,0,0,0
+setvl 0,10,63,0,0,1
+setvl 0,10,63,0,1,0
+setvl 0,10,63,0,1,1
+setvl 0,10,63,1,0,0
+setvl 0,10,63,1,0,1
+setvl 0,10,63,1,1,0
+setvl 0,10,63,1,1,1
+setvl 0,10,32,0,0,0
+setvl 0,10,32,0,0,1
+setvl 0,10,32,0,1,0
+setvl 0,10,32,0,1,1
+setvl 0,10,32,1,0,0
+setvl 0,10,32,1,0,1
+setvl 0,10,32,1,1,0
+setvl 0,10,32,1,1,1
+setvl 0,21,1,0,0,0
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+setvl 0,21,1,0,1,0
+setvl 0,21,1,0,1,1
+setvl 0,21,1,1,0,0
+setvl 0,21,1,1,0,1
+setvl 0,21,1,1,1,0
+setvl 0,21,1,1,1,1
+setvl 0,21,21,0,0,0
+setvl 0,21,21,0,0,1
+setvl 0,21,21,0,1,0
+setvl 0,21,21,0,1,1
+setvl 0,21,21,1,0,0
+setvl 0,21,21,1,0,1
+setvl 0,21,21,1,1,0
+setvl 0,21,21,1,1,1
+setvl 0,21,42,0,0,0
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+setvl 0,21,42,0,1,0
+setvl 0,21,42,0,1,1
+setvl 0,21,42,1,0,0
+setvl 0,21,42,1,0,1
+setvl 0,21,42,1,1,0
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+setvl 0,21,51,0,0,0
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+setvl 0,21,51,0,1,0
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+setvl 0,21,51,1,0,0
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+setvl 0,21,63,0,0,0
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+setvl 0,21,32,0,0,0
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+setvl 0,27,1,0,0,0
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+setvl 0,27,51,0,0,0
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+setvl 0,27,63,0,0,0
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+setvl 0,27,63,1,0,0
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+setvl 0,27,63,1,1,0
+setvl 0,27,63,1,1,1
+setvl 0,27,32,0,0,0
+setvl 0,27,32,0,0,1
+setvl 0,27,32,0,1,0
+setvl 0,27,32,0,1,1
+setvl 0,27,32,1,0,0
+setvl 0,27,32,1,0,1
+setvl 0,27,32,1,1,0
+setvl 0,27,32,1,1,1
+setvl 0,31,1,0,0,0
+setvl 0,31,1,0,0,1
+setvl 0,31,1,0,1,0
+setvl 0,31,1,0,1,1
+setvl 0,31,1,1,0,0
+setvl 0,31,1,1,0,1
+setvl 0,31,1,1,1,0
+setvl 0,31,1,1,1,1
+setvl 0,31,21,0,0,0
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+setvl 0,31,21,0,1,0
+setvl 0,31,21,0,1,1
+setvl 0,31,21,1,0,0
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+setvl 0,31,21,1,1,0
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+setvl 0,31,42,0,0,0
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+setvl 0,31,51,0,0,0
+setvl 0,31,51,0,0,1
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+setvl. 31,0,63,0,0,1
+setvl. 31,0,63,0,1,0
+setvl. 31,0,63,0,1,1
+setvl. 31,0,63,1,0,0
+setvl. 31,0,63,1,0,1
+setvl. 31,0,63,1,1,0
+setvl. 31,0,63,1,1,1
+setvl. 31,0,32,0,0,0
+setvl. 31,0,32,0,0,1
+setvl. 31,0,32,0,1,0
+setvl. 31,0,32,0,1,1
+setvl. 31,0,32,1,0,0
+setvl. 31,0,32,1,0,1
+setvl. 31,0,32,1,1,0
+setvl. 31,0,32,1,1,1
+setvl. 31,10,1,0,0,0
+setvl. 31,10,1,0,0,1
+setvl. 31,10,1,0,1,0
+setvl. 31,10,1,0,1,1
+setvl. 31,10,1,1,0,0
+setvl. 31,10,1,1,0,1
+setvl. 31,10,1,1,1,0
+setvl. 31,10,1,1,1,1
+setvl. 31,10,21,0,0,0
+setvl. 31,10,21,0,0,1
+setvl. 31,10,21,0,1,0
+setvl. 31,10,21,0,1,1
+setvl. 31,10,21,1,0,0
+setvl. 31,10,21,1,0,1
+setvl. 31,10,21,1,1,0
+setvl. 31,10,21,1,1,1
+setvl. 31,10,42,0,0,0
+setvl. 31,10,42,0,0,1
+setvl. 31,10,42,0,1,0
+setvl. 31,10,42,0,1,1
+setvl. 31,10,42,1,0,0
+setvl. 31,10,42,1,0,1
+setvl. 31,10,42,1,1,0
+setvl. 31,10,42,1,1,1
+setvl. 31,10,51,0,0,0
+setvl. 31,10,51,0,0,1
+setvl. 31,10,51,0,1,0
+setvl. 31,10,51,0,1,1
+setvl. 31,10,51,1,0,0
+setvl. 31,10,51,1,0,1
+setvl. 31,10,51,1,1,0
+setvl. 31,10,51,1,1,1
+setvl. 31,10,63,0,0,0
+setvl. 31,10,63,0,0,1
+setvl. 31,10,63,0,1,0
+setvl. 31,10,63,0,1,1
+setvl. 31,10,63,1,0,0
+setvl. 31,10,63,1,0,1
+setvl. 31,10,63,1,1,0
+setvl. 31,10,63,1,1,1
+setvl. 31,10,32,0,0,0
+setvl. 31,10,32,0,0,1
+setvl. 31,10,32,0,1,0
+setvl. 31,10,32,0,1,1
+setvl. 31,10,32,1,0,0
+setvl. 31,10,32,1,0,1
+setvl. 31,10,32,1,1,0
+setvl. 31,10,32,1,1,1
+setvl. 31,21,1,0,0,0
+setvl. 31,21,1,0,0,1
+setvl. 31,21,1,0,1,0
+setvl. 31,21,1,0,1,1
+setvl. 31,21,1,1,0,0
+setvl. 31,21,1,1,0,1
+setvl. 31,21,1,1,1,0
+setvl. 31,21,1,1,1,1
+setvl. 31,21,21,0,0,0
+setvl. 31,21,21,0,0,1
+setvl. 31,21,21,0,1,0
+setvl. 31,21,21,0,1,1
+setvl. 31,21,21,1,0,0
+setvl. 31,21,21,1,0,1
+setvl. 31,21,21,1,1,0
+setvl. 31,21,21,1,1,1
+setvl. 31,21,42,0,0,0
+setvl. 31,21,42,0,0,1
+setvl. 31,21,42,0,1,0
+setvl. 31,21,42,0,1,1
+setvl. 31,21,42,1,0,0
+setvl. 31,21,42,1,0,1
+setvl. 31,21,42,1,1,0
+setvl. 31,21,42,1,1,1
+setvl. 31,21,51,0,0,0
+setvl. 31,21,51,0,0,1
+setvl. 31,21,51,0,1,0
+setvl. 31,21,51,0,1,1
+setvl. 31,21,51,1,0,0
+setvl. 31,21,51,1,0,1
+setvl. 31,21,51,1,1,0
+setvl. 31,21,51,1,1,1
+setvl. 31,21,63,0,0,0
+setvl. 31,21,63,0,0,1
+setvl. 31,21,63,0,1,0
+setvl. 31,21,63,0,1,1
+setvl. 31,21,63,1,0,0
+setvl. 31,21,63,1,0,1
+setvl. 31,21,63,1,1,0
+setvl. 31,21,63,1,1,1
+setvl. 31,21,32,0,0,0
+setvl. 31,21,32,0,0,1
+setvl. 31,21,32,0,1,0
+setvl. 31,21,32,0,1,1
+setvl. 31,21,32,1,0,0
+setvl. 31,21,32,1,0,1
+setvl. 31,21,32,1,1,0
+setvl. 31,21,32,1,1,1
+setvl. 31,27,1,0,0,0
+setvl. 31,27,1,0,0,1
+setvl. 31,27,1,0,1,0
+setvl. 31,27,1,0,1,1
+setvl. 31,27,1,1,0,0
+setvl. 31,27,1,1,0,1
+setvl. 31,27,1,1,1,0
+setvl. 31,27,1,1,1,1
+setvl. 31,27,21,0,0,0
+setvl. 31,27,21,0,0,1
+setvl. 31,27,21,0,1,0
+setvl. 31,27,21,0,1,1
+setvl. 31,27,21,1,0,0
+setvl. 31,27,21,1,0,1
+setvl. 31,27,21,1,1,0
+setvl. 31,27,21,1,1,1
+setvl. 31,27,42,0,0,0
+setvl. 31,27,42,0,0,1
+setvl. 31,27,42,0,1,0
+setvl. 31,27,42,0,1,1
+setvl. 31,27,42,1,0,0
+setvl. 31,27,42,1,0,1
+setvl. 31,27,42,1,1,0
+setvl. 31,27,42,1,1,1
+setvl. 31,27,51,0,0,0
+setvl. 31,27,51,0,0,1
+setvl. 31,27,51,0,1,0
+setvl. 31,27,51,0,1,1
+setvl. 31,27,51,1,0,0
+setvl. 31,27,51,1,0,1
+setvl. 31,27,51,1,1,0
+setvl. 31,27,51,1,1,1
+setvl. 31,27,63,0,0,0
+setvl. 31,27,63,0,0,1
+setvl. 31,27,63,0,1,0
+setvl. 31,27,63,0,1,1
+setvl. 31,27,63,1,0,0
+setvl. 31,27,63,1,0,1
+setvl. 31,27,63,1,1,0
+setvl. 31,27,63,1,1,1
+setvl. 31,27,32,0,0,0
+setvl. 31,27,32,0,0,1
+setvl. 31,27,32,0,1,0
+setvl. 31,27,32,0,1,1
+setvl. 31,27,32,1,0,0
+setvl. 31,27,32,1,0,1
+setvl. 31,27,32,1,1,0
+setvl. 31,27,32,1,1,1
+setvl. 31,31,1,0,0,0
+setvl. 31,31,1,0,0,1
+setvl. 31,31,1,0,1,0
+setvl. 31,31,1,0,1,1
+setvl. 31,31,1,1,0,0
+setvl. 31,31,1,1,0,1
+setvl. 31,31,1,1,1,0
+setvl. 31,31,1,1,1,1
+setvl. 31,31,21,0,0,0
+setvl. 31,31,21,0,0,1
+setvl. 31,31,21,0,1,0
+setvl. 31,31,21,0,1,1
+setvl. 31,31,21,1,0,0
+setvl. 31,31,21,1,0,1
+setvl. 31,31,21,1,1,0
+setvl. 31,31,21,1,1,1
+setvl. 31,31,42,0,0,0
+setvl. 31,31,42,0,0,1
+setvl. 31,31,42,0,1,0
+setvl. 31,31,42,0,1,1
+setvl. 31,31,42,1,0,0
+setvl. 31,31,42,1,0,1
+setvl. 31,31,42,1,1,0
+setvl. 31,31,42,1,1,1
+setvl. 31,31,51,0,0,0
+setvl. 31,31,51,0,0,1
+setvl. 31,31,51,0,1,0
+setvl. 31,31,51,0,1,1
+setvl. 31,31,51,1,0,0
+setvl. 31,31,51,1,0,1
+setvl. 31,31,51,1,1,0
+setvl. 31,31,51,1,1,1
+setvl. 31,31,63,0,0,0
+setvl. 31,31,63,0,0,1
+setvl. 31,31,63,0,1,0
+setvl. 31,31,63,0,1,1
+setvl. 31,31,63,1,0,0
+setvl. 31,31,63,1,0,1
+setvl. 31,31,63,1,1,0
+setvl. 31,31,63,1,1,1
+setvl. 31,31,32,0,0,0
+setvl. 31,31,32,0,0,1
+setvl. 31,31,32,0,1,0
+setvl. 31,31,32,0,1,1
+setvl. 31,31,32,1,0,0
+setvl. 31,31,32,1,0,1
+setvl. 31,31,32,1,1,0
+setvl. 31,31,32,1,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d..0a34417820 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,26 @@ extract_thds (uint64_t insn,
return value;
}
+
+static uint64_t
+insert_svi (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value <= 0)
+ *errmsg = _("invalid SVi field");
+ return (insn | (((value - 1) & 0x3f) << 9));
+}
+
+static int64_t
+extract_svi (uint64_t insn ATTRIBUTE_UNUSED,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> 9) & 0x3f) + 1);
+}
+
\f
/* The operands table.
@@ -3825,6 +3845,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, insert_svi, extract_svi, 0 },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4726,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6763,6 +6802,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH 3/5] ppc/svp64: support svstep instructions
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-06-17 19:08 ` Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
` (2 subsequent siblings)
5 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-17 19:08 UTC (permalink / raw)
To: binutils; +Cc: amodra, luke.leighton, Dmitry Selyutin
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svstep.d | 128 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svstep.s | 120 +++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 3 +
4 files changed, 252 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cd4dd658ce..d4d06d587e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -155,3 +155,4 @@ run_dump_test "pr27676"
run_dump_test "raw"
run_dump_test "setvl"
+run_dump_test "svstep"
diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644
index 0000000000..772d7857e7
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,128 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 26 00 00 58 svstep r0,1,0
+ 4: 66 00 00 58 svstep r0,1,1
+ 8: 26 28 00 58 svstep r0,21,0
+ c: 66 28 00 58 svstep r0,21,1
+ 10: 26 52 00 58 svstep r0,42,0
+ 14: 66 52 00 58 svstep r0,42,1
+ 18: 26 64 00 58 svstep r0,51,0
+ 1c: 66 64 00 58 svstep r0,51,1
+ 20: 26 7c 00 58 svstep r0,63,0
+ 24: 66 7c 00 58 svstep r0,63,1
+ 28: 26 3e 00 58 svstep r0,32,0
+ 2c: 66 3e 00 58 svstep r0,32,1
+ 30: 26 00 40 59 svstep r10,1,0
+ 34: 66 00 40 59 svstep r10,1,1
+ 38: 26 28 40 59 svstep r10,21,0
+ 3c: 66 28 40 59 svstep r10,21,1
+ 40: 26 52 40 59 svstep r10,42,0
+ 44: 66 52 40 59 svstep r10,42,1
+ 48: 26 64 40 59 svstep r10,51,0
+ 4c: 66 64 40 59 svstep r10,51,1
+ 50: 26 7c 40 59 svstep r10,63,0
+ 54: 66 7c 40 59 svstep r10,63,1
+ 58: 26 3e 40 59 svstep r10,32,0
+ 5c: 66 3e 40 59 svstep r10,32,1
+ 60: 26 00 a0 5a svstep r21,1,0
+ 64: 66 00 a0 5a svstep r21,1,1
+ 68: 26 28 a0 5a svstep r21,21,0
+ 6c: 66 28 a0 5a svstep r21,21,1
+ 70: 26 52 a0 5a svstep r21,42,0
+ 74: 66 52 a0 5a svstep r21,42,1
+ 78: 26 64 a0 5a svstep r21,51,0
+ 7c: 66 64 a0 5a svstep r21,51,1
+ 80: 26 7c a0 5a svstep r21,63,0
+ 84: 66 7c a0 5a svstep r21,63,1
+ 88: 26 3e a0 5a svstep r21,32,0
+ 8c: 66 3e a0 5a svstep r21,32,1
+ 90: 26 00 60 5b svstep r27,1,0
+ 94: 66 00 60 5b svstep r27,1,1
+ 98: 26 28 60 5b svstep r27,21,0
+ 9c: 66 28 60 5b svstep r27,21,1
+ a0: 26 52 60 5b svstep r27,42,0
+ a4: 66 52 60 5b svstep r27,42,1
+ a8: 26 64 60 5b svstep r27,51,0
+ ac: 66 64 60 5b svstep r27,51,1
+ b0: 26 7c 60 5b svstep r27,63,0
+ b4: 66 7c 60 5b svstep r27,63,1
+ b8: 26 3e 60 5b svstep r27,32,0
+ bc: 66 3e 60 5b svstep r27,32,1
+ c0: 26 00 e0 5b svstep r31,1,0
+ c4: 66 00 e0 5b svstep r31,1,1
+ c8: 26 28 e0 5b svstep r31,21,0
+ cc: 66 28 e0 5b svstep r31,21,1
+ d0: 26 52 e0 5b svstep r31,42,0
+ d4: 66 52 e0 5b svstep r31,42,1
+ d8: 26 64 e0 5b svstep r31,51,0
+ dc: 66 64 e0 5b svstep r31,51,1
+ e0: 26 7c e0 5b svstep r31,63,0
+ e4: 66 7c e0 5b svstep r31,63,1
+ e8: 26 3e e0 5b svstep r31,32,0
+ ec: 66 3e e0 5b svstep r31,32,1
+ f0: 27 00 00 58 svstep\. r0,1,0
+ f4: 67 00 00 58 svstep\. r0,1,1
+ f8: 27 28 00 58 svstep\. r0,21,0
+ fc: 67 28 00 58 svstep\. r0,21,1
+ 100: 27 52 00 58 svstep\. r0,42,0
+ 104: 67 52 00 58 svstep\. r0,42,1
+ 108: 27 64 00 58 svstep\. r0,51,0
+ 10c: 67 64 00 58 svstep\. r0,51,1
+ 110: 27 7c 00 58 svstep\. r0,63,0
+ 114: 67 7c 00 58 svstep\. r0,63,1
+ 118: 27 3e 00 58 svstep\. r0,32,0
+ 11c: 67 3e 00 58 svstep\. r0,32,1
+ 120: 27 00 40 59 svstep\. r10,1,0
+ 124: 67 00 40 59 svstep\. r10,1,1
+ 128: 27 28 40 59 svstep\. r10,21,0
+ 12c: 67 28 40 59 svstep\. r10,21,1
+ 130: 27 52 40 59 svstep\. r10,42,0
+ 134: 67 52 40 59 svstep\. r10,42,1
+ 138: 27 64 40 59 svstep\. r10,51,0
+ 13c: 67 64 40 59 svstep\. r10,51,1
+ 140: 27 7c 40 59 svstep\. r10,63,0
+ 144: 67 7c 40 59 svstep\. r10,63,1
+ 148: 27 3e 40 59 svstep\. r10,32,0
+ 14c: 67 3e 40 59 svstep\. r10,32,1
+ 150: 27 00 a0 5a svstep\. r21,1,0
+ 154: 67 00 a0 5a svstep\. r21,1,1
+ 158: 27 28 a0 5a svstep\. r21,21,0
+ 15c: 67 28 a0 5a svstep\. r21,21,1
+ 160: 27 52 a0 5a svstep\. r21,42,0
+ 164: 67 52 a0 5a svstep\. r21,42,1
+ 168: 27 64 a0 5a svstep\. r21,51,0
+ 16c: 67 64 a0 5a svstep\. r21,51,1
+ 170: 27 7c a0 5a svstep\. r21,63,0
+ 174: 67 7c a0 5a svstep\. r21,63,1
+ 178: 27 3e a0 5a svstep\. r21,32,0
+ 17c: 67 3e a0 5a svstep\. r21,32,1
+ 180: 27 00 60 5b svstep\. r27,1,0
+ 184: 67 00 60 5b svstep\. r27,1,1
+ 188: 27 28 60 5b svstep\. r27,21,0
+ 18c: 67 28 60 5b svstep\. r27,21,1
+ 190: 27 52 60 5b svstep\. r27,42,0
+ 194: 67 52 60 5b svstep\. r27,42,1
+ 198: 27 64 60 5b svstep\. r27,51,0
+ 19c: 67 64 60 5b svstep\. r27,51,1
+ 1a0: 27 7c 60 5b svstep\. r27,63,0
+ 1a4: 67 7c 60 5b svstep\. r27,63,1
+ 1a8: 27 3e 60 5b svstep\. r27,32,0
+ 1ac: 67 3e 60 5b svstep\. r27,32,1
+ 1b0: 27 00 e0 5b svstep\. r31,1,0
+ 1b4: 67 00 e0 5b svstep\. r31,1,1
+ 1b8: 27 28 e0 5b svstep\. r31,21,0
+ 1bc: 67 28 e0 5b svstep\. r31,21,1
+ 1c0: 27 52 e0 5b svstep\. r31,42,0
+ 1c4: 67 52 e0 5b svstep\. r31,42,1
+ 1c8: 27 64 e0 5b svstep\. r31,51,0
+ 1cc: 67 64 e0 5b svstep\. r31,51,1
+ 1d0: 27 7c e0 5b svstep\. r31,63,0
+ 1d4: 67 7c e0 5b svstep\. r31,63,1
+ 1d8: 27 3e e0 5b svstep\. r31,32,0
+ 1dc: 67 3e e0 5b svstep\. r31,32,1
diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644
index 0000000000..f41547ad63
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,120 @@
+svstep 0,1,0
+svstep 0,1,1
+svstep 0,21,0
+svstep 0,21,1
+svstep 0,42,0
+svstep 0,42,1
+svstep 0,51,0
+svstep 0,51,1
+svstep 0,63,0
+svstep 0,63,1
+svstep 0,32,0
+svstep 0,32,1
+svstep 10,1,0
+svstep 10,1,1
+svstep 10,21,0
+svstep 10,21,1
+svstep 10,42,0
+svstep 10,42,1
+svstep 10,51,0
+svstep 10,51,1
+svstep 10,63,0
+svstep 10,63,1
+svstep 10,32,0
+svstep 10,32,1
+svstep 21,1,0
+svstep 21,1,1
+svstep 21,21,0
+svstep 21,21,1
+svstep 21,42,0
+svstep 21,42,1
+svstep 21,51,0
+svstep 21,51,1
+svstep 21,63,0
+svstep 21,63,1
+svstep 21,32,0
+svstep 21,32,1
+svstep 27,1,0
+svstep 27,1,1
+svstep 27,21,0
+svstep 27,21,1
+svstep 27,42,0
+svstep 27,42,1
+svstep 27,51,0
+svstep 27,51,1
+svstep 27,63,0
+svstep 27,63,1
+svstep 27,32,0
+svstep 27,32,1
+svstep 31,1,0
+svstep 31,1,1
+svstep 31,21,0
+svstep 31,21,1
+svstep 31,42,0
+svstep 31,42,1
+svstep 31,51,0
+svstep 31,51,1
+svstep 31,63,0
+svstep 31,63,1
+svstep 31,32,0
+svstep 31,32,1
+svstep. 0,1,0
+svstep. 0,1,1
+svstep. 0,21,0
+svstep. 0,21,1
+svstep. 0,42,0
+svstep. 0,42,1
+svstep. 0,51,0
+svstep. 0,51,1
+svstep. 0,63,0
+svstep. 0,63,1
+svstep. 0,32,0
+svstep. 0,32,1
+svstep. 10,1,0
+svstep. 10,1,1
+svstep. 10,21,0
+svstep. 10,21,1
+svstep. 10,42,0
+svstep. 10,42,1
+svstep. 10,51,0
+svstep. 10,51,1
+svstep. 10,63,0
+svstep. 10,63,1
+svstep. 10,32,0
+svstep. 10,32,1
+svstep. 21,1,0
+svstep. 21,1,1
+svstep. 21,21,0
+svstep. 21,21,1
+svstep. 21,42,0
+svstep. 21,42,1
+svstep. 21,51,0
+svstep. 21,51,1
+svstep. 21,63,0
+svstep. 21,63,1
+svstep. 21,32,0
+svstep. 21,32,1
+svstep. 27,1,0
+svstep. 27,1,1
+svstep. 27,21,0
+svstep. 27,21,1
+svstep. 27,42,0
+svstep. 27,42,1
+svstep. 27,51,0
+svstep. 27,51,1
+svstep. 27,63,0
+svstep. 27,63,1
+svstep. 27,32,0
+svstep. 27,32,1
+svstep. 31,1,0
+svstep. 31,1,1
+svstep. 31,21,0
+svstep. 31,21,1
+svstep. 31,42,0
+svstep. 31,42,1
+svstep. 31,51,0
+svstep. 31,51,1
+svstep. 31,63,0
+svstep. 31,63,1
+svstep. 31,32,0
+svstep. 31,32,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 0a34417820..b053a15125 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6802,6 +6802,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH 4/5] ppc/svp64: support svshape instruction
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (2 preceding siblings ...)
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
@ 2022-06-17 19:08 ` Dmitry Selyutin
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
5 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-17 19:08 UTC (permalink / raw)
To: binutils; +Cc: amodra, luke.leighton, Dmitry Selyutin
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svshape.d | 1736 +++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svshape.s | 1728 ++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 93 ++
4 files changed, 3558 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d4d06d587e..04082439bb 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..e78784bed1
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,1736 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 19 00 00 58 svshape 1,1,1,0,0
+ 4: 59 00 00 58 svshape 1,1,1,0,1
+ 8: 99 02 00 58 svshape 1,1,1,5,0
+ c: d9 02 00 58 svshape 1,1,1,5,1
+ 10: 19 05 00 58 svshape 1,1,1,10,0
+ 14: 59 05 00 58 svshape 1,1,1,10,1
+ 18: 99 07 00 58 svshape 1,1,1,15,0
+ 1c: d9 07 00 58 svshape 1,1,1,15,1
+ 20: 19 48 00 58 svshape 1,1,10,0,0
+ 24: 59 48 00 58 svshape 1,1,10,0,1
+ 28: 99 4a 00 58 svshape 1,1,10,5,0
+ 2c: d9 4a 00 58 svshape 1,1,10,5,1
+ 30: 19 4d 00 58 svshape 1,1,10,10,0
+ 34: 59 4d 00 58 svshape 1,1,10,10,1
+ 38: 99 4f 00 58 svshape 1,1,10,15,0
+ 3c: d9 4f 00 58 svshape 1,1,10,15,1
+ 40: 19 a0 00 58 svshape 1,1,21,0,0
+ 44: 59 a0 00 58 svshape 1,1,21,0,1
+ 48: 99 a2 00 58 svshape 1,1,21,5,0
+ 4c: d9 a2 00 58 svshape 1,1,21,5,1
+ 50: 19 a5 00 58 svshape 1,1,21,10,0
+ 54: 59 a5 00 58 svshape 1,1,21,10,1
+ 58: 99 a7 00 58 svshape 1,1,21,15,0
+ 5c: d9 a7 00 58 svshape 1,1,21,15,1
+ 60: 19 d0 00 58 svshape 1,1,27,0,0
+ 64: 59 d0 00 58 svshape 1,1,27,0,1
+ 68: 99 d2 00 58 svshape 1,1,27,5,0
+ 6c: d9 d2 00 58 svshape 1,1,27,5,1
+ 70: 19 d5 00 58 svshape 1,1,27,10,0
+ 74: 59 d5 00 58 svshape 1,1,27,10,1
+ 78: 99 d7 00 58 svshape 1,1,27,15,0
+ 7c: d9 d7 00 58 svshape 1,1,27,15,1
+ 80: 19 f0 00 58 svshape 1,1,31,0,0
+ 84: 59 f0 00 58 svshape 1,1,31,0,1
+ 88: 99 f2 00 58 svshape 1,1,31,5,0
+ 8c: d9 f2 00 58 svshape 1,1,31,5,1
+ 90: 19 f5 00 58 svshape 1,1,31,10,0
+ 94: 59 f5 00 58 svshape 1,1,31,10,1
+ 98: 99 f7 00 58 svshape 1,1,31,15,0
+ 9c: d9 f7 00 58 svshape 1,1,31,15,1
+ a0: 19 78 00 58 svshape 1,1,16,0,0
+ a4: 59 78 00 58 svshape 1,1,16,0,1
+ a8: 99 7a 00 58 svshape 1,1,16,5,0
+ ac: d9 7a 00 58 svshape 1,1,16,5,1
+ b0: 19 7d 00 58 svshape 1,1,16,10,0
+ b4: 59 7d 00 58 svshape 1,1,16,10,1
+ b8: 99 7f 00 58 svshape 1,1,16,15,0
+ bc: d9 7f 00 58 svshape 1,1,16,15,1
+ c0: 19 00 09 58 svshape 1,10,1,0,0
+ c4: 59 00 09 58 svshape 1,10,1,0,1
+ c8: 99 02 09 58 svshape 1,10,1,5,0
+ cc: d9 02 09 58 svshape 1,10,1,5,1
+ d0: 19 05 09 58 svshape 1,10,1,10,0
+ d4: 59 05 09 58 svshape 1,10,1,10,1
+ d8: 99 07 09 58 svshape 1,10,1,15,0
+ dc: d9 07 09 58 svshape 1,10,1,15,1
+ e0: 19 48 09 58 svshape 1,10,10,0,0
+ e4: 59 48 09 58 svshape 1,10,10,0,1
+ e8: 99 4a 09 58 svshape 1,10,10,5,0
+ ec: d9 4a 09 58 svshape 1,10,10,5,1
+ f0: 19 4d 09 58 svshape 1,10,10,10,0
+ f4: 59 4d 09 58 svshape 1,10,10,10,1
+ f8: 99 4f 09 58 svshape 1,10,10,15,0
+ fc: d9 4f 09 58 svshape 1,10,10,15,1
+ 100: 19 a0 09 58 svshape 1,10,21,0,0
+ 104: 59 a0 09 58 svshape 1,10,21,0,1
+ 108: 99 a2 09 58 svshape 1,10,21,5,0
+ 10c: d9 a2 09 58 svshape 1,10,21,5,1
+ 110: 19 a5 09 58 svshape 1,10,21,10,0
+ 114: 59 a5 09 58 svshape 1,10,21,10,1
+ 118: 99 a7 09 58 svshape 1,10,21,15,0
+ 11c: d9 a7 09 58 svshape 1,10,21,15,1
+ 120: 19 d0 09 58 svshape 1,10,27,0,0
+ 124: 59 d0 09 58 svshape 1,10,27,0,1
+ 128: 99 d2 09 58 svshape 1,10,27,5,0
+ 12c: d9 d2 09 58 svshape 1,10,27,5,1
+ 130: 19 d5 09 58 svshape 1,10,27,10,0
+ 134: 59 d5 09 58 svshape 1,10,27,10,1
+ 138: 99 d7 09 58 svshape 1,10,27,15,0
+ 13c: d9 d7 09 58 svshape 1,10,27,15,1
+ 140: 19 f0 09 58 svshape 1,10,31,0,0
+ 144: 59 f0 09 58 svshape 1,10,31,0,1
+ 148: 99 f2 09 58 svshape 1,10,31,5,0
+ 14c: d9 f2 09 58 svshape 1,10,31,5,1
+ 150: 19 f5 09 58 svshape 1,10,31,10,0
+ 154: 59 f5 09 58 svshape 1,10,31,10,1
+ 158: 99 f7 09 58 svshape 1,10,31,15,0
+ 15c: d9 f7 09 58 svshape 1,10,31,15,1
+ 160: 19 78 09 58 svshape 1,10,16,0,0
+ 164: 59 78 09 58 svshape 1,10,16,0,1
+ 168: 99 7a 09 58 svshape 1,10,16,5,0
+ 16c: d9 7a 09 58 svshape 1,10,16,5,1
+ 170: 19 7d 09 58 svshape 1,10,16,10,0
+ 174: 59 7d 09 58 svshape 1,10,16,10,1
+ 178: 99 7f 09 58 svshape 1,10,16,15,0
+ 17c: d9 7f 09 58 svshape 1,10,16,15,1
+ 180: 19 00 14 58 svshape 1,21,1,0,0
+ 184: 59 00 14 58 svshape 1,21,1,0,1
+ 188: 99 02 14 58 svshape 1,21,1,5,0
+ 18c: d9 02 14 58 svshape 1,21,1,5,1
+ 190: 19 05 14 58 svshape 1,21,1,10,0
+ 194: 59 05 14 58 svshape 1,21,1,10,1
+ 198: 99 07 14 58 svshape 1,21,1,15,0
+ 19c: d9 07 14 58 svshape 1,21,1,15,1
+ 1a0: 19 48 14 58 svshape 1,21,10,0,0
+ 1a4: 59 48 14 58 svshape 1,21,10,0,1
+ 1a8: 99 4a 14 58 svshape 1,21,10,5,0
+ 1ac: d9 4a 14 58 svshape 1,21,10,5,1
+ 1b0: 19 4d 14 58 svshape 1,21,10,10,0
+ 1b4: 59 4d 14 58 svshape 1,21,10,10,1
+ 1b8: 99 4f 14 58 svshape 1,21,10,15,0
+ 1bc: d9 4f 14 58 svshape 1,21,10,15,1
+ 1c0: 19 a0 14 58 svshape 1,21,21,0,0
+ 1c4: 59 a0 14 58 svshape 1,21,21,0,1
+ 1c8: 99 a2 14 58 svshape 1,21,21,5,0
+ 1cc: d9 a2 14 58 svshape 1,21,21,5,1
+ 1d0: 19 a5 14 58 svshape 1,21,21,10,0
+ 1d4: 59 a5 14 58 svshape 1,21,21,10,1
+ 1d8: 99 a7 14 58 svshape 1,21,21,15,0
+ 1dc: d9 a7 14 58 svshape 1,21,21,15,1
+ 1e0: 19 d0 14 58 svshape 1,21,27,0,0
+ 1e4: 59 d0 14 58 svshape 1,21,27,0,1
+ 1e8: 99 d2 14 58 svshape 1,21,27,5,0
+ 1ec: d9 d2 14 58 svshape 1,21,27,5,1
+ 1f0: 19 d5 14 58 svshape 1,21,27,10,0
+ 1f4: 59 d5 14 58 svshape 1,21,27,10,1
+ 1f8: 99 d7 14 58 svshape 1,21,27,15,0
+ 1fc: d9 d7 14 58 svshape 1,21,27,15,1
+ 200: 19 f0 14 58 svshape 1,21,31,0,0
+ 204: 59 f0 14 58 svshape 1,21,31,0,1
+ 208: 99 f2 14 58 svshape 1,21,31,5,0
+ 20c: d9 f2 14 58 svshape 1,21,31,5,1
+ 210: 19 f5 14 58 svshape 1,21,31,10,0
+ 214: 59 f5 14 58 svshape 1,21,31,10,1
+ 218: 99 f7 14 58 svshape 1,21,31,15,0
+ 21c: d9 f7 14 58 svshape 1,21,31,15,1
+ 220: 19 78 14 58 svshape 1,21,16,0,0
+ 224: 59 78 14 58 svshape 1,21,16,0,1
+ 228: 99 7a 14 58 svshape 1,21,16,5,0
+ 22c: d9 7a 14 58 svshape 1,21,16,5,1
+ 230: 19 7d 14 58 svshape 1,21,16,10,0
+ 234: 59 7d 14 58 svshape 1,21,16,10,1
+ 238: 99 7f 14 58 svshape 1,21,16,15,0
+ 23c: d9 7f 14 58 svshape 1,21,16,15,1
+ 240: 19 00 1a 58 svshape 1,27,1,0,0
+ 244: 59 00 1a 58 svshape 1,27,1,0,1
+ 248: 99 02 1a 58 svshape 1,27,1,5,0
+ 24c: d9 02 1a 58 svshape 1,27,1,5,1
+ 250: 19 05 1a 58 svshape 1,27,1,10,0
+ 254: 59 05 1a 58 svshape 1,27,1,10,1
+ 258: 99 07 1a 58 svshape 1,27,1,15,0
+ 25c: d9 07 1a 58 svshape 1,27,1,15,1
+ 260: 19 48 1a 58 svshape 1,27,10,0,0
+ 264: 59 48 1a 58 svshape 1,27,10,0,1
+ 268: 99 4a 1a 58 svshape 1,27,10,5,0
+ 26c: d9 4a 1a 58 svshape 1,27,10,5,1
+ 270: 19 4d 1a 58 svshape 1,27,10,10,0
+ 274: 59 4d 1a 58 svshape 1,27,10,10,1
+ 278: 99 4f 1a 58 svshape 1,27,10,15,0
+ 27c: d9 4f 1a 58 svshape 1,27,10,15,1
+ 280: 19 a0 1a 58 svshape 1,27,21,0,0
+ 284: 59 a0 1a 58 svshape 1,27,21,0,1
+ 288: 99 a2 1a 58 svshape 1,27,21,5,0
+ 28c: d9 a2 1a 58 svshape 1,27,21,5,1
+ 290: 19 a5 1a 58 svshape 1,27,21,10,0
+ 294: 59 a5 1a 58 svshape 1,27,21,10,1
+ 298: 99 a7 1a 58 svshape 1,27,21,15,0
+ 29c: d9 a7 1a 58 svshape 1,27,21,15,1
+ 2a0: 19 d0 1a 58 svshape 1,27,27,0,0
+ 2a4: 59 d0 1a 58 svshape 1,27,27,0,1
+ 2a8: 99 d2 1a 58 svshape 1,27,27,5,0
+ 2ac: d9 d2 1a 58 svshape 1,27,27,5,1
+ 2b0: 19 d5 1a 58 svshape 1,27,27,10,0
+ 2b4: 59 d5 1a 58 svshape 1,27,27,10,1
+ 2b8: 99 d7 1a 58 svshape 1,27,27,15,0
+ 2bc: d9 d7 1a 58 svshape 1,27,27,15,1
+ 2c0: 19 f0 1a 58 svshape 1,27,31,0,0
+ 2c4: 59 f0 1a 58 svshape 1,27,31,0,1
+ 2c8: 99 f2 1a 58 svshape 1,27,31,5,0
+ 2cc: d9 f2 1a 58 svshape 1,27,31,5,1
+ 2d0: 19 f5 1a 58 svshape 1,27,31,10,0
+ 2d4: 59 f5 1a 58 svshape 1,27,31,10,1
+ 2d8: 99 f7 1a 58 svshape 1,27,31,15,0
+ 2dc: d9 f7 1a 58 svshape 1,27,31,15,1
+ 2e0: 19 78 1a 58 svshape 1,27,16,0,0
+ 2e4: 59 78 1a 58 svshape 1,27,16,0,1
+ 2e8: 99 7a 1a 58 svshape 1,27,16,5,0
+ 2ec: d9 7a 1a 58 svshape 1,27,16,5,1
+ 2f0: 19 7d 1a 58 svshape 1,27,16,10,0
+ 2f4: 59 7d 1a 58 svshape 1,27,16,10,1
+ 2f8: 99 7f 1a 58 svshape 1,27,16,15,0
+ 2fc: d9 7f 1a 58 svshape 1,27,16,15,1
+ 300: 19 00 1e 58 svshape 1,31,1,0,0
+ 304: 59 00 1e 58 svshape 1,31,1,0,1
+ 308: 99 02 1e 58 svshape 1,31,1,5,0
+ 30c: d9 02 1e 58 svshape 1,31,1,5,1
+ 310: 19 05 1e 58 svshape 1,31,1,10,0
+ 314: 59 05 1e 58 svshape 1,31,1,10,1
+ 318: 99 07 1e 58 svshape 1,31,1,15,0
+ 31c: d9 07 1e 58 svshape 1,31,1,15,1
+ 320: 19 48 1e 58 svshape 1,31,10,0,0
+ 324: 59 48 1e 58 svshape 1,31,10,0,1
+ 328: 99 4a 1e 58 svshape 1,31,10,5,0
+ 32c: d9 4a 1e 58 svshape 1,31,10,5,1
+ 330: 19 4d 1e 58 svshape 1,31,10,10,0
+ 334: 59 4d 1e 58 svshape 1,31,10,10,1
+ 338: 99 4f 1e 58 svshape 1,31,10,15,0
+ 33c: d9 4f 1e 58 svshape 1,31,10,15,1
+ 340: 19 a0 1e 58 svshape 1,31,21,0,0
+ 344: 59 a0 1e 58 svshape 1,31,21,0,1
+ 348: 99 a2 1e 58 svshape 1,31,21,5,0
+ 34c: d9 a2 1e 58 svshape 1,31,21,5,1
+ 350: 19 a5 1e 58 svshape 1,31,21,10,0
+ 354: 59 a5 1e 58 svshape 1,31,21,10,1
+ 358: 99 a7 1e 58 svshape 1,31,21,15,0
+ 35c: d9 a7 1e 58 svshape 1,31,21,15,1
+ 360: 19 d0 1e 58 svshape 1,31,27,0,0
+ 364: 59 d0 1e 58 svshape 1,31,27,0,1
+ 368: 99 d2 1e 58 svshape 1,31,27,5,0
+ 36c: d9 d2 1e 58 svshape 1,31,27,5,1
+ 370: 19 d5 1e 58 svshape 1,31,27,10,0
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+ 378: 99 d7 1e 58 svshape 1,31,27,15,0
+ 37c: d9 d7 1e 58 svshape 1,31,27,15,1
+ 380: 19 f0 1e 58 svshape 1,31,31,0,0
+ 384: 59 f0 1e 58 svshape 1,31,31,0,1
+ 388: 99 f2 1e 58 svshape 1,31,31,5,0
+ 38c: d9 f2 1e 58 svshape 1,31,31,5,1
+ 390: 19 f5 1e 58 svshape 1,31,31,10,0
+ 394: 59 f5 1e 58 svshape 1,31,31,10,1
+ 398: 99 f7 1e 58 svshape 1,31,31,15,0
+ 39c: d9 f7 1e 58 svshape 1,31,31,15,1
+ 3a0: 19 78 1e 58 svshape 1,31,16,0,0
+ 3a4: 59 78 1e 58 svshape 1,31,16,0,1
+ 3a8: 99 7a 1e 58 svshape 1,31,16,5,0
+ 3ac: d9 7a 1e 58 svshape 1,31,16,5,1
+ 3b0: 19 7d 1e 58 svshape 1,31,16,10,0
+ 3b4: 59 7d 1e 58 svshape 1,31,16,10,1
+ 3b8: 99 7f 1e 58 svshape 1,31,16,15,0
+ 3bc: d9 7f 1e 58 svshape 1,31,16,15,1
+ 3c0: 19 00 0f 58 svshape 1,16,1,0,0
+ 3c4: 59 00 0f 58 svshape 1,16,1,0,1
+ 3c8: 99 02 0f 58 svshape 1,16,1,5,0
+ 3cc: d9 02 0f 58 svshape 1,16,1,5,1
+ 3d0: 19 05 0f 58 svshape 1,16,1,10,0
+ 3d4: 59 05 0f 58 svshape 1,16,1,10,1
+ 3d8: 99 07 0f 58 svshape 1,16,1,15,0
+ 3dc: d9 07 0f 58 svshape 1,16,1,15,1
+ 3e0: 19 48 0f 58 svshape 1,16,10,0,0
+ 3e4: 59 48 0f 58 svshape 1,16,10,0,1
+ 3e8: 99 4a 0f 58 svshape 1,16,10,5,0
+ 3ec: d9 4a 0f 58 svshape 1,16,10,5,1
+ 3f0: 19 4d 0f 58 svshape 1,16,10,10,0
+ 3f4: 59 4d 0f 58 svshape 1,16,10,10,1
+ 3f8: 99 4f 0f 58 svshape 1,16,10,15,0
+ 3fc: d9 4f 0f 58 svshape 1,16,10,15,1
+ 400: 19 a0 0f 58 svshape 1,16,21,0,0
+ 404: 59 a0 0f 58 svshape 1,16,21,0,1
+ 408: 99 a2 0f 58 svshape 1,16,21,5,0
+ 40c: d9 a2 0f 58 svshape 1,16,21,5,1
+ 410: 19 a5 0f 58 svshape 1,16,21,10,0
+ 414: 59 a5 0f 58 svshape 1,16,21,10,1
+ 418: 99 a7 0f 58 svshape 1,16,21,15,0
+ 41c: d9 a7 0f 58 svshape 1,16,21,15,1
+ 420: 19 d0 0f 58 svshape 1,16,27,0,0
+ 424: 59 d0 0f 58 svshape 1,16,27,0,1
+ 428: 99 d2 0f 58 svshape 1,16,27,5,0
+ 42c: d9 d2 0f 58 svshape 1,16,27,5,1
+ 430: 19 d5 0f 58 svshape 1,16,27,10,0
+ 434: 59 d5 0f 58 svshape 1,16,27,10,1
+ 438: 99 d7 0f 58 svshape 1,16,27,15,0
+ 43c: d9 d7 0f 58 svshape 1,16,27,15,1
+ 440: 19 f0 0f 58 svshape 1,16,31,0,0
+ 444: 59 f0 0f 58 svshape 1,16,31,0,1
+ 448: 99 f2 0f 58 svshape 1,16,31,5,0
+ 44c: d9 f2 0f 58 svshape 1,16,31,5,1
+ 450: 19 f5 0f 58 svshape 1,16,31,10,0
+ 454: 59 f5 0f 58 svshape 1,16,31,10,1
+ 458: 99 f7 0f 58 svshape 1,16,31,15,0
+ 45c: d9 f7 0f 58 svshape 1,16,31,15,1
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diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..6a0984aa5f
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,1728 @@
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+svshape 16,31,21,10,0
+svshape 16,31,21,10,1
+svshape 16,31,21,15,0
+svshape 16,31,21,15,1
+svshape 16,31,27,0,0
+svshape 16,31,27,0,1
+svshape 16,31,27,5,0
+svshape 16,31,27,5,1
+svshape 16,31,27,10,0
+svshape 16,31,27,10,1
+svshape 16,31,27,15,0
+svshape 16,31,27,15,1
+svshape 16,31,31,0,0
+svshape 16,31,31,0,1
+svshape 16,31,31,5,0
+svshape 16,31,31,5,1
+svshape 16,31,31,10,0
+svshape 16,31,31,10,1
+svshape 16,31,31,15,0
+svshape 16,31,31,15,1
+svshape 16,31,16,0,0
+svshape 16,31,16,0,1
+svshape 16,31,16,5,0
+svshape 16,31,16,5,1
+svshape 16,31,16,10,0
+svshape 16,31,16,10,1
+svshape 16,31,16,15,0
+svshape 16,31,16,15,1
+svshape 16,16,1,0,0
+svshape 16,16,1,0,1
+svshape 16,16,1,5,0
+svshape 16,16,1,5,1
+svshape 16,16,1,10,0
+svshape 16,16,1,10,1
+svshape 16,16,1,15,0
+svshape 16,16,1,15,1
+svshape 16,16,10,0,0
+svshape 16,16,10,0,1
+svshape 16,16,10,5,0
+svshape 16,16,10,5,1
+svshape 16,16,10,10,0
+svshape 16,16,10,10,1
+svshape 16,16,10,15,0
+svshape 16,16,10,15,1
+svshape 16,16,21,0,0
+svshape 16,16,21,0,1
+svshape 16,16,21,5,0
+svshape 16,16,21,5,1
+svshape 16,16,21,10,0
+svshape 16,16,21,10,1
+svshape 16,16,21,15,0
+svshape 16,16,21,15,1
+svshape 16,16,27,0,0
+svshape 16,16,27,0,1
+svshape 16,16,27,5,0
+svshape 16,16,27,5,1
+svshape 16,16,27,10,0
+svshape 16,16,27,10,1
+svshape 16,16,27,15,0
+svshape 16,16,27,15,1
+svshape 16,16,31,0,0
+svshape 16,16,31,0,1
+svshape 16,16,31,5,0
+svshape 16,16,31,5,1
+svshape 16,16,31,10,0
+svshape 16,16,31,10,1
+svshape 16,16,31,15,0
+svshape 16,16,31,15,1
+svshape 16,16,16,0,0
+svshape 16,16,16,0,1
+svshape 16,16,16,5,0
+svshape 16,16,16,5,1
+svshape 16,16,16,10,0
+svshape 16,16,16,10,1
+svshape 16,16,16,15,0
+svshape 16,16,16,15,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index b053a15125..f5fd444ea3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2739,6 +2739,76 @@ extract_svi (uint64_t insn ATTRIBUTE_UNUSED,
return (((insn >> 9) & 0x3f) + 1);
}
+static uint64_t
+insert_svm (uint64_t insn,
+ int64_t value,
+ unsigned int shift,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return (insn | (((value - 1) & 0x1f) << shift));
+}
+
+static uint64_t
+insert_svxd (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_svm (insn, value, 21, dialect, errmsg);
+}
+
+static uint64_t
+insert_svyd (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_svm (insn, value, 16, dialect, errmsg);
+}
+
+static uint64_t
+insert_svzd (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_svm (insn, value, 11, dialect, errmsg);
+}
+
+static int64_t
+extract_svm (uint64_t insn,
+ unsigned int shift,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> shift) & 0x1f) + 1);
+}
+
+static int64_t
+extract_svxd (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_svm (insn, 21, dialect, invalid);
+}
+
+static int64_t
+extract_svyd (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_svm (insn, 16, dialect, invalid);
+}
+
+static int64_t
+extract_svzd (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_svm (insn, 11, dialect, invalid);
+}
+
\f
/* The operands table.
@@ -3857,6 +3927,21 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
{ 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+ { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+ { 0x1f, 21, insert_svxd, extract_svxd, 0 },
+
+#define SVyd SVxd + 1
+ { 0x1f, 16, insert_svyd, extract_svyd, 0 },
+
+#define SVzd SVyd + 1
+ { 0x1f, 11, insert_svzd, extract_svzd, 0 },
+
+#define SVRMf SVzd + 1
+ { 0xf, 7, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4733,6 +4818,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(rc)) & 1))
#define SVL_MASK SVL (0x3f, 0x1f, 1)
+/* An SVM form instruction. */
+#define SVM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK SVM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6805,6 +6896,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVRMf, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH 0/5] ppc/svp64: support SVP64 and its first insns
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (3 preceding siblings ...)
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
@ 2022-06-19 23:49 ` Alan Modra
2022-06-21 11:55 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
5 siblings, 1 reply; 62+ messages in thread
From: Alan Modra @ 2022-06-19 23:49 UTC (permalink / raw)
To: Dmitry Selyutin; +Cc: binutils, luke.leighton
On Fri, Jun 17, 2022 at 10:08:15PM +0300, Dmitry Selyutin wrote:
> These patches introduce SVP64 extension and LibreSOC CPU which supports
> this extension. We also provide the first 32-bit instructions, namely
> setvl, svstep, svshape and svremap, plus the corresponding tests.
These all look good to me, and can be pushed when your copyright
assignment is complete. The only review comment I have is that
#define SVme TO
would be better for maintenance if placed with the TO definition, so
that someone doesn't change the TO entry without realising they are
also changing things for SVme. Similarly for the other aliases you
define.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (4 preceding siblings ...)
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
@ 2022-06-21 11:51 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
` (6 more replies)
5 siblings, 7 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-21 11:51 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
Changes since v1:
- Aliased instruction fields now appear after the original ones.
Dmitry Selyutin (5):
ppc/svp64: support LibreSOC architecture
ppc/svp64: support setvl instructions
ppc/svp64: support svstep instructions
ppc/svp64: support svshape instruction
ppc/svp64: support svremap instruction
gas/config/tc-ppc.c | 2 +
gas/testsuite/gas/ppc/ppc.exp | 5 +
gas/testsuite/gas/ppc/setvl.d | 2408 +++++++
gas/testsuite/gas/ppc/setvl.s | 2400 +++++++
gas/testsuite/gas/ppc/svremap.d | 10248 ++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 10240 +++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svshape.d | 1736 +++++
gas/testsuite/gas/ppc/svshape.s | 1728 +++++
gas/testsuite/gas/ppc/svstep.d | 128 +
gas/testsuite/gas/ppc/svstep.s | 120 +
include/opcode/ppc.h | 3 +
opcodes/ppc-dis.c | 5 +
opcodes/ppc-opc.c | 159 +
13 files changed, 29182 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
@ 2022-06-21 11:51 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
` (5 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-21 11:51 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
---
gas/config/tc-ppc.c | 2 ++
include/opcode/ppc.h | 3 +++
opcodes/ppc-dis.c | 5 +++++
opcodes/ppc-opc.c | 1 +
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4d789fd16a..76bdfb2e35 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e..d5752a42e6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5..f61e6518f1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5bd6dac50..fe2fcaeb1d 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 2/5] ppc/svp64: support setvl instructions
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
@ 2022-06-21 11:51 ` Dmitry Selyutin
2022-06-21 18:25 ` Peter Bergner
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
` (4 subsequent siblings)
6 siblings, 1 reply; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-21 11:51 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
---
gas/testsuite/gas/ppc/ppc.exp | 2 +
gas/testsuite/gas/ppc/setvl.d | 2408 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 2400 ++++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 42 +
4 files changed, 4852 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6a..cd4dd658ce 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..46c6d9bbc0
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,2408 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 36 00 00 58 setvl r0,r0,1,0,0,0
+ 4: 36 01 00 58 setvl r0,r0,1,0,0,1
+ 8: b6 00 00 58 setvl r0,r0,1,0,1,0
+ c: b6 01 00 58 setvl r0,r0,1,0,1,1
+ 10: 76 00 00 58 setvl r0,r0,1,1,0,0
+ 14: 76 01 00 58 setvl r0,r0,1,1,0,1
+ 18: f6 00 00 58 setvl r0,r0,1,1,1,0
+ 1c: f6 01 00 58 setvl r0,r0,1,1,1,1
+ 20: 36 28 00 58 setvl r0,r0,21,0,0,0
+ 24: 36 29 00 58 setvl r0,r0,21,0,0,1
+ 28: b6 28 00 58 setvl r0,r0,21,0,1,0
+ 2c: b6 29 00 58 setvl r0,r0,21,0,1,1
+ 30: 76 28 00 58 setvl r0,r0,21,1,0,0
+ 34: 76 29 00 58 setvl r0,r0,21,1,0,1
+ 38: f6 28 00 58 setvl r0,r0,21,1,1,0
+ 3c: f6 29 00 58 setvl r0,r0,21,1,1,1
+ 40: 36 52 00 58 setvl r0,r0,42,0,0,0
+ 44: 36 53 00 58 setvl r0,r0,42,0,0,1
+ 48: b6 52 00 58 setvl r0,r0,42,0,1,0
+ 4c: b6 53 00 58 setvl r0,r0,42,0,1,1
+ 50: 76 52 00 58 setvl r0,r0,42,1,0,0
+ 54: 76 53 00 58 setvl r0,r0,42,1,0,1
+ 58: f6 52 00 58 setvl r0,r0,42,1,1,0
+ 5c: f6 53 00 58 setvl r0,r0,42,1,1,1
+ 60: 36 64 00 58 setvl r0,r0,51,0,0,0
+ 64: 36 65 00 58 setvl r0,r0,51,0,0,1
+ 68: b6 64 00 58 setvl r0,r0,51,0,1,0
+ 6c: b6 65 00 58 setvl r0,r0,51,0,1,1
+ 70: 76 64 00 58 setvl r0,r0,51,1,0,0
+ 74: 76 65 00 58 setvl r0,r0,51,1,0,1
+ 78: f6 64 00 58 setvl r0,r0,51,1,1,0
+ 7c: f6 65 00 58 setvl r0,r0,51,1,1,1
+ 80: 36 7c 00 58 setvl r0,r0,63,0,0,0
+ 84: 36 7d 00 58 setvl r0,r0,63,0,0,1
+ 88: b6 7c 00 58 setvl r0,r0,63,0,1,0
+ 8c: b6 7d 00 58 setvl r0,r0,63,0,1,1
+ 90: 76 7c 00 58 setvl r0,r0,63,1,0,0
+ 94: 76 7d 00 58 setvl r0,r0,63,1,0,1
+ 98: f6 7c 00 58 setvl r0,r0,63,1,1,0
+ 9c: f6 7d 00 58 setvl r0,r0,63,1,1,1
+ a0: 36 3e 00 58 setvl r0,r0,32,0,0,0
+ a4: 36 3f 00 58 setvl r0,r0,32,0,0,1
+ a8: b6 3e 00 58 setvl r0,r0,32,0,1,0
+ ac: b6 3f 00 58 setvl r0,r0,32,0,1,1
+ b0: 76 3e 00 58 setvl r0,r0,32,1,0,0
+ b4: 76 3f 00 58 setvl r0,r0,32,1,0,1
+ b8: f6 3e 00 58 setvl r0,r0,32,1,1,0
+ bc: f6 3f 00 58 setvl r0,r0,32,1,1,1
+ c0: 36 00 0a 58 setvl r0,r10,1,0,0,0
+ c4: 36 01 0a 58 setvl r0,r10,1,0,0,1
+ c8: b6 00 0a 58 setvl r0,r10,1,0,1,0
+ cc: b6 01 0a 58 setvl r0,r10,1,0,1,1
+ d0: 76 00 0a 58 setvl r0,r10,1,1,0,0
+ d4: 76 01 0a 58 setvl r0,r10,1,1,0,1
+ d8: f6 00 0a 58 setvl r0,r10,1,1,1,0
+ dc: f6 01 0a 58 setvl r0,r10,1,1,1,1
+ e0: 36 28 0a 58 setvl r0,r10,21,0,0,0
+ e4: 36 29 0a 58 setvl r0,r10,21,0,0,1
+ e8: b6 28 0a 58 setvl r0,r10,21,0,1,0
+ ec: b6 29 0a 58 setvl r0,r10,21,0,1,1
+ f0: 76 28 0a 58 setvl r0,r10,21,1,0,0
+ f4: 76 29 0a 58 setvl r0,r10,21,1,0,1
+ f8: f6 28 0a 58 setvl r0,r10,21,1,1,0
+ fc: f6 29 0a 58 setvl r0,r10,21,1,1,1
+ 100: 36 52 0a 58 setvl r0,r10,42,0,0,0
+ 104: 36 53 0a 58 setvl r0,r10,42,0,0,1
+ 108: b6 52 0a 58 setvl r0,r10,42,0,1,0
+ 10c: b6 53 0a 58 setvl r0,r10,42,0,1,1
+ 110: 76 52 0a 58 setvl r0,r10,42,1,0,0
+ 114: 76 53 0a 58 setvl r0,r10,42,1,0,1
+ 118: f6 52 0a 58 setvl r0,r10,42,1,1,0
+ 11c: f6 53 0a 58 setvl r0,r10,42,1,1,1
+ 120: 36 64 0a 58 setvl r0,r10,51,0,0,0
+ 124: 36 65 0a 58 setvl r0,r10,51,0,0,1
+ 128: b6 64 0a 58 setvl r0,r10,51,0,1,0
+ 12c: b6 65 0a 58 setvl r0,r10,51,0,1,1
+ 130: 76 64 0a 58 setvl r0,r10,51,1,0,0
+ 134: 76 65 0a 58 setvl r0,r10,51,1,0,1
+ 138: f6 64 0a 58 setvl r0,r10,51,1,1,0
+ 13c: f6 65 0a 58 setvl r0,r10,51,1,1,1
+ 140: 36 7c 0a 58 setvl r0,r10,63,0,0,0
+ 144: 36 7d 0a 58 setvl r0,r10,63,0,0,1
+ 148: b6 7c 0a 58 setvl r0,r10,63,0,1,0
+ 14c: b6 7d 0a 58 setvl r0,r10,63,0,1,1
+ 150: 76 7c 0a 58 setvl r0,r10,63,1,0,0
+ 154: 76 7d 0a 58 setvl r0,r10,63,1,0,1
+ 158: f6 7c 0a 58 setvl r0,r10,63,1,1,0
+ 15c: f6 7d 0a 58 setvl r0,r10,63,1,1,1
+ 160: 36 3e 0a 58 setvl r0,r10,32,0,0,0
+ 164: 36 3f 0a 58 setvl r0,r10,32,0,0,1
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+ 215c: f7 53 7f 5b setvl\. r27,r31,42,1,1,1
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+ 2558: f7 7c ff 5b setvl\. r31,r31,63,1,1,0
+ 255c: f7 7d ff 5b setvl\. r31,r31,63,1,1,1
+ 2560: 37 3e ff 5b setvl\. r31,r31,32,0,0,0
+ 2564: 37 3f ff 5b setvl\. r31,r31,32,0,0,1
+ 2568: b7 3e ff 5b setvl\. r31,r31,32,0,1,0
+ 256c: b7 3f ff 5b setvl\. r31,r31,32,0,1,1
+ 2570: 77 3e ff 5b setvl\. r31,r31,32,1,0,0
+ 2574: 77 3f ff 5b setvl\. r31,r31,32,1,0,1
+ 2578: f7 3e ff 5b setvl\. r31,r31,32,1,1,0
+ 257c: f7 3f ff 5b setvl\. r31,r31,32,1,1,1
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..944f8afc08
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,2400 @@
+setvl 0,0,1,0,0,0
+setvl 0,0,1,0,0,1
+setvl 0,0,1,0,1,0
+setvl 0,0,1,0,1,1
+setvl 0,0,1,1,0,0
+setvl 0,0,1,1,0,1
+setvl 0,0,1,1,1,0
+setvl 0,0,1,1,1,1
+setvl 0,0,21,0,0,0
+setvl 0,0,21,0,0,1
+setvl 0,0,21,0,1,0
+setvl 0,0,21,0,1,1
+setvl 0,0,21,1,0,0
+setvl 0,0,21,1,0,1
+setvl 0,0,21,1,1,0
+setvl 0,0,21,1,1,1
+setvl 0,0,42,0,0,0
+setvl 0,0,42,0,0,1
+setvl 0,0,42,0,1,0
+setvl 0,0,42,0,1,1
+setvl 0,0,42,1,0,0
+setvl 0,0,42,1,0,1
+setvl 0,0,42,1,1,0
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+setvl. 27,10,32,0,1,1
+setvl. 27,10,32,1,0,0
+setvl. 27,10,32,1,0,1
+setvl. 27,10,32,1,1,0
+setvl. 27,10,32,1,1,1
+setvl. 27,21,1,0,0,0
+setvl. 27,21,1,0,0,1
+setvl. 27,21,1,0,1,0
+setvl. 27,21,1,0,1,1
+setvl. 27,21,1,1,0,0
+setvl. 27,21,1,1,0,1
+setvl. 27,21,1,1,1,0
+setvl. 27,21,1,1,1,1
+setvl. 27,21,21,0,0,0
+setvl. 27,21,21,0,0,1
+setvl. 27,21,21,0,1,0
+setvl. 27,21,21,0,1,1
+setvl. 27,21,21,1,0,0
+setvl. 27,21,21,1,0,1
+setvl. 27,21,21,1,1,0
+setvl. 27,21,21,1,1,1
+setvl. 27,21,42,0,0,0
+setvl. 27,21,42,0,0,1
+setvl. 27,21,42,0,1,0
+setvl. 27,21,42,0,1,1
+setvl. 27,21,42,1,0,0
+setvl. 27,21,42,1,0,1
+setvl. 27,21,42,1,1,0
+setvl. 27,21,42,1,1,1
+setvl. 27,21,51,0,0,0
+setvl. 27,21,51,0,0,1
+setvl. 27,21,51,0,1,0
+setvl. 27,21,51,0,1,1
+setvl. 27,21,51,1,0,0
+setvl. 27,21,51,1,0,1
+setvl. 27,21,51,1,1,0
+setvl. 27,21,51,1,1,1
+setvl. 27,21,63,0,0,0
+setvl. 27,21,63,0,0,1
+setvl. 27,21,63,0,1,0
+setvl. 27,21,63,0,1,1
+setvl. 27,21,63,1,0,0
+setvl. 27,21,63,1,0,1
+setvl. 27,21,63,1,1,0
+setvl. 27,21,63,1,1,1
+setvl. 27,21,32,0,0,0
+setvl. 27,21,32,0,0,1
+setvl. 27,21,32,0,1,0
+setvl. 27,21,32,0,1,1
+setvl. 27,21,32,1,0,0
+setvl. 27,21,32,1,0,1
+setvl. 27,21,32,1,1,0
+setvl. 27,21,32,1,1,1
+setvl. 27,27,1,0,0,0
+setvl. 27,27,1,0,0,1
+setvl. 27,27,1,0,1,0
+setvl. 27,27,1,0,1,1
+setvl. 27,27,1,1,0,0
+setvl. 27,27,1,1,0,1
+setvl. 27,27,1,1,1,0
+setvl. 27,27,1,1,1,1
+setvl. 27,27,21,0,0,0
+setvl. 27,27,21,0,0,1
+setvl. 27,27,21,0,1,0
+setvl. 27,27,21,0,1,1
+setvl. 27,27,21,1,0,0
+setvl. 27,27,21,1,0,1
+setvl. 27,27,21,1,1,0
+setvl. 27,27,21,1,1,1
+setvl. 27,27,42,0,0,0
+setvl. 27,27,42,0,0,1
+setvl. 27,27,42,0,1,0
+setvl. 27,27,42,0,1,1
+setvl. 27,27,42,1,0,0
+setvl. 27,27,42,1,0,1
+setvl. 27,27,42,1,1,0
+setvl. 27,27,42,1,1,1
+setvl. 27,27,51,0,0,0
+setvl. 27,27,51,0,0,1
+setvl. 27,27,51,0,1,0
+setvl. 27,27,51,0,1,1
+setvl. 27,27,51,1,0,0
+setvl. 27,27,51,1,0,1
+setvl. 27,27,51,1,1,0
+setvl. 27,27,51,1,1,1
+setvl. 27,27,63,0,0,0
+setvl. 27,27,63,0,0,1
+setvl. 27,27,63,0,1,0
+setvl. 27,27,63,0,1,1
+setvl. 27,27,63,1,0,0
+setvl. 27,27,63,1,0,1
+setvl. 27,27,63,1,1,0
+setvl. 27,27,63,1,1,1
+setvl. 27,27,32,0,0,0
+setvl. 27,27,32,0,0,1
+setvl. 27,27,32,0,1,0
+setvl. 27,27,32,0,1,1
+setvl. 27,27,32,1,0,0
+setvl. 27,27,32,1,0,1
+setvl. 27,27,32,1,1,0
+setvl. 27,27,32,1,1,1
+setvl. 27,31,1,0,0,0
+setvl. 27,31,1,0,0,1
+setvl. 27,31,1,0,1,0
+setvl. 27,31,1,0,1,1
+setvl. 27,31,1,1,0,0
+setvl. 27,31,1,1,0,1
+setvl. 27,31,1,1,1,0
+setvl. 27,31,1,1,1,1
+setvl. 27,31,21,0,0,0
+setvl. 27,31,21,0,0,1
+setvl. 27,31,21,0,1,0
+setvl. 27,31,21,0,1,1
+setvl. 27,31,21,1,0,0
+setvl. 27,31,21,1,0,1
+setvl. 27,31,21,1,1,0
+setvl. 27,31,21,1,1,1
+setvl. 27,31,42,0,0,0
+setvl. 27,31,42,0,0,1
+setvl. 27,31,42,0,1,0
+setvl. 27,31,42,0,1,1
+setvl. 27,31,42,1,0,0
+setvl. 27,31,42,1,0,1
+setvl. 27,31,42,1,1,0
+setvl. 27,31,42,1,1,1
+setvl. 27,31,51,0,0,0
+setvl. 27,31,51,0,0,1
+setvl. 27,31,51,0,1,0
+setvl. 27,31,51,0,1,1
+setvl. 27,31,51,1,0,0
+setvl. 27,31,51,1,0,1
+setvl. 27,31,51,1,1,0
+setvl. 27,31,51,1,1,1
+setvl. 27,31,63,0,0,0
+setvl. 27,31,63,0,0,1
+setvl. 27,31,63,0,1,0
+setvl. 27,31,63,0,1,1
+setvl. 27,31,63,1,0,0
+setvl. 27,31,63,1,0,1
+setvl. 27,31,63,1,1,0
+setvl. 27,31,63,1,1,1
+setvl. 27,31,32,0,0,0
+setvl. 27,31,32,0,0,1
+setvl. 27,31,32,0,1,0
+setvl. 27,31,32,0,1,1
+setvl. 27,31,32,1,0,0
+setvl. 27,31,32,1,0,1
+setvl. 27,31,32,1,1,0
+setvl. 27,31,32,1,1,1
+setvl. 31,0,1,0,0,0
+setvl. 31,0,1,0,0,1
+setvl. 31,0,1,0,1,0
+setvl. 31,0,1,0,1,1
+setvl. 31,0,1,1,0,0
+setvl. 31,0,1,1,0,1
+setvl. 31,0,1,1,1,0
+setvl. 31,0,1,1,1,1
+setvl. 31,0,21,0,0,0
+setvl. 31,0,21,0,0,1
+setvl. 31,0,21,0,1,0
+setvl. 31,0,21,0,1,1
+setvl. 31,0,21,1,0,0
+setvl. 31,0,21,1,0,1
+setvl. 31,0,21,1,1,0
+setvl. 31,0,21,1,1,1
+setvl. 31,0,42,0,0,0
+setvl. 31,0,42,0,0,1
+setvl. 31,0,42,0,1,0
+setvl. 31,0,42,0,1,1
+setvl. 31,0,42,1,0,0
+setvl. 31,0,42,1,0,1
+setvl. 31,0,42,1,1,0
+setvl. 31,0,42,1,1,1
+setvl. 31,0,51,0,0,0
+setvl. 31,0,51,0,0,1
+setvl. 31,0,51,0,1,0
+setvl. 31,0,51,0,1,1
+setvl. 31,0,51,1,0,0
+setvl. 31,0,51,1,0,1
+setvl. 31,0,51,1,1,0
+setvl. 31,0,51,1,1,1
+setvl. 31,0,63,0,0,0
+setvl. 31,0,63,0,0,1
+setvl. 31,0,63,0,1,0
+setvl. 31,0,63,0,1,1
+setvl. 31,0,63,1,0,0
+setvl. 31,0,63,1,0,1
+setvl. 31,0,63,1,1,0
+setvl. 31,0,63,1,1,1
+setvl. 31,0,32,0,0,0
+setvl. 31,0,32,0,0,1
+setvl. 31,0,32,0,1,0
+setvl. 31,0,32,0,1,1
+setvl. 31,0,32,1,0,0
+setvl. 31,0,32,1,0,1
+setvl. 31,0,32,1,1,0
+setvl. 31,0,32,1,1,1
+setvl. 31,10,1,0,0,0
+setvl. 31,10,1,0,0,1
+setvl. 31,10,1,0,1,0
+setvl. 31,10,1,0,1,1
+setvl. 31,10,1,1,0,0
+setvl. 31,10,1,1,0,1
+setvl. 31,10,1,1,1,0
+setvl. 31,10,1,1,1,1
+setvl. 31,10,21,0,0,0
+setvl. 31,10,21,0,0,1
+setvl. 31,10,21,0,1,0
+setvl. 31,10,21,0,1,1
+setvl. 31,10,21,1,0,0
+setvl. 31,10,21,1,0,1
+setvl. 31,10,21,1,1,0
+setvl. 31,10,21,1,1,1
+setvl. 31,10,42,0,0,0
+setvl. 31,10,42,0,0,1
+setvl. 31,10,42,0,1,0
+setvl. 31,10,42,0,1,1
+setvl. 31,10,42,1,0,0
+setvl. 31,10,42,1,0,1
+setvl. 31,10,42,1,1,0
+setvl. 31,10,42,1,1,1
+setvl. 31,10,51,0,0,0
+setvl. 31,10,51,0,0,1
+setvl. 31,10,51,0,1,0
+setvl. 31,10,51,0,1,1
+setvl. 31,10,51,1,0,0
+setvl. 31,10,51,1,0,1
+setvl. 31,10,51,1,1,0
+setvl. 31,10,51,1,1,1
+setvl. 31,10,63,0,0,0
+setvl. 31,10,63,0,0,1
+setvl. 31,10,63,0,1,0
+setvl. 31,10,63,0,1,1
+setvl. 31,10,63,1,0,0
+setvl. 31,10,63,1,0,1
+setvl. 31,10,63,1,1,0
+setvl. 31,10,63,1,1,1
+setvl. 31,10,32,0,0,0
+setvl. 31,10,32,0,0,1
+setvl. 31,10,32,0,1,0
+setvl. 31,10,32,0,1,1
+setvl. 31,10,32,1,0,0
+setvl. 31,10,32,1,0,1
+setvl. 31,10,32,1,1,0
+setvl. 31,10,32,1,1,1
+setvl. 31,21,1,0,0,0
+setvl. 31,21,1,0,0,1
+setvl. 31,21,1,0,1,0
+setvl. 31,21,1,0,1,1
+setvl. 31,21,1,1,0,0
+setvl. 31,21,1,1,0,1
+setvl. 31,21,1,1,1,0
+setvl. 31,21,1,1,1,1
+setvl. 31,21,21,0,0,0
+setvl. 31,21,21,0,0,1
+setvl. 31,21,21,0,1,0
+setvl. 31,21,21,0,1,1
+setvl. 31,21,21,1,0,0
+setvl. 31,21,21,1,0,1
+setvl. 31,21,21,1,1,0
+setvl. 31,21,21,1,1,1
+setvl. 31,21,42,0,0,0
+setvl. 31,21,42,0,0,1
+setvl. 31,21,42,0,1,0
+setvl. 31,21,42,0,1,1
+setvl. 31,21,42,1,0,0
+setvl. 31,21,42,1,0,1
+setvl. 31,21,42,1,1,0
+setvl. 31,21,42,1,1,1
+setvl. 31,21,51,0,0,0
+setvl. 31,21,51,0,0,1
+setvl. 31,21,51,0,1,0
+setvl. 31,21,51,0,1,1
+setvl. 31,21,51,1,0,0
+setvl. 31,21,51,1,0,1
+setvl. 31,21,51,1,1,0
+setvl. 31,21,51,1,1,1
+setvl. 31,21,63,0,0,0
+setvl. 31,21,63,0,0,1
+setvl. 31,21,63,0,1,0
+setvl. 31,21,63,0,1,1
+setvl. 31,21,63,1,0,0
+setvl. 31,21,63,1,0,1
+setvl. 31,21,63,1,1,0
+setvl. 31,21,63,1,1,1
+setvl. 31,21,32,0,0,0
+setvl. 31,21,32,0,0,1
+setvl. 31,21,32,0,1,0
+setvl. 31,21,32,0,1,1
+setvl. 31,21,32,1,0,0
+setvl. 31,21,32,1,0,1
+setvl. 31,21,32,1,1,0
+setvl. 31,21,32,1,1,1
+setvl. 31,27,1,0,0,0
+setvl. 31,27,1,0,0,1
+setvl. 31,27,1,0,1,0
+setvl. 31,27,1,0,1,1
+setvl. 31,27,1,1,0,0
+setvl. 31,27,1,1,0,1
+setvl. 31,27,1,1,1,0
+setvl. 31,27,1,1,1,1
+setvl. 31,27,21,0,0,0
+setvl. 31,27,21,0,0,1
+setvl. 31,27,21,0,1,0
+setvl. 31,27,21,0,1,1
+setvl. 31,27,21,1,0,0
+setvl. 31,27,21,1,0,1
+setvl. 31,27,21,1,1,0
+setvl. 31,27,21,1,1,1
+setvl. 31,27,42,0,0,0
+setvl. 31,27,42,0,0,1
+setvl. 31,27,42,0,1,0
+setvl. 31,27,42,0,1,1
+setvl. 31,27,42,1,0,0
+setvl. 31,27,42,1,0,1
+setvl. 31,27,42,1,1,0
+setvl. 31,27,42,1,1,1
+setvl. 31,27,51,0,0,0
+setvl. 31,27,51,0,0,1
+setvl. 31,27,51,0,1,0
+setvl. 31,27,51,0,1,1
+setvl. 31,27,51,1,0,0
+setvl. 31,27,51,1,0,1
+setvl. 31,27,51,1,1,0
+setvl. 31,27,51,1,1,1
+setvl. 31,27,63,0,0,0
+setvl. 31,27,63,0,0,1
+setvl. 31,27,63,0,1,0
+setvl. 31,27,63,0,1,1
+setvl. 31,27,63,1,0,0
+setvl. 31,27,63,1,0,1
+setvl. 31,27,63,1,1,0
+setvl. 31,27,63,1,1,1
+setvl. 31,27,32,0,0,0
+setvl. 31,27,32,0,0,1
+setvl. 31,27,32,0,1,0
+setvl. 31,27,32,0,1,1
+setvl. 31,27,32,1,0,0
+setvl. 31,27,32,1,0,1
+setvl. 31,27,32,1,1,0
+setvl. 31,27,32,1,1,1
+setvl. 31,31,1,0,0,0
+setvl. 31,31,1,0,0,1
+setvl. 31,31,1,0,1,0
+setvl. 31,31,1,0,1,1
+setvl. 31,31,1,1,0,0
+setvl. 31,31,1,1,0,1
+setvl. 31,31,1,1,1,0
+setvl. 31,31,1,1,1,1
+setvl. 31,31,21,0,0,0
+setvl. 31,31,21,0,0,1
+setvl. 31,31,21,0,1,0
+setvl. 31,31,21,0,1,1
+setvl. 31,31,21,1,0,0
+setvl. 31,31,21,1,0,1
+setvl. 31,31,21,1,1,0
+setvl. 31,31,21,1,1,1
+setvl. 31,31,42,0,0,0
+setvl. 31,31,42,0,0,1
+setvl. 31,31,42,0,1,0
+setvl. 31,31,42,0,1,1
+setvl. 31,31,42,1,0,0
+setvl. 31,31,42,1,0,1
+setvl. 31,31,42,1,1,0
+setvl. 31,31,42,1,1,1
+setvl. 31,31,51,0,0,0
+setvl. 31,31,51,0,0,1
+setvl. 31,31,51,0,1,0
+setvl. 31,31,51,0,1,1
+setvl. 31,31,51,1,0,0
+setvl. 31,31,51,1,0,1
+setvl. 31,31,51,1,1,0
+setvl. 31,31,51,1,1,1
+setvl. 31,31,63,0,0,0
+setvl. 31,31,63,0,0,1
+setvl. 31,31,63,0,1,0
+setvl. 31,31,63,0,1,1
+setvl. 31,31,63,1,0,0
+setvl. 31,31,63,1,0,1
+setvl. 31,31,63,1,1,0
+setvl. 31,31,63,1,1,1
+setvl. 31,31,32,0,0,0
+setvl. 31,31,32,0,0,1
+setvl. 31,31,32,0,1,0
+setvl. 31,31,32,0,1,1
+setvl. 31,31,32,1,0,0
+setvl. 31,31,32,1,0,1
+setvl. 31,31,32,1,1,0
+setvl. 31,31,32,1,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d..0a34417820 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,26 @@ extract_thds (uint64_t insn,
return value;
}
+
+static uint64_t
+insert_svi (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value <= 0)
+ *errmsg = _("invalid SVi field");
+ return (insn | (((value - 1) & 0x3f) << 9));
+}
+
+static int64_t
+extract_svi (uint64_t insn ATTRIBUTE_UNUSED,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> 9) & 0x3f) + 1);
+}
+
\f
/* The operands table.
@@ -3825,6 +3845,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, insert_svi, extract_svi, 0 },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4726,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6763,6 +6802,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 3/5] ppc/svp64: support svstep instructions
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-06-21 11:51 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
` (3 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-21 11:51 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svstep.d | 128 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svstep.s | 120 +++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 3 +
4 files changed, 252 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cd4dd658ce..d4d06d587e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -155,3 +155,4 @@ run_dump_test "pr27676"
run_dump_test "raw"
run_dump_test "setvl"
+run_dump_test "svstep"
diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644
index 0000000000..772d7857e7
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,128 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 26 00 00 58 svstep r0,1,0
+ 4: 66 00 00 58 svstep r0,1,1
+ 8: 26 28 00 58 svstep r0,21,0
+ c: 66 28 00 58 svstep r0,21,1
+ 10: 26 52 00 58 svstep r0,42,0
+ 14: 66 52 00 58 svstep r0,42,1
+ 18: 26 64 00 58 svstep r0,51,0
+ 1c: 66 64 00 58 svstep r0,51,1
+ 20: 26 7c 00 58 svstep r0,63,0
+ 24: 66 7c 00 58 svstep r0,63,1
+ 28: 26 3e 00 58 svstep r0,32,0
+ 2c: 66 3e 00 58 svstep r0,32,1
+ 30: 26 00 40 59 svstep r10,1,0
+ 34: 66 00 40 59 svstep r10,1,1
+ 38: 26 28 40 59 svstep r10,21,0
+ 3c: 66 28 40 59 svstep r10,21,1
+ 40: 26 52 40 59 svstep r10,42,0
+ 44: 66 52 40 59 svstep r10,42,1
+ 48: 26 64 40 59 svstep r10,51,0
+ 4c: 66 64 40 59 svstep r10,51,1
+ 50: 26 7c 40 59 svstep r10,63,0
+ 54: 66 7c 40 59 svstep r10,63,1
+ 58: 26 3e 40 59 svstep r10,32,0
+ 5c: 66 3e 40 59 svstep r10,32,1
+ 60: 26 00 a0 5a svstep r21,1,0
+ 64: 66 00 a0 5a svstep r21,1,1
+ 68: 26 28 a0 5a svstep r21,21,0
+ 6c: 66 28 a0 5a svstep r21,21,1
+ 70: 26 52 a0 5a svstep r21,42,0
+ 74: 66 52 a0 5a svstep r21,42,1
+ 78: 26 64 a0 5a svstep r21,51,0
+ 7c: 66 64 a0 5a svstep r21,51,1
+ 80: 26 7c a0 5a svstep r21,63,0
+ 84: 66 7c a0 5a svstep r21,63,1
+ 88: 26 3e a0 5a svstep r21,32,0
+ 8c: 66 3e a0 5a svstep r21,32,1
+ 90: 26 00 60 5b svstep r27,1,0
+ 94: 66 00 60 5b svstep r27,1,1
+ 98: 26 28 60 5b svstep r27,21,0
+ 9c: 66 28 60 5b svstep r27,21,1
+ a0: 26 52 60 5b svstep r27,42,0
+ a4: 66 52 60 5b svstep r27,42,1
+ a8: 26 64 60 5b svstep r27,51,0
+ ac: 66 64 60 5b svstep r27,51,1
+ b0: 26 7c 60 5b svstep r27,63,0
+ b4: 66 7c 60 5b svstep r27,63,1
+ b8: 26 3e 60 5b svstep r27,32,0
+ bc: 66 3e 60 5b svstep r27,32,1
+ c0: 26 00 e0 5b svstep r31,1,0
+ c4: 66 00 e0 5b svstep r31,1,1
+ c8: 26 28 e0 5b svstep r31,21,0
+ cc: 66 28 e0 5b svstep r31,21,1
+ d0: 26 52 e0 5b svstep r31,42,0
+ d4: 66 52 e0 5b svstep r31,42,1
+ d8: 26 64 e0 5b svstep r31,51,0
+ dc: 66 64 e0 5b svstep r31,51,1
+ e0: 26 7c e0 5b svstep r31,63,0
+ e4: 66 7c e0 5b svstep r31,63,1
+ e8: 26 3e e0 5b svstep r31,32,0
+ ec: 66 3e e0 5b svstep r31,32,1
+ f0: 27 00 00 58 svstep\. r0,1,0
+ f4: 67 00 00 58 svstep\. r0,1,1
+ f8: 27 28 00 58 svstep\. r0,21,0
+ fc: 67 28 00 58 svstep\. r0,21,1
+ 100: 27 52 00 58 svstep\. r0,42,0
+ 104: 67 52 00 58 svstep\. r0,42,1
+ 108: 27 64 00 58 svstep\. r0,51,0
+ 10c: 67 64 00 58 svstep\. r0,51,1
+ 110: 27 7c 00 58 svstep\. r0,63,0
+ 114: 67 7c 00 58 svstep\. r0,63,1
+ 118: 27 3e 00 58 svstep\. r0,32,0
+ 11c: 67 3e 00 58 svstep\. r0,32,1
+ 120: 27 00 40 59 svstep\. r10,1,0
+ 124: 67 00 40 59 svstep\. r10,1,1
+ 128: 27 28 40 59 svstep\. r10,21,0
+ 12c: 67 28 40 59 svstep\. r10,21,1
+ 130: 27 52 40 59 svstep\. r10,42,0
+ 134: 67 52 40 59 svstep\. r10,42,1
+ 138: 27 64 40 59 svstep\. r10,51,0
+ 13c: 67 64 40 59 svstep\. r10,51,1
+ 140: 27 7c 40 59 svstep\. r10,63,0
+ 144: 67 7c 40 59 svstep\. r10,63,1
+ 148: 27 3e 40 59 svstep\. r10,32,0
+ 14c: 67 3e 40 59 svstep\. r10,32,1
+ 150: 27 00 a0 5a svstep\. r21,1,0
+ 154: 67 00 a0 5a svstep\. r21,1,1
+ 158: 27 28 a0 5a svstep\. r21,21,0
+ 15c: 67 28 a0 5a svstep\. r21,21,1
+ 160: 27 52 a0 5a svstep\. r21,42,0
+ 164: 67 52 a0 5a svstep\. r21,42,1
+ 168: 27 64 a0 5a svstep\. r21,51,0
+ 16c: 67 64 a0 5a svstep\. r21,51,1
+ 170: 27 7c a0 5a svstep\. r21,63,0
+ 174: 67 7c a0 5a svstep\. r21,63,1
+ 178: 27 3e a0 5a svstep\. r21,32,0
+ 17c: 67 3e a0 5a svstep\. r21,32,1
+ 180: 27 00 60 5b svstep\. r27,1,0
+ 184: 67 00 60 5b svstep\. r27,1,1
+ 188: 27 28 60 5b svstep\. r27,21,0
+ 18c: 67 28 60 5b svstep\. r27,21,1
+ 190: 27 52 60 5b svstep\. r27,42,0
+ 194: 67 52 60 5b svstep\. r27,42,1
+ 198: 27 64 60 5b svstep\. r27,51,0
+ 19c: 67 64 60 5b svstep\. r27,51,1
+ 1a0: 27 7c 60 5b svstep\. r27,63,0
+ 1a4: 67 7c 60 5b svstep\. r27,63,1
+ 1a8: 27 3e 60 5b svstep\. r27,32,0
+ 1ac: 67 3e 60 5b svstep\. r27,32,1
+ 1b0: 27 00 e0 5b svstep\. r31,1,0
+ 1b4: 67 00 e0 5b svstep\. r31,1,1
+ 1b8: 27 28 e0 5b svstep\. r31,21,0
+ 1bc: 67 28 e0 5b svstep\. r31,21,1
+ 1c0: 27 52 e0 5b svstep\. r31,42,0
+ 1c4: 67 52 e0 5b svstep\. r31,42,1
+ 1c8: 27 64 e0 5b svstep\. r31,51,0
+ 1cc: 67 64 e0 5b svstep\. r31,51,1
+ 1d0: 27 7c e0 5b svstep\. r31,63,0
+ 1d4: 67 7c e0 5b svstep\. r31,63,1
+ 1d8: 27 3e e0 5b svstep\. r31,32,0
+ 1dc: 67 3e e0 5b svstep\. r31,32,1
diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644
index 0000000000..f41547ad63
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,120 @@
+svstep 0,1,0
+svstep 0,1,1
+svstep 0,21,0
+svstep 0,21,1
+svstep 0,42,0
+svstep 0,42,1
+svstep 0,51,0
+svstep 0,51,1
+svstep 0,63,0
+svstep 0,63,1
+svstep 0,32,0
+svstep 0,32,1
+svstep 10,1,0
+svstep 10,1,1
+svstep 10,21,0
+svstep 10,21,1
+svstep 10,42,0
+svstep 10,42,1
+svstep 10,51,0
+svstep 10,51,1
+svstep 10,63,0
+svstep 10,63,1
+svstep 10,32,0
+svstep 10,32,1
+svstep 21,1,0
+svstep 21,1,1
+svstep 21,21,0
+svstep 21,21,1
+svstep 21,42,0
+svstep 21,42,1
+svstep 21,51,0
+svstep 21,51,1
+svstep 21,63,0
+svstep 21,63,1
+svstep 21,32,0
+svstep 21,32,1
+svstep 27,1,0
+svstep 27,1,1
+svstep 27,21,0
+svstep 27,21,1
+svstep 27,42,0
+svstep 27,42,1
+svstep 27,51,0
+svstep 27,51,1
+svstep 27,63,0
+svstep 27,63,1
+svstep 27,32,0
+svstep 27,32,1
+svstep 31,1,0
+svstep 31,1,1
+svstep 31,21,0
+svstep 31,21,1
+svstep 31,42,0
+svstep 31,42,1
+svstep 31,51,0
+svstep 31,51,1
+svstep 31,63,0
+svstep 31,63,1
+svstep 31,32,0
+svstep 31,32,1
+svstep. 0,1,0
+svstep. 0,1,1
+svstep. 0,21,0
+svstep. 0,21,1
+svstep. 0,42,0
+svstep. 0,42,1
+svstep. 0,51,0
+svstep. 0,51,1
+svstep. 0,63,0
+svstep. 0,63,1
+svstep. 0,32,0
+svstep. 0,32,1
+svstep. 10,1,0
+svstep. 10,1,1
+svstep. 10,21,0
+svstep. 10,21,1
+svstep. 10,42,0
+svstep. 10,42,1
+svstep. 10,51,0
+svstep. 10,51,1
+svstep. 10,63,0
+svstep. 10,63,1
+svstep. 10,32,0
+svstep. 10,32,1
+svstep. 21,1,0
+svstep. 21,1,1
+svstep. 21,21,0
+svstep. 21,21,1
+svstep. 21,42,0
+svstep. 21,42,1
+svstep. 21,51,0
+svstep. 21,51,1
+svstep. 21,63,0
+svstep. 21,63,1
+svstep. 21,32,0
+svstep. 21,32,1
+svstep. 27,1,0
+svstep. 27,1,1
+svstep. 27,21,0
+svstep. 27,21,1
+svstep. 27,42,0
+svstep. 27,42,1
+svstep. 27,51,0
+svstep. 27,51,1
+svstep. 27,63,0
+svstep. 27,63,1
+svstep. 27,32,0
+svstep. 27,32,1
+svstep. 31,1,0
+svstep. 31,1,1
+svstep. 31,21,0
+svstep. 31,21,1
+svstep. 31,42,0
+svstep. 31,42,1
+svstep. 31,51,0
+svstep. 31,51,1
+svstep. 31,63,0
+svstep. 31,63,1
+svstep. 31,32,0
+svstep. 31,32,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 0a34417820..b053a15125 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6802,6 +6802,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 4/5] ppc/svp64: support svshape instruction
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
` (2 preceding siblings ...)
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
@ 2022-06-21 11:51 ` Dmitry Selyutin
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
` (2 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-21 11:51 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svshape.d | 1736 +++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/svshape.s | 1728 ++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 93 ++
4 files changed, 3558 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d4d06d587e..04082439bb 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..e78784bed1
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,1736 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 19 00 00 58 svshape 1,1,1,0,0
+ 4: 59 00 00 58 svshape 1,1,1,0,1
+ 8: 99 02 00 58 svshape 1,1,1,5,0
+ c: d9 02 00 58 svshape 1,1,1,5,1
+ 10: 19 05 00 58 svshape 1,1,1,10,0
+ 14: 59 05 00 58 svshape 1,1,1,10,1
+ 18: 99 07 00 58 svshape 1,1,1,15,0
+ 1c: d9 07 00 58 svshape 1,1,1,15,1
+ 20: 19 48 00 58 svshape 1,1,10,0,0
+ 24: 59 48 00 58 svshape 1,1,10,0,1
+ 28: 99 4a 00 58 svshape 1,1,10,5,0
+ 2c: d9 4a 00 58 svshape 1,1,10,5,1
+ 30: 19 4d 00 58 svshape 1,1,10,10,0
+ 34: 59 4d 00 58 svshape 1,1,10,10,1
+ 38: 99 4f 00 58 svshape 1,1,10,15,0
+ 3c: d9 4f 00 58 svshape 1,1,10,15,1
+ 40: 19 a0 00 58 svshape 1,1,21,0,0
+ 44: 59 a0 00 58 svshape 1,1,21,0,1
+ 48: 99 a2 00 58 svshape 1,1,21,5,0
+ 4c: d9 a2 00 58 svshape 1,1,21,5,1
+ 50: 19 a5 00 58 svshape 1,1,21,10,0
+ 54: 59 a5 00 58 svshape 1,1,21,10,1
+ 58: 99 a7 00 58 svshape 1,1,21,15,0
+ 5c: d9 a7 00 58 svshape 1,1,21,15,1
+ 60: 19 d0 00 58 svshape 1,1,27,0,0
+ 64: 59 d0 00 58 svshape 1,1,27,0,1
+ 68: 99 d2 00 58 svshape 1,1,27,5,0
+ 6c: d9 d2 00 58 svshape 1,1,27,5,1
+ 70: 19 d5 00 58 svshape 1,1,27,10,0
+ 74: 59 d5 00 58 svshape 1,1,27,10,1
+ 78: 99 d7 00 58 svshape 1,1,27,15,0
+ 7c: d9 d7 00 58 svshape 1,1,27,15,1
+ 80: 19 f0 00 58 svshape 1,1,31,0,0
+ 84: 59 f0 00 58 svshape 1,1,31,0,1
+ 88: 99 f2 00 58 svshape 1,1,31,5,0
+ 8c: d9 f2 00 58 svshape 1,1,31,5,1
+ 90: 19 f5 00 58 svshape 1,1,31,10,0
+ 94: 59 f5 00 58 svshape 1,1,31,10,1
+ 98: 99 f7 00 58 svshape 1,1,31,15,0
+ 9c: d9 f7 00 58 svshape 1,1,31,15,1
+ a0: 19 78 00 58 svshape 1,1,16,0,0
+ a4: 59 78 00 58 svshape 1,1,16,0,1
+ a8: 99 7a 00 58 svshape 1,1,16,5,0
+ ac: d9 7a 00 58 svshape 1,1,16,5,1
+ b0: 19 7d 00 58 svshape 1,1,16,10,0
+ b4: 59 7d 00 58 svshape 1,1,16,10,1
+ b8: 99 7f 00 58 svshape 1,1,16,15,0
+ bc: d9 7f 00 58 svshape 1,1,16,15,1
+ c0: 19 00 09 58 svshape 1,10,1,0,0
+ c4: 59 00 09 58 svshape 1,10,1,0,1
+ c8: 99 02 09 58 svshape 1,10,1,5,0
+ cc: d9 02 09 58 svshape 1,10,1,5,1
+ d0: 19 05 09 58 svshape 1,10,1,10,0
+ d4: 59 05 09 58 svshape 1,10,1,10,1
+ d8: 99 07 09 58 svshape 1,10,1,15,0
+ dc: d9 07 09 58 svshape 1,10,1,15,1
+ e0: 19 48 09 58 svshape 1,10,10,0,0
+ e4: 59 48 09 58 svshape 1,10,10,0,1
+ e8: 99 4a 09 58 svshape 1,10,10,5,0
+ ec: d9 4a 09 58 svshape 1,10,10,5,1
+ f0: 19 4d 09 58 svshape 1,10,10,10,0
+ f4: 59 4d 09 58 svshape 1,10,10,10,1
+ f8: 99 4f 09 58 svshape 1,10,10,15,0
+ fc: d9 4f 09 58 svshape 1,10,10,15,1
+ 100: 19 a0 09 58 svshape 1,10,21,0,0
+ 104: 59 a0 09 58 svshape 1,10,21,0,1
+ 108: 99 a2 09 58 svshape 1,10,21,5,0
+ 10c: d9 a2 09 58 svshape 1,10,21,5,1
+ 110: 19 a5 09 58 svshape 1,10,21,10,0
+ 114: 59 a5 09 58 svshape 1,10,21,10,1
+ 118: 99 a7 09 58 svshape 1,10,21,15,0
+ 11c: d9 a7 09 58 svshape 1,10,21,15,1
+ 120: 19 d0 09 58 svshape 1,10,27,0,0
+ 124: 59 d0 09 58 svshape 1,10,27,0,1
+ 128: 99 d2 09 58 svshape 1,10,27,5,0
+ 12c: d9 d2 09 58 svshape 1,10,27,5,1
+ 130: 19 d5 09 58 svshape 1,10,27,10,0
+ 134: 59 d5 09 58 svshape 1,10,27,10,1
+ 138: 99 d7 09 58 svshape 1,10,27,15,0
+ 13c: d9 d7 09 58 svshape 1,10,27,15,1
+ 140: 19 f0 09 58 svshape 1,10,31,0,0
+ 144: 59 f0 09 58 svshape 1,10,31,0,1
+ 148: 99 f2 09 58 svshape 1,10,31,5,0
+ 14c: d9 f2 09 58 svshape 1,10,31,5,1
+ 150: 19 f5 09 58 svshape 1,10,31,10,0
+ 154: 59 f5 09 58 svshape 1,10,31,10,1
+ 158: 99 f7 09 58 svshape 1,10,31,15,0
+ 15c: d9 f7 09 58 svshape 1,10,31,15,1
+ 160: 19 78 09 58 svshape 1,10,16,0,0
+ 164: 59 78 09 58 svshape 1,10,16,0,1
+ 168: 99 7a 09 58 svshape 1,10,16,5,0
+ 16c: d9 7a 09 58 svshape 1,10,16,5,1
+ 170: 19 7d 09 58 svshape 1,10,16,10,0
+ 174: 59 7d 09 58 svshape 1,10,16,10,1
+ 178: 99 7f 09 58 svshape 1,10,16,15,0
+ 17c: d9 7f 09 58 svshape 1,10,16,15,1
+ 180: 19 00 14 58 svshape 1,21,1,0,0
+ 184: 59 00 14 58 svshape 1,21,1,0,1
+ 188: 99 02 14 58 svshape 1,21,1,5,0
+ 18c: d9 02 14 58 svshape 1,21,1,5,1
+ 190: 19 05 14 58 svshape 1,21,1,10,0
+ 194: 59 05 14 58 svshape 1,21,1,10,1
+ 198: 99 07 14 58 svshape 1,21,1,15,0
+ 19c: d9 07 14 58 svshape 1,21,1,15,1
+ 1a0: 19 48 14 58 svshape 1,21,10,0,0
+ 1a4: 59 48 14 58 svshape 1,21,10,0,1
+ 1a8: 99 4a 14 58 svshape 1,21,10,5,0
+ 1ac: d9 4a 14 58 svshape 1,21,10,5,1
+ 1b0: 19 4d 14 58 svshape 1,21,10,10,0
+ 1b4: 59 4d 14 58 svshape 1,21,10,10,1
+ 1b8: 99 4f 14 58 svshape 1,21,10,15,0
+ 1bc: d9 4f 14 58 svshape 1,21,10,15,1
+ 1c0: 19 a0 14 58 svshape 1,21,21,0,0
+ 1c4: 59 a0 14 58 svshape 1,21,21,0,1
+ 1c8: 99 a2 14 58 svshape 1,21,21,5,0
+ 1cc: d9 a2 14 58 svshape 1,21,21,5,1
+ 1d0: 19 a5 14 58 svshape 1,21,21,10,0
+ 1d4: 59 a5 14 58 svshape 1,21,21,10,1
+ 1d8: 99 a7 14 58 svshape 1,21,21,15,0
+ 1dc: d9 a7 14 58 svshape 1,21,21,15,1
+ 1e0: 19 d0 14 58 svshape 1,21,27,0,0
+ 1e4: 59 d0 14 58 svshape 1,21,27,0,1
+ 1e8: 99 d2 14 58 svshape 1,21,27,5,0
+ 1ec: d9 d2 14 58 svshape 1,21,27,5,1
+ 1f0: 19 d5 14 58 svshape 1,21,27,10,0
+ 1f4: 59 d5 14 58 svshape 1,21,27,10,1
+ 1f8: 99 d7 14 58 svshape 1,21,27,15,0
+ 1fc: d9 d7 14 58 svshape 1,21,27,15,1
+ 200: 19 f0 14 58 svshape 1,21,31,0,0
+ 204: 59 f0 14 58 svshape 1,21,31,0,1
+ 208: 99 f2 14 58 svshape 1,21,31,5,0
+ 20c: d9 f2 14 58 svshape 1,21,31,5,1
+ 210: 19 f5 14 58 svshape 1,21,31,10,0
+ 214: 59 f5 14 58 svshape 1,21,31,10,1
+ 218: 99 f7 14 58 svshape 1,21,31,15,0
+ 21c: d9 f7 14 58 svshape 1,21,31,15,1
+ 220: 19 78 14 58 svshape 1,21,16,0,0
+ 224: 59 78 14 58 svshape 1,21,16,0,1
+ 228: 99 7a 14 58 svshape 1,21,16,5,0
+ 22c: d9 7a 14 58 svshape 1,21,16,5,1
+ 230: 19 7d 14 58 svshape 1,21,16,10,0
+ 234: 59 7d 14 58 svshape 1,21,16,10,1
+ 238: 99 7f 14 58 svshape 1,21,16,15,0
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diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..6a0984aa5f
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,1728 @@
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+svshape 31,16,16,5,0
+svshape 31,16,16,5,1
+svshape 31,16,16,10,0
+svshape 31,16,16,10,1
+svshape 31,16,16,15,0
+svshape 31,16,16,15,1
+svshape 16,1,1,0,0
+svshape 16,1,1,0,1
+svshape 16,1,1,5,0
+svshape 16,1,1,5,1
+svshape 16,1,1,10,0
+svshape 16,1,1,10,1
+svshape 16,1,1,15,0
+svshape 16,1,1,15,1
+svshape 16,1,10,0,0
+svshape 16,1,10,0,1
+svshape 16,1,10,5,0
+svshape 16,1,10,5,1
+svshape 16,1,10,10,0
+svshape 16,1,10,10,1
+svshape 16,1,10,15,0
+svshape 16,1,10,15,1
+svshape 16,1,21,0,0
+svshape 16,1,21,0,1
+svshape 16,1,21,5,0
+svshape 16,1,21,5,1
+svshape 16,1,21,10,0
+svshape 16,1,21,10,1
+svshape 16,1,21,15,0
+svshape 16,1,21,15,1
+svshape 16,1,27,0,0
+svshape 16,1,27,0,1
+svshape 16,1,27,5,0
+svshape 16,1,27,5,1
+svshape 16,1,27,10,0
+svshape 16,1,27,10,1
+svshape 16,1,27,15,0
+svshape 16,1,27,15,1
+svshape 16,1,31,0,0
+svshape 16,1,31,0,1
+svshape 16,1,31,5,0
+svshape 16,1,31,5,1
+svshape 16,1,31,10,0
+svshape 16,1,31,10,1
+svshape 16,1,31,15,0
+svshape 16,1,31,15,1
+svshape 16,1,16,0,0
+svshape 16,1,16,0,1
+svshape 16,1,16,5,0
+svshape 16,1,16,5,1
+svshape 16,1,16,10,0
+svshape 16,1,16,10,1
+svshape 16,1,16,15,0
+svshape 16,1,16,15,1
+svshape 16,10,1,0,0
+svshape 16,10,1,0,1
+svshape 16,10,1,5,0
+svshape 16,10,1,5,1
+svshape 16,10,1,10,0
+svshape 16,10,1,10,1
+svshape 16,10,1,15,0
+svshape 16,10,1,15,1
+svshape 16,10,10,0,0
+svshape 16,10,10,0,1
+svshape 16,10,10,5,0
+svshape 16,10,10,5,1
+svshape 16,10,10,10,0
+svshape 16,10,10,10,1
+svshape 16,10,10,15,0
+svshape 16,10,10,15,1
+svshape 16,10,21,0,0
+svshape 16,10,21,0,1
+svshape 16,10,21,5,0
+svshape 16,10,21,5,1
+svshape 16,10,21,10,0
+svshape 16,10,21,10,1
+svshape 16,10,21,15,0
+svshape 16,10,21,15,1
+svshape 16,10,27,0,0
+svshape 16,10,27,0,1
+svshape 16,10,27,5,0
+svshape 16,10,27,5,1
+svshape 16,10,27,10,0
+svshape 16,10,27,10,1
+svshape 16,10,27,15,0
+svshape 16,10,27,15,1
+svshape 16,10,31,0,0
+svshape 16,10,31,0,1
+svshape 16,10,31,5,0
+svshape 16,10,31,5,1
+svshape 16,10,31,10,0
+svshape 16,10,31,10,1
+svshape 16,10,31,15,0
+svshape 16,10,31,15,1
+svshape 16,10,16,0,0
+svshape 16,10,16,0,1
+svshape 16,10,16,5,0
+svshape 16,10,16,5,1
+svshape 16,10,16,10,0
+svshape 16,10,16,10,1
+svshape 16,10,16,15,0
+svshape 16,10,16,15,1
+svshape 16,21,1,0,0
+svshape 16,21,1,0,1
+svshape 16,21,1,5,0
+svshape 16,21,1,5,1
+svshape 16,21,1,10,0
+svshape 16,21,1,10,1
+svshape 16,21,1,15,0
+svshape 16,21,1,15,1
+svshape 16,21,10,0,0
+svshape 16,21,10,0,1
+svshape 16,21,10,5,0
+svshape 16,21,10,5,1
+svshape 16,21,10,10,0
+svshape 16,21,10,10,1
+svshape 16,21,10,15,0
+svshape 16,21,10,15,1
+svshape 16,21,21,0,0
+svshape 16,21,21,0,1
+svshape 16,21,21,5,0
+svshape 16,21,21,5,1
+svshape 16,21,21,10,0
+svshape 16,21,21,10,1
+svshape 16,21,21,15,0
+svshape 16,21,21,15,1
+svshape 16,21,27,0,0
+svshape 16,21,27,0,1
+svshape 16,21,27,5,0
+svshape 16,21,27,5,1
+svshape 16,21,27,10,0
+svshape 16,21,27,10,1
+svshape 16,21,27,15,0
+svshape 16,21,27,15,1
+svshape 16,21,31,0,0
+svshape 16,21,31,0,1
+svshape 16,21,31,5,0
+svshape 16,21,31,5,1
+svshape 16,21,31,10,0
+svshape 16,21,31,10,1
+svshape 16,21,31,15,0
+svshape 16,21,31,15,1
+svshape 16,21,16,0,0
+svshape 16,21,16,0,1
+svshape 16,21,16,5,0
+svshape 16,21,16,5,1
+svshape 16,21,16,10,0
+svshape 16,21,16,10,1
+svshape 16,21,16,15,0
+svshape 16,21,16,15,1
+svshape 16,27,1,0,0
+svshape 16,27,1,0,1
+svshape 16,27,1,5,0
+svshape 16,27,1,5,1
+svshape 16,27,1,10,0
+svshape 16,27,1,10,1
+svshape 16,27,1,15,0
+svshape 16,27,1,15,1
+svshape 16,27,10,0,0
+svshape 16,27,10,0,1
+svshape 16,27,10,5,0
+svshape 16,27,10,5,1
+svshape 16,27,10,10,0
+svshape 16,27,10,10,1
+svshape 16,27,10,15,0
+svshape 16,27,10,15,1
+svshape 16,27,21,0,0
+svshape 16,27,21,0,1
+svshape 16,27,21,5,0
+svshape 16,27,21,5,1
+svshape 16,27,21,10,0
+svshape 16,27,21,10,1
+svshape 16,27,21,15,0
+svshape 16,27,21,15,1
+svshape 16,27,27,0,0
+svshape 16,27,27,0,1
+svshape 16,27,27,5,0
+svshape 16,27,27,5,1
+svshape 16,27,27,10,0
+svshape 16,27,27,10,1
+svshape 16,27,27,15,0
+svshape 16,27,27,15,1
+svshape 16,27,31,0,0
+svshape 16,27,31,0,1
+svshape 16,27,31,5,0
+svshape 16,27,31,5,1
+svshape 16,27,31,10,0
+svshape 16,27,31,10,1
+svshape 16,27,31,15,0
+svshape 16,27,31,15,1
+svshape 16,27,16,0,0
+svshape 16,27,16,0,1
+svshape 16,27,16,5,0
+svshape 16,27,16,5,1
+svshape 16,27,16,10,0
+svshape 16,27,16,10,1
+svshape 16,27,16,15,0
+svshape 16,27,16,15,1
+svshape 16,31,1,0,0
+svshape 16,31,1,0,1
+svshape 16,31,1,5,0
+svshape 16,31,1,5,1
+svshape 16,31,1,10,0
+svshape 16,31,1,10,1
+svshape 16,31,1,15,0
+svshape 16,31,1,15,1
+svshape 16,31,10,0,0
+svshape 16,31,10,0,1
+svshape 16,31,10,5,0
+svshape 16,31,10,5,1
+svshape 16,31,10,10,0
+svshape 16,31,10,10,1
+svshape 16,31,10,15,0
+svshape 16,31,10,15,1
+svshape 16,31,21,0,0
+svshape 16,31,21,0,1
+svshape 16,31,21,5,0
+svshape 16,31,21,5,1
+svshape 16,31,21,10,0
+svshape 16,31,21,10,1
+svshape 16,31,21,15,0
+svshape 16,31,21,15,1
+svshape 16,31,27,0,0
+svshape 16,31,27,0,1
+svshape 16,31,27,5,0
+svshape 16,31,27,5,1
+svshape 16,31,27,10,0
+svshape 16,31,27,10,1
+svshape 16,31,27,15,0
+svshape 16,31,27,15,1
+svshape 16,31,31,0,0
+svshape 16,31,31,0,1
+svshape 16,31,31,5,0
+svshape 16,31,31,5,1
+svshape 16,31,31,10,0
+svshape 16,31,31,10,1
+svshape 16,31,31,15,0
+svshape 16,31,31,15,1
+svshape 16,31,16,0,0
+svshape 16,31,16,0,1
+svshape 16,31,16,5,0
+svshape 16,31,16,5,1
+svshape 16,31,16,10,0
+svshape 16,31,16,10,1
+svshape 16,31,16,15,0
+svshape 16,31,16,15,1
+svshape 16,16,1,0,0
+svshape 16,16,1,0,1
+svshape 16,16,1,5,0
+svshape 16,16,1,5,1
+svshape 16,16,1,10,0
+svshape 16,16,1,10,1
+svshape 16,16,1,15,0
+svshape 16,16,1,15,1
+svshape 16,16,10,0,0
+svshape 16,16,10,0,1
+svshape 16,16,10,5,0
+svshape 16,16,10,5,1
+svshape 16,16,10,10,0
+svshape 16,16,10,10,1
+svshape 16,16,10,15,0
+svshape 16,16,10,15,1
+svshape 16,16,21,0,0
+svshape 16,16,21,0,1
+svshape 16,16,21,5,0
+svshape 16,16,21,5,1
+svshape 16,16,21,10,0
+svshape 16,16,21,10,1
+svshape 16,16,21,15,0
+svshape 16,16,21,15,1
+svshape 16,16,27,0,0
+svshape 16,16,27,0,1
+svshape 16,16,27,5,0
+svshape 16,16,27,5,1
+svshape 16,16,27,10,0
+svshape 16,16,27,10,1
+svshape 16,16,27,15,0
+svshape 16,16,27,15,1
+svshape 16,16,31,0,0
+svshape 16,16,31,0,1
+svshape 16,16,31,5,0
+svshape 16,16,31,5,1
+svshape 16,16,31,10,0
+svshape 16,16,31,10,1
+svshape 16,16,31,15,0
+svshape 16,16,31,15,1
+svshape 16,16,16,0,0
+svshape 16,16,16,0,1
+svshape 16,16,16,5,0
+svshape 16,16,16,5,1
+svshape 16,16,16,10,0
+svshape 16,16,16,10,1
+svshape 16,16,16,15,0
+svshape 16,16,16,15,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index b053a15125..f5fd444ea3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2739,6 +2739,76 @@ extract_svi (uint64_t insn ATTRIBUTE_UNUSED,
return (((insn >> 9) & 0x3f) + 1);
}
+static uint64_t
+insert_svm (uint64_t insn,
+ int64_t value,
+ unsigned int shift,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return (insn | (((value - 1) & 0x1f) << shift));
+}
+
+static uint64_t
+insert_svxd (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_svm (insn, value, 21, dialect, errmsg);
+}
+
+static uint64_t
+insert_svyd (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_svm (insn, value, 16, dialect, errmsg);
+}
+
+static uint64_t
+insert_svzd (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg)
+{
+ return insert_svm (insn, value, 11, dialect, errmsg);
+}
+
+static int64_t
+extract_svm (uint64_t insn,
+ unsigned int shift,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> shift) & 0x1f) + 1);
+}
+
+static int64_t
+extract_svxd (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_svm (insn, 21, dialect, invalid);
+}
+
+static int64_t
+extract_svyd (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_svm (insn, 16, dialect, invalid);
+}
+
+static int64_t
+extract_svzd (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid)
+{
+ return extract_svm (insn, 11, dialect, invalid);
+}
+
\f
/* The operands table.
@@ -3857,6 +3927,21 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
{ 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+ { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+ { 0x1f, 21, insert_svxd, extract_svxd, 0 },
+
+#define SVyd SVxd + 1
+ { 0x1f, 16, insert_svyd, extract_svyd, 0 },
+
+#define SVzd SVyd + 1
+ { 0x1f, 11, insert_svzd, extract_svzd, 0 },
+
+#define SVRMf SVzd + 1
+ { 0xf, 7, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4733,6 +4818,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(rc)) & 1))
#define SVL_MASK SVL (0x3f, 0x1f, 1)
+/* An SVM form instruction. */
+#define SVM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK SVM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6805,6 +6896,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVRMf, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH 0/5] ppc/svp64: support SVP64 and its first insns
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
@ 2022-06-21 11:55 ` Dmitry Selyutin
0 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-21 11:55 UTC (permalink / raw)
To: Alan Modra; +Cc: binutils, Luke Kenneth Casson Leighton
On Mon, Jun 20, 2022 at 2:50 AM Alan Modra <amodra@gmail.com> wrote:
> These all look good to me, and can be pushed when your copyright
> assignment is complete.
Still no news about it. We have contacted fst-records at GNU and
copyright-clerk at FSF, no reply yet.
> The only review comment I have is that
> #define SVme TO
> would be better for maintenance if placed with the TO definition, so
> that someone doesn't change the TO entry without realising they are
> also changing things for SVme. Similarly for the other aliases you
> define.
I've chosen the approach in patches since it made tracking arguments
somewhat simpler. Anyway, I totally agree with your rationale, I've
just submitted the updated patch to the mailing list.
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 2/5] ppc/svp64: support setvl instructions
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-06-21 18:25 ` Peter Bergner
2022-06-21 18:39 ` Peter Bergner
0 siblings, 1 reply; 62+ messages in thread
From: Peter Bergner @ 2022-06-21 18:25 UTC (permalink / raw)
To: Dmitry Selyutin, binutils; +Cc: Luke Kenneth Casson Leighton, Alan Modra
One or more of the following files ( byte-swap-test.pl ) violates IBM policy and all attachment(s) have been removed from the message.
**********************************************************************
On 6/21/22 6:51 AM, Dmitry Selyutin via Binutils wrote:
> + 0: 36 00 00 58 setvl r0,r0,1,0,0,0
> + 4: 36 01 00 58 setvl r0,r0,1,0,0,1
> + 8: b6 00 00 58 setvl r0,r0,1,0,1,0
> + c: b6 01 00 58 setvl r0,r0,1,0,1,1
> + 10: 76 00 00 58 setvl r0,r0,1,1,0,0
> + 14: 76 01 00 58 setvl r0,r0,1,1,0,1
I have learned that not specifying the exact offset in the foo.d file is
beneficial when you want to make changes to that file in the future,
especially if you want to add a new instruction test in the beginning
or middle of the test. If you do that, all of the offsets for the
following tests will change and your patch will be LARGE. The offset
is really not important, so you don't need it. I recommend just using:
.*:
...for the offset of all of the instructions. It makes adding new test
lines much easier for the patch reviewer! :-)
Secondly, ppc is a bi-endian architecture and I assume libre-soc is as well?
If so, I recommend following what Alan and I have done with the Power server
tests (eg, power10.d) and accept the encoding as both big or little endian.
Taking both of those suggestions on the snipit from setvl.d, you'd have:
.*: (36 00 00 58|58 00 00 36) setvl r0,r0,1,0,0,0
.*: (36 01 00 58|58 00 01 36) setvl r0,r0,1,0,0,1
.*: (b6 00 00 58|58 00 00 b6) setvl r0,r0,1,0,1,0
.*: (b6 01 00 58|58 00 01 b6) setvl r0,r0,1,0,1,1
.*: (76 00 00 58|58 00 00 76) setvl r0,r0,1,1,0,0
.*: (76 01 00 58|58 00 01 76) setvl r0,r0,1,1,0,1
We also place a "#pass" on the last line of the foo.d file which fixes
some issue which I can't remember off hand. Alan, can you remind me/us
why we place that there? I've attached a hackish perl script that will
take an "objdump -dr setvl.o" output and convert it into a setvl.d test
file for you. It'll create lines like the above for you. You do need
to verify that your objdump output is correct though! :-)
You'll also need a ChangeLog entry for these changes before you can push
your commit.
Peter
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 2/5] ppc/svp64: support setvl instructions
2022-06-21 18:25 ` Peter Bergner
@ 2022-06-21 18:39 ` Peter Bergner
0 siblings, 0 replies; 62+ messages in thread
From: Peter Bergner @ 2022-06-21 18:39 UTC (permalink / raw)
To: Dmitry Selyutin, binutils; +Cc: Luke Kenneth Casson Leighton, Alan Modra
On 6/21/22 1:25 PM, Peter Bergner via Binutils wrote:
> One or more of the following files ( byte-swap-test.pl ) violates ...
WT*? :-(
Here it is inline.
Peter
#!/usr/bin/perl -w
use File::Basename;
use FileHandle;
use strict;
die "Usage: ", basename ($0), " <asm file>\n" unless (@ARGV);
my $file = shift ();
my $fh = new FileHandle;
$fh->open ($file) or
die "Error opening '$file' for reading: $!\n";
print "#as: -m<cpu>\n",
"#objdump: -dr -M<cpu>\n",
"#name: <CPU> tests\n";
my $found = 0;
while (my $insn = <$fh>)
{
chomp ($insn);
if ($insn =~ m/^.*:\W+file format.*/)
{
print ".*\n";
}
elsif ($insn =~ m/^[0-9a-fA-F]+ <([^>]+)>:(.*)/)
{
print "0+0 <$1>:$2\n";
last;
}
else
{
$insn =~ s#\.#\\\.#g;
$insn =~ s#\(#\\\(#g;
$insn =~ s#\)#\\\)#g;
print "$insn\n";
}
}
while (my $insn = <$fh>)
{
chomp ($insn);
if ($insn =~ m/^\W*([0-9a-fA-F]+):\t([0-9a-f][0-9a-f]) ([0-9a-f][0-9a-f]) ([0-9a-f][0-9a-f]) ([0-9a-f][0-9a-f])(.*)/)
{
my ($offset,$b0,$b1,$b2,$b3,$end) = ($1,$2,$3,$4,$5,$6);
$offset = '.*';
$end =~ s#\.#\\\.#g;
$end =~ s#\(#\\\(#g;
$end =~ s#\)#\\\)#g;
$end =~ s#\+#\\\+#g;
$end =~ s#\*#\\\*#g;
$insn = sprintf ("%s:\t($b0 $b1 $b2 $b3|$b3 $b2 $b1 $b0)$end", $offset);
}
elsif ($insn =~ m/^\s+[0-9a-fA-F]+: R_PPC64_.*/)
{
$insn =~ s#R_PPC64_#R_PPC\(|64\)_#g;
}
print "$insn\n";
}
print "#pass\n";
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
` (3 preceding siblings ...)
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
@ 2022-06-22 6:41 ` Jan Beulich
2022-06-22 6:44 ` Jan Beulich
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
6 siblings, 0 replies; 62+ messages in thread
From: Jan Beulich @ 2022-06-22 6:41 UTC (permalink / raw)
To: Dmitry Selyutin; +Cc: Luke Kenneth Casson Leighton, binutils
On 21.06.2022 13:51, Dmitry Selyutin via Binutils wrote:
> Changes since v1:
> - Aliased instruction fields now appear after the original ones.
>
> Dmitry Selyutin (5):
> ppc/svp64: support LibreSOC architecture
> ppc/svp64: support setvl instructions
> ppc/svp64: support svstep instructions
> ppc/svp64: support svshape instruction
> ppc/svp64: support svremap instruction
Btw neither my inbox nor the list archive have patch 5, with the same
already having been the case for v1.
Jan
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
` (4 preceding siblings ...)
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
@ 2022-06-22 6:44 ` Jan Beulich
2022-06-22 6:57 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
6 siblings, 1 reply; 62+ messages in thread
From: Jan Beulich @ 2022-06-22 6:44 UTC (permalink / raw)
To: Dmitry Selyutin; +Cc: Luke Kenneth Casson Leighton, binutils
On 21.06.2022 13:51, Dmitry Selyutin via Binutils wrote:
> Changes since v1:
> - Aliased instruction fields now appear after the original ones.
One more remark: Neither here nor in the individual patches you have
much of a (in fact any) description. I think at the very least you
want to help people by supplying a link to the spec.
Jan
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns
2022-06-22 6:44 ` Jan Beulich
@ 2022-06-22 6:57 ` Dmitry Selyutin
0 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-22 6:57 UTC (permalink / raw)
To: Jan Beulich; +Cc: Luke Kenneth Casson Leighton, binutils
On Wed, Jun 22, 2022, 09:44 Jan Beulich <jbeulich@suse.com> wrote:
> One more remark: Neither here nor in the individual patches you have
> much of a (in fact any) description. I think at the very least you
> want to help people by supplying a link to the spec.
>
Thanks for the remark! I'll update the very first patch with links and
overall description. Also I'll supply the description for each instruction.
Also I'll probably decrease patch 5 in size. Stay tuned for v3. :-)
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
` (5 preceding siblings ...)
2022-06-22 6:44 ` Jan Beulich
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
` (7 more replies)
6 siblings, 8 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
These patches add support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
Changes since v2:
- All patches now have the description including links to docs.
- A new operand flag is introduced for ranges 1..n instead of 0..n-1.
- All tests are rewritten for simplicity's sake.
Changes since v1:
- Aliased instruction fields now appear after the original ones.
Dmitry Selyutin (6):
ppc/svp64: support LibreSOC architecture
ppc: introduce non-zero operand
ppc/svp64: support setvl instructions
ppc/svp64: support svstep instructions
ppc/svp64: support svshape instruction
ppc/svp64: support svremap instruction
gas/config/tc-ppc.c | 5 +++
gas/testsuite/gas/ppc/ppc.exp | 5 +++
gas/testsuite/gas/ppc/setvl.d | 15 +++++++
gas/testsuite/gas/ppc/setvl.s | 7 ++++
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++
gas/testsuite/gas/ppc/svshape.d | 13 +++++++
gas/testsuite/gas/ppc/svshape.s | 5 +++
gas/testsuite/gas/ppc/svstep.d | 13 +++++++
gas/testsuite/gas/ppc/svstep.s | 5 +++
include/opcode/ppc.h | 6 +++
opcodes/ppc-dis.c | 5 +++
opcodes/ppc-opc.c | 69 +++++++++++++++++++++++++++++++++
13 files changed, 172 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
` (6 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
---
gas/config/tc-ppc.c | 2 ++
include/opcode/ppc.h | 3 +++
opcodes/ppc-dis.c | 5 +++++
opcodes/ppc-opc.c | 1 +
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4d789fd16a..76bdfb2e35 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e..d5752a42e6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5..f61e6518f1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5bd6dac50..fe2fcaeb1d 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 2/6] ppc: introduce non-zero operand
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:58 ` lkcl
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
` (5 subsequent siblings)
7 siblings, 1 reply; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPCODE_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPCODE_NONZERO, for this
purpose.
---
gas/config/tc-ppc.c | 3 +++
include/opcode/ppc.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 76bdfb2e35..7d27334aa6 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1951,6 +1951,9 @@ ppc_insert_operand (uint64_t insn,
right = max & -max;
min = 0;
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ min = 1;
+
if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0)
{
/* Extend the allowed range for addis to [-32768, 65535].
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index d5752a42e6..215fa8c5e0 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -463,6 +463,9 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_FCR (0x1000000)
#define PPC_OPERAND_UDI (0x2000000)
+/* The operand cannot be zero. */
+#define PPC_OPERAND_NONZERO (0x4000000)
+
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
static inline int64_t
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 3/6] ppc/svp64: support setvl instructions
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
` (4 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/setvl/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 2 ++
gas/testsuite/gas/ppc/setvl.d | 15 +++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 7 +++++++
opcodes/ppc-opc.c | 23 +++++++++++++++++++++++
4 files changed, 47 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6a..cd4dd658ce 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..20af161ae7
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,15 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (37 00 00 58|58 00 00 37) setvl. r0,r0,1,0,0,0
+.*: (36 00 00 58|58 00 00 36) setvl r0,r0,1,0,0,0
+.*: (36 00 e0 5b|5b e0 00 36) setvl r31,r0,1,0,0,0
+.*: (36 00 1f 58|58 1f 00 36) setvl r0,r31,1,0,0,0
+.*: (36 7e 00 58|58 00 7e 36) setvl r0,r0,64,0,0,0
+.*: (76 00 00 58|58 00 00 76) setvl r0,r0,1,1,0,0
+.*: (b6 00 00 58|58 00 00 b6) setvl r0,r0,1,0,1,0
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..b7f1825b54
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,7 @@
+setvl. 0,0,1,0,0,0
+setvl 0,0,1,0,0,0
+setvl 31,0,1,0,0,0
+setvl 0,31,1,0,0,0
+setvl 0,0,64,0,0,0
+setvl 0,0,1,1,0,0
+setvl 0,0,1,0,1,0
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d..2b47fb8781 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,7 @@ extract_thds (uint64_t insn,
return value;
}
+
\f
/* The operands table.
@@ -3825,6 +3826,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, NULL, NULL, (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO) },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4707,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6763,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 4/6] ppc/svp64: support svstep instructions
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
` (2 preceding siblings ...)
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
` (3 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svstep.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svstep.s | 5 +++++
opcodes/ppc-opc.c | 3 +++
4 files changed, 22 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cd4dd658ce..d4d06d587e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -155,3 +155,4 @@ run_dump_test "pr27676"
run_dump_test "raw"
run_dump_test "setvl"
+run_dump_test "svstep"
diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644
index 0000000000..156eb4668a
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (27 00 00 58|58 00 00 27) svstep. r0,1,0
+.*: (26 00 00 58|58 00 00 26) svstep r0,1,0
+.*: (26 00 e0 59|59 e0 00 26) svstep r15,1,0
+.*: (26 7e 00 58|58 00 7e 26) svstep r0,64,0
+.*: (66 00 00 58|58 00 00 66) svstep r0,1,1
diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644
index 0000000000..f238954cf6
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,5 @@
+svstep. 0,1,0
+svstep 0,1,0
+svstep 15,1,0
+svstep 0,64,0
+svstep 0,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 2b47fb8781..c1ad26def9 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6783,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 5/6] ppc/svp64: support svshape instruction
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
` (3 preceding siblings ...)
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
` (2 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svshape.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svshape.s | 5 +++++
opcodes/ppc-opc.c | 22 ++++++++++++++++++++++
4 files changed, 41 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d4d06d587e..04082439bb 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..8244741ed3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (19 00 e0 5b|5b e0 00 19) svshape 32,1,1,0,0
+.*: (19 00 1f 58|58 1f 00 19) svshape 1,32,1,0,0
+.*: (19 f8 00 58|58 00 f8 19) svshape 1,1,32,0,0
+.*: (99 07 00 58|58 00 07 99) svshape 1,1,1,15,0
+.*: (59 00 00 58|58 00 00 59) svshape 1,1,1,0,1
diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..c83373ba37
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,5 @@
+svshape 32,1,1,0,0
+svshape 1,32,1,0,0
+svshape 1,1,32,0,0
+svshape 1,1,1,15,0
+svshape 1,1,1,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index c1ad26def9..33797fcab5 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3838,6 +3838,21 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
{ 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+ { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+ { 0x1f, 21, NULL, NULL, (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO) },
+
+#define SVyd SVxd + 1
+ { 0x1f, 16, NULL, NULL, (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO) },
+
+#define SVzd SVyd + 1
+ { 0x1f, 11, NULL, NULL, (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO) },
+
+#define SVRMf SVzd + 1
+ { 0xf, 7, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4714,6 +4729,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(rc)) & 1))
#define SVL_MASK SVL (0x3f, 0x1f, 1)
+/* An SVM form instruction. */
+#define SVM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK SVM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6785,6 +6806,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVRMf, vf}},
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 6/6] ppc/svp64: support svremap instruction
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
` (4 preceding siblings ...)
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
@ 2022-06-23 19:37 ` Dmitry Selyutin
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:37 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++++++
opcodes/ppc-opc.c | 20 ++++++++++++++++++++
4 files changed, 45 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 04082439bb..a182cc81d7 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -157,3 +157,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
+run_dump_test "svremap"
diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d
new file mode 100644
index 0000000000..18646ec37d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0
+.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0
+.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0
+.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0
+.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0
+.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0
+.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0
+.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s
new file mode 100644
index 0000000000..860040afc5
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.s
@@ -0,0 +1,8 @@
+svremap 0,0,0,0,0,0,0
+svremap 31,0,0,0,0,0,0
+svremap 0,3,0,0,0,0,0
+svremap 0,0,3,0,0,0,0
+svremap 0,0,0,3,0,0,0
+svremap 0,0,0,0,3,0,0
+svremap 0,0,0,0,0,3,0
+svremap 0,3,0,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 33797fcab5..4e98c56f35 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2850,6 +2850,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RM field in an X form instruction. */
#define RM BOP + 1
#define DD RM
+#define mo1 RM
{ 0x3, 11, NULL, NULL, 0 },
#define BH RM + 1
@@ -3508,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define DUI TO
+#define SVme TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -3621,6 +3623,8 @@ const struct powerpc_operand powerpc_operands[] =
#define PSWM WS + 1
/* The BO16 field in a BD8 form instruction. */
#define BO16 PSWM
+ /* The pst field in a SVRM form instruction. */
+#define pst PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@@ -3658,6 +3662,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
#define S SP + 1
@@ -3825,6 +3830,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
#define HH DDD + 1
+#define mo0 HH
{ 0x3, 13, NULL, NULL, 0 },
#define SVi HH + 1
@@ -3853,6 +3859,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SVRMf SVzd + 1
{ 0xf, 7, NULL, NULL, 0 },
+
+#define mi1 SVRMf + 1
+ { 0x3, 17, NULL, NULL, 0 },
+
+#define mi2 mi1 + 1
+ { 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4735,6 +4747,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVM_MASK SVM (0x3f, 0x3f)
+/* An SVRM form instruction. */
+#define SVRM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVRM_MASK SVRM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6811,6 +6829,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
` (5 preceding siblings ...)
2022-06-23 19:37 ` [PATCH v3 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
@ 2022-06-23 19:45 ` Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
7 siblings, 2 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 19:45 UTC (permalink / raw)
To: Binutils
Cc: Alan Modra, Luke Kenneth Casson Leighton, Jan Beulich,
Nick Alcock, Richard Earnshaw, Andreas Schwab
On Thu, Jun 23, 2022 at 10:37 PM Dmitry Selyutin <ghostmansd@gmail.com> wrote:
> Changes since v2:
> - All patches now have the description including links to docs.
> - A new operand flag is introduced for ranges 1..n instead of 0..n-1.
> - All tests are rewritten for simplicity's sake.
Hi folks, many thanks for your tips, suggestions and ideas on
improvements! I've just published version 3, trying to follow the
approach you suggested for tests. Please, let me know if I got the
idea correctly. Also note that there's one more patch which drops a
lot of duplicated code from the original version.
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 2/6] ppc: introduce non-zero operand
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
@ 2022-06-23 19:58 ` lkcl
0 siblings, 0 replies; 62+ messages in thread
From: lkcl @ 2022-06-23 19:58 UTC (permalink / raw)
To: Dmitry Selyutin, binutils
the "normal" way of handling this is e.g. to have a 5-bit field where 0b00000 represents 32 (i.e. 0b100000 rather than 0b00000).
the reasoning behind the decision to go with the -1 offset is that a future version, using v3.1 64-bit prefixing, may end up extending the immediates with a lot more bits, at which point it gets complicated to detect the maximum.
l.
On June 23, 2022 8:37:30 PM GMT+01:00, Dmitry Selyutin <ghostmansd@gmail.com> wrote:
>svstep and svshape instructions subtract 1 before encoding some of the
>operands. Obviously zero is not supported for these operands. Whilst
>PPC_OPCODE_PLUS1 fits perfectly to mark that maximal value should be
>incremented, there is no flag which marks the fact that zero values are
>not allowed. This patch adds a new flag, PPC_OPCODE_NONZERO, for this
>purpose.
>---
> gas/config/tc-ppc.c | 3 +++
> include/opcode/ppc.h | 3 +++
> 2 files changed, 6 insertions(+)
>
>diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
>index 76bdfb2e35..7d27334aa6 100644
>--- a/gas/config/tc-ppc.c
>+++ b/gas/config/tc-ppc.c
>@@ -1951,6 +1951,9 @@ ppc_insert_operand (uint64_t insn,
> right = max & -max;
> min = 0;
>
>+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
>+ min = 1;
>+
> if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0)
> {
> /* Extend the allowed range for addis to [-32768, 65535].
>diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
>index d5752a42e6..215fa8c5e0 100644
>--- a/include/opcode/ppc.h
>+++ b/include/opcode/ppc.h
>@@ -463,6 +463,9 @@ extern const unsigned int num_powerpc_operands;
> #define PPC_OPERAND_FCR (0x1000000)
> #define PPC_OPERAND_UDI (0x2000000)
>
>+/* The operand cannot be zero. */
>+#define PPC_OPERAND_NONZERO (0x4000000)
>+
> extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
>
> static inline int64_t
>--
>2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
` (6 preceding siblings ...)
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
` (6 more replies)
7 siblings, 7 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
These patches add support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
Changes since v3:
- Applied the correct version of patches.
Changes since v2:
- All patches now have the description including links to docs.
- A new operand flag is introduced for ranges 1..n instead of 0..n-1.
- All tests are rewritten for simplicity's sake.
Changes since v1:
- Aliased instruction fields now appear after the original ones.
gas/config/tc-ppc.c | 24 ++++++++++--
gas/testsuite/gas/ppc/ppc.exp | 5 +++
gas/testsuite/gas/ppc/setvl.d | 15 +++++++
gas/testsuite/gas/ppc/setvl.s | 7 ++++
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++
gas/testsuite/gas/ppc/svshape.d | 13 +++++++
gas/testsuite/gas/ppc/svshape.s | 5 +++
gas/testsuite/gas/ppc/svstep.d | 13 +++++++
gas/testsuite/gas/ppc/svstep.s | 5 +++
include/opcode/ppc.h | 10 +++++
opcodes/ppc-dis.c | 8 ++++
opcodes/ppc-opc.c | 69 +++++++++++++++++++++++++++++++++
13 files changed, 195 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 2/6] ppc: introduce non-zero operand flag Dmitry Selyutin
` (5 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
---
gas/config/tc-ppc.c | 2 ++
include/opcode/ppc.h | 3 +++
opcodes/ppc-dis.c | 5 +++++
opcodes/ppc-opc.c | 1 +
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4d789fd16a..76bdfb2e35 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e..d5752a42e6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5..f61e6518f1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5bd6dac50..fe2fcaeb1d 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 2/6] ppc: introduce non-zero operand flag
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
` (4 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
---
gas/config/tc-ppc.c | 22 +++++++++++++++++++---
include/opcode/ppc.h | 7 +++++++
opcodes/ppc-dis.c | 3 +++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 76bdfb2e35..c048721ed0 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1643,10 +1643,16 @@ ppc_setup_opcodes (void)
all the 1's in the mask are contiguous. */
for (i = 0; i < num_powerpc_operands; ++i)
{
+
uint64_t mask = powerpc_operands[i].bitm;
+ unsigned long flags = powerpc_operands[i].flags;
uint64_t right_bit;
unsigned int j;
+ if ((flags & (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO)) ==
+ (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO))
+ as_bad ("mutually exclusive operand flags");
+
right_bit = mask & -mask;
mask += right_bit;
right_bit = mask & -mask;
@@ -1968,6 +1974,11 @@ ppc_insert_operand (uint64_t insn,
max = (max >> 1) & -right;
min = ~max & -right;
}
+ else if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ {
+ ++min;
+ ++max;
+ }
if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
max++;
@@ -2018,10 +2029,15 @@ ppc_insert_operand (uint64_t insn,
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
- else if (operand->shift >= 0)
- insn |= (val & operand->bitm) << operand->shift;
else
- insn |= (val & operand->bitm) >> -operand->shift;
+ {
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ --val;
+ if (operand->shift >= 0)
+ insn |= (val & operand->bitm) << operand->shift;
+ else
+ insn |= (val & operand->bitm) >> -operand->shift;
+ }
return insn;
}
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index d5752a42e6..df06671db4 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -463,6 +463,13 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_FCR (0x1000000)
#define PPC_OPERAND_UDI (0x2000000)
+/*
+ * Valid range of operand is 1..n rather than 0..n-1.
+ * Before encoding, the operand value is decremented.
+ * After decoding. the operand value is incremented.
+ */
+#define PPC_OPERAND_NONZERO 0x4000000
+
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
static inline int64_t
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index f61e6518f1..d5b23c8a75 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -545,6 +545,9 @@ operand_value_powerpc (const struct powerpc_operand *operand,
}
}
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ ++value;
+
return value;
}
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 3/6] ppc/svp64: support setvl instructions
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 2/6] ppc: introduce non-zero operand flag Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
` (3 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/setvl/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 2 ++
gas/testsuite/gas/ppc/setvl.d | 15 +++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 7 +++++++
opcodes/ppc-opc.c | 23 +++++++++++++++++++++++
4 files changed, 47 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6a..cd4dd658ce 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..a241c64fd1
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,15 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (37 00 00 58|58 00 00 37) setvl. r0,r0,1,0,0,0
+.*: (36 00 00 58|58 00 00 36) setvl r0,r0,1,0,0,0
+.*: (36 00 e0 5b|5b e0 00 36) setvl r31,r0,1,0,0,0
+.*: (36 00 1f 58|58 1f 00 36) setvl r0,r31,1,0,0,0
+.*: (36 7e 00 58|58 00 7e 36) setvl r0,r0,64,0,0,0
+.*: (76 00 00 58|58 00 00 76) setvl r0,r0,1,1,0,0
+.*: (b6 00 00 58|58 00 00 b6) setvl r0,r0,1,0,1,0
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..b7f1825b54
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,7 @@
+setvl. 0,0,1,0,0,0
+setvl 0,0,1,0,0,0
+setvl 31,0,1,0,0,0
+setvl 0,31,1,0,0,0
+setvl 0,0,64,0,0,0
+setvl 0,0,1,1,0,0
+setvl 0,0,1,0,1,0
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d..90f813a280 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,7 @@ extract_thds (uint64_t insn,
return value;
}
+
\f
/* The operands table.
@@ -3825,6 +3826,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4707,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6763,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 4/6] ppc/svp64: support svstep instructions
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (2 preceding siblings ...)
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
` (2 subsequent siblings)
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svstep.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svstep.s | 5 +++++
opcodes/ppc-opc.c | 3 +++
4 files changed, 22 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cd4dd658ce..d4d06d587e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -155,3 +155,4 @@ run_dump_test "pr27676"
run_dump_test "raw"
run_dump_test "setvl"
+run_dump_test "svstep"
diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644
index 0000000000..156eb4668a
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (27 00 00 58|58 00 00 27) svstep. r0,1,0
+.*: (26 00 00 58|58 00 00 26) svstep r0,1,0
+.*: (26 00 e0 59|59 e0 00 26) svstep r15,1,0
+.*: (26 7e 00 58|58 00 7e 26) svstep r0,64,0
+.*: (66 00 00 58|58 00 00 66) svstep r0,1,1
diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644
index 0000000000..f238954cf6
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,5 @@
+svstep. 0,1,0
+svstep 0,1,0
+svstep 15,1,0
+svstep 0,64,0
+svstep 0,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 90f813a280..60a038aa40 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6783,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 5/6] ppc/svp64: support svshape instruction
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (3 preceding siblings ...)
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svshape.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svshape.s | 5 +++++
opcodes/ppc-opc.c | 22 ++++++++++++++++++++++
4 files changed, 41 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d4d06d587e..04082439bb 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..8244741ed3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (19 00 e0 5b|5b e0 00 19) svshape 32,1,1,0,0
+.*: (19 00 1f 58|58 1f 00 19) svshape 1,32,1,0,0
+.*: (19 f8 00 58|58 00 f8 19) svshape 1,1,32,0,0
+.*: (99 07 00 58|58 00 07 99) svshape 1,1,1,15,0
+.*: (59 00 00 58|58 00 00 59) svshape 1,1,1,0,1
diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..c83373ba37
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,5 @@
+svshape 32,1,1,0,0
+svshape 1,32,1,0,0
+svshape 1,1,32,0,0
+svshape 1,1,1,15,0
+svshape 1,1,1,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 60a038aa40..fe42c23eab 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3838,6 +3838,21 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
{ 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+ { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+ { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVyd SVxd + 1
+ { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVzd SVyd + 1
+ { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVRMf SVzd + 1
+ { 0xf, 7, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4714,6 +4729,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(rc)) & 1))
#define SVL_MASK SVL (0x3f, 0x1f, 1)
+/* An SVM form instruction. */
+#define SVM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK SVM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6785,6 +6806,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVRMf, vf}},
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v4 6/6] ppc/svp64: support svremap instruction
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (4 preceding siblings ...)
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
@ 2022-06-23 20:08 ` Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
6 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:08 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++++++
opcodes/ppc-opc.c | 20 ++++++++++++++++++++
4 files changed, 45 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 04082439bb..a182cc81d7 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -157,3 +157,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
+run_dump_test "svremap"
diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d
new file mode 100644
index 0000000000..18646ec37d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0
+.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0
+.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0
+.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0
+.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0
+.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0
+.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0
+.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s
new file mode 100644
index 0000000000..860040afc5
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.s
@@ -0,0 +1,8 @@
+svremap 0,0,0,0,0,0,0
+svremap 31,0,0,0,0,0,0
+svremap 0,3,0,0,0,0,0
+svremap 0,0,3,0,0,0,0
+svremap 0,0,0,3,0,0,0
+svremap 0,0,0,0,3,0,0
+svremap 0,0,0,0,0,3,0
+svremap 0,3,0,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe42c23eab..6ece61da09 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2850,6 +2850,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RM field in an X form instruction. */
#define RM BOP + 1
#define DD RM
+#define mo1 RM
{ 0x3, 11, NULL, NULL, 0 },
#define BH RM + 1
@@ -3508,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define DUI TO
+#define SVme TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -3621,6 +3623,8 @@ const struct powerpc_operand powerpc_operands[] =
#define PSWM WS + 1
/* The BO16 field in a BD8 form instruction. */
#define BO16 PSWM
+ /* The pst field in a SVRM form instruction. */
+#define pst PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@@ -3658,6 +3662,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
#define S SP + 1
@@ -3825,6 +3830,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
#define HH DDD + 1
+#define mo0 HH
{ 0x3, 13, NULL, NULL, 0 },
#define SVi HH + 1
@@ -3853,6 +3859,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SVRMf SVzd + 1
{ 0xf, 7, NULL, NULL, 0 },
+
+#define mi1 SVRMf + 1
+ { 0x3, 17, NULL, NULL, 0 },
+
+#define mi2 mi1 + 1
+ { 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4735,6 +4747,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVM_MASK SVM (0x3f, 0x3f)
+/* An SVRM form instruction. */
+#define SVRM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVRM_MASK SVRM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6811,6 +6829,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
1 sibling, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-23 20:10 UTC (permalink / raw)
To: Binutils
Cc: Alan Modra, Luke Kenneth Casson Leighton, Jan Beulich,
Nick Alcock, Richard Earnshaw, Andreas Schwab
Please ignore v3, that revision was incorrect (wrong SHA-1 between
branches) used. Please refer to v4.
--
Best regards,
Dmitry Selyutin
^ permalink raw reply [flat|nested] 62+ messages in thread
* Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns)
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
@ 2022-06-24 11:38 ` lkcl
1 sibling, 0 replies; 62+ messages in thread
From: lkcl @ 2022-06-24 11:38 UTC (permalink / raw)
To: Dmitry Selyutin
Cc: Binutils, Alan Modra, Jan Beulich, Nick Alcock, Richard Earnshaw,
Andreas Schwab, Libre-Soc General Development
On Thu, Jun 23, 2022 at 8:46 PM Dmitry Selyutin <ghostmansd@gmail.com> wrote:
> Hi folks, many thanks for your tips, suggestions and ideas on
> improvements!
it's greatly appreciated, everyone, you as well, Dmitry.
just so everyone knows, the bulk of the work for binutils, adding
Draft Cray-style Scalable Vectors to the Power ISA is, astoundingly,
pretty much done.
there are *NO* actual Vector instructions in SV. we will NOT be
submitting 200-5,000 Vector opcodes as would normally be done
in any other Scalable Vector ISA: ppc64-opc.c contains the
*entirety* of the Vector "contextualisation" of *pre-existing* Scalar
instructions [9]
context and roadmap:
* Simple-V is named "simple" because it adheres to a strict
RISC paradigm [extended into the Scalable Vector space]
* there are only 5 actual "management" instructions:
setvl, svstep, svremap, svshape, svindex (TODO [0])
these last three are for hardware-controlled "Structure Packing"
such as Matrices and other Dimensional shuffling, and
full triple-loop DCT/FFT (normally only found in VLIW DSPs)
* there is "borrowing" of 25% of the EXT001 64-bit prefix
space which gives 24 bits to "categorise" every Scalar
instruction, according to their register profile [1]
as new *Scalar* instructions get added to the Power ISA,
then if it is appropriate to do so [8] they would correspondingly
have to be run through the "register profile analysis" [2] and,
for sanity's sake, the ppc64-opc.[ch] auto-generator re-run [3].
now, we *also* happen to be developing some Scalar instructions.
it's really important to emphasise that these have absolutely nothing
to do with SV, at all.
these Scalar instructions are designed to bring the Scalar Power
ISA up-to-date in many areas outside of its primary focus and perfectly
reasonable and understandable use-case to date [IBM's high-end
customers]. example: i'm currently designing a bitmanip-mask instruction
which covers the entirety of BMI and TBM [4] *and* RVV's vsbfm suite.
none of these were needed for any IBM workloads / customers so
it is perfectly reasonable that they were never considered.
there's also a pair of biginteger math operations, a variant of
the intel "mulx" instruction is one of them [5]. the majority
of the list is on the bitmanip page [6], these will take some
time simply because there's a lot of them (appx... 80-100)
still on the TODO list:
* macro support (including the "8" of element-width=8, sorry Dmitry!) [7]
* svindex for doing vector-looped GPR[RT] = GPR(GPR(RA)) [0]
* submit scalar instructions [6] and corresponding ppc64-opc.[ch] [2][3]
that's basically it. there's no binutils-level subsetting of SVP64 because
the lower SV Compliancy Levels require soft-emulation through illegal
instruction traps. there's no Vector instructions to add: everything
Scalable-Vectorised is in the 24-bit Prefix.
overall, then, the strict RISC paradigm creates one hell of a lot less
work for everyone, yet brings something mind-melting like 2 million
intrinsics to the Power ISA. which is only manageable by sticking
strictly to RISC principles.
l.
[0] https://bugs.libre-soc.org/show_bug.cgi?id=867
[1] fascinatingly this approach was exactly the one that Peter Hsu
and his team at MIPS, when they were developing the R8000,
came up with around 1995.
[2] https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD
[3] https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_binutils.py;hb=HEAD
[4] https://bugs.libre-soc.org/show_bug.cgi?id=865#c1
[5] https://libre-soc.org/openpower/sv/biginteger/
[6] https://libre-soc.org/openpower/sv/bitmanip/
[7] https://bugs.libre-soc.org/show_bug.cgi?id=849
[8] new Scalar instructions have to make sense in a Vector context
"scalar===element" before they can be Prefixed to extend to multiple
elements. mtmsr doesn't qualify for example because there's only
ever going to be one MSR. sc makes no sense, but weirdly td/tw
tdi/twi do.
[9] we tried breaking the rule of adding Vector opcodes without having
the corresponding identical Scalar instruction: it went very badly.
lesson learned.
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (5 preceding siblings ...)
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
@ 2022-06-26 18:59 ` Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
` (7 more replies)
6 siblings, 8 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 18:59 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
These patches add support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
Changes since v4:
- Introduced svindex instruction along with SVI form.
- Fixed svstep test so that ranges for operand 0 are correct.
- Updated commit messages with the links to instructions.
- Renamed SVRMf field to SVrm.
Changes since v3:
- Applied the correct version of patches.
Changes since v2:
- All patches now have the description including links to docs.
- A new operand flag is introduced for ranges 1..n instead of 0..n-1.
- All tests are rewritten for simplicity's sake.
Changes since v1:
- Aliased instruction fields now appear after the original ones.
Dmitry Selyutin (7):
ppc/svp64: support LibreSOC architecture
ppc: introduce non-zero operand flag
ppc/svp64: support setvl instructions
ppc/svp64: support svstep instructions
ppc/svp64: support svshape instruction
ppc/svp64: support svremap instruction
ppc/svp64: support svindex instruction
gas/config/tc-ppc.c | 24 ++++++++--
gas/testsuite/gas/ppc/ppc.exp | 6 +++
gas/testsuite/gas/ppc/setvl.d | 15 ++++++
gas/testsuite/gas/ppc/setvl.s | 7 +++
gas/testsuite/gas/ppc/svindex.d | 16 +++++++
gas/testsuite/gas/ppc/svindex.s | 8 ++++
gas/testsuite/gas/ppc/svremap.d | 16 +++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++
gas/testsuite/gas/ppc/svshape.d | 13 +++++
gas/testsuite/gas/ppc/svshape.s | 5 ++
gas/testsuite/gas/ppc/svstep.d | 13 +++++
gas/testsuite/gas/ppc/svstep.s | 5 ++
include/opcode/ppc.h | 10 ++++
opcodes/ppc-dis.c | 8 ++++
opcodes/ppc-opc.c | 84 +++++++++++++++++++++++++++++++++
15 files changed, 235 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
create mode 100644 gas/testsuite/gas/ppc/svindex.d
create mode 100644 gas/testsuite/gas/ppc/svindex.s
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-06-26 18:59 ` Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
` (6 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 18:59 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
---
gas/config/tc-ppc.c | 2 ++
include/opcode/ppc.h | 3 +++
opcodes/ppc-dis.c | 5 +++++
opcodes/ppc-opc.c | 1 +
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4d789fd16a..76bdfb2e35 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e..d5752a42e6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5..f61e6518f1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5bd6dac50..fe2fcaeb1d 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 2/7] ppc: introduce non-zero operand flag
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
@ 2022-06-26 19:00 ` Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
` (5 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 19:00 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
---
gas/config/tc-ppc.c | 22 +++++++++++++++++++---
include/opcode/ppc.h | 7 +++++++
opcodes/ppc-dis.c | 3 +++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 76bdfb2e35..c048721ed0 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1643,10 +1643,16 @@ ppc_setup_opcodes (void)
all the 1's in the mask are contiguous. */
for (i = 0; i < num_powerpc_operands; ++i)
{
+
uint64_t mask = powerpc_operands[i].bitm;
+ unsigned long flags = powerpc_operands[i].flags;
uint64_t right_bit;
unsigned int j;
+ if ((flags & (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO)) ==
+ (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO))
+ as_bad ("mutually exclusive operand flags");
+
right_bit = mask & -mask;
mask += right_bit;
right_bit = mask & -mask;
@@ -1968,6 +1974,11 @@ ppc_insert_operand (uint64_t insn,
max = (max >> 1) & -right;
min = ~max & -right;
}
+ else if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ {
+ ++min;
+ ++max;
+ }
if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
max++;
@@ -2018,10 +2029,15 @@ ppc_insert_operand (uint64_t insn,
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
- else if (operand->shift >= 0)
- insn |= (val & operand->bitm) << operand->shift;
else
- insn |= (val & operand->bitm) >> -operand->shift;
+ {
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ --val;
+ if (operand->shift >= 0)
+ insn |= (val & operand->bitm) << operand->shift;
+ else
+ insn |= (val & operand->bitm) >> -operand->shift;
+ }
return insn;
}
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index d5752a42e6..df06671db4 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -463,6 +463,13 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_FCR (0x1000000)
#define PPC_OPERAND_UDI (0x2000000)
+/*
+ * Valid range of operand is 1..n rather than 0..n-1.
+ * Before encoding, the operand value is decremented.
+ * After decoding. the operand value is incremented.
+ */
+#define PPC_OPERAND_NONZERO 0x4000000
+
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
static inline int64_t
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index f61e6518f1..d5b23c8a75 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -545,6 +545,9 @@ operand_value_powerpc (const struct powerpc_operand *operand,
}
}
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ ++value;
+
return value;
}
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 3/7] ppc/svp64: support setvl instructions
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
@ 2022-06-26 19:00 ` Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
` (4 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 19:00 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/setvl/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 2 ++
gas/testsuite/gas/ppc/setvl.d | 15 +++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 7 +++++++
opcodes/ppc-opc.c | 23 +++++++++++++++++++++++
4 files changed, 47 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6a..cd4dd658ce 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..a241c64fd1
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,15 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (37 00 00 58|58 00 00 37) setvl. r0,r0,1,0,0,0
+.*: (36 00 00 58|58 00 00 36) setvl r0,r0,1,0,0,0
+.*: (36 00 e0 5b|5b e0 00 36) setvl r31,r0,1,0,0,0
+.*: (36 00 1f 58|58 1f 00 36) setvl r0,r31,1,0,0,0
+.*: (36 7e 00 58|58 00 7e 36) setvl r0,r0,64,0,0,0
+.*: (76 00 00 58|58 00 00 76) setvl r0,r0,1,1,0,0
+.*: (b6 00 00 58|58 00 00 b6) setvl r0,r0,1,0,1,0
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..b7f1825b54
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,7 @@
+setvl. 0,0,1,0,0,0
+setvl 0,0,1,0,0,0
+setvl 31,0,1,0,0,0
+setvl 0,31,1,0,0,0
+setvl 0,0,64,0,0,0
+setvl 0,0,1,1,0,0
+setvl 0,0,1,0,1,0
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d..90f813a280 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,7 @@ extract_thds (uint64_t insn,
return value;
}
+
\f
/* The operands table.
@@ -3825,6 +3826,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4707,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6763,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 4/7] ppc/svp64: support svstep instructions
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (2 preceding siblings ...)
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-06-26 19:00 ` Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
` (3 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 19:00 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/svstep/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svstep.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svstep.s | 5 +++++
opcodes/ppc-opc.c | 3 +++
4 files changed, 22 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cd4dd658ce..d4d06d587e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -155,3 +155,4 @@ run_dump_test "pr27676"
run_dump_test "raw"
run_dump_test "setvl"
+run_dump_test "svstep"
diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644
index 0000000000..5ce2c2570c
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (27 00 00 58|58 00 00 27) svstep. r0,1,0
+.*: (26 00 00 58|58 00 00 26) svstep r0,1,0
+.*: (26 00 e0 5b|5b e0 00 26) svstep r31,1,0
+.*: (26 7e 00 58|58 00 7e 26) svstep r0,64,0
+.*: (66 00 00 58|58 00 00 66) svstep r0,1,1
diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644
index 0000000000..b073b2e467
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,5 @@
+svstep. 0,1,0
+svstep 0,1,0
+svstep 31,1,0
+svstep 0,64,0
+svstep 0,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 90f813a280..60a038aa40 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6783,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 5/7] ppc/svp64: support svshape instruction
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (3 preceding siblings ...)
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
@ 2022-06-26 19:00 ` Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
` (2 subsequent siblings)
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 19:00 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svshape
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svshape.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svshape.s | 5 +++++
opcodes/ppc-opc.c | 23 +++++++++++++++++++++++
4 files changed, 42 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d4d06d587e..04082439bb 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..8244741ed3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (19 00 e0 5b|5b e0 00 19) svshape 32,1,1,0,0
+.*: (19 00 1f 58|58 1f 00 19) svshape 1,32,1,0,0
+.*: (19 f8 00 58|58 00 f8 19) svshape 1,1,32,0,0
+.*: (99 07 00 58|58 00 07 99) svshape 1,1,1,15,0
+.*: (59 00 00 58|58 00 00 59) svshape 1,1,1,0,1
diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..c83373ba37
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,5 @@
+svshape 32,1,1,0,0
+svshape 1,32,1,0,0
+svshape 1,1,32,0,0
+svshape 1,1,1,15,0
+svshape 1,1,1,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 60a038aa40..f95bbf9402 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3838,6 +3838,21 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
{ 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+ { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+ { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVyd SVxd + 1
+ { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVzd SVyd + 1
+ { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVrm SVzd + 1
+ { 0xf, 7, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4714,6 +4729,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(rc)) & 1))
#define SVL_MASK SVL (0x3f, 0x1f, 1)
+/* An SVM form instruction. */
+#define SVM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK SVM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6786,6 +6807,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVrm, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 6/7] ppc/svp64: support svremap instruction
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (4 preceding siblings ...)
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
@ 2022-06-26 19:00 ` Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 19:00 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svremap
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++++++
opcodes/ppc-opc.c | 20 ++++++++++++++++++++
4 files changed, 45 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 04082439bb..a182cc81d7 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -157,3 +157,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
+run_dump_test "svremap"
diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d
new file mode 100644
index 0000000000..18646ec37d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0
+.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0
+.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0
+.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0
+.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0
+.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0
+.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0
+.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s
new file mode 100644
index 0000000000..860040afc5
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.s
@@ -0,0 +1,8 @@
+svremap 0,0,0,0,0,0,0
+svremap 31,0,0,0,0,0,0
+svremap 0,3,0,0,0,0,0
+svremap 0,0,3,0,0,0,0
+svremap 0,0,0,3,0,0,0
+svremap 0,0,0,0,3,0,0
+svremap 0,0,0,0,0,3,0
+svremap 0,3,0,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f95bbf9402..8e56f88a6c 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2850,6 +2850,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RM field in an X form instruction. */
#define RM BOP + 1
#define DD RM
+#define mo1 RM
{ 0x3, 11, NULL, NULL, 0 },
#define BH RM + 1
@@ -3508,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define DUI TO
+#define SVme TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -3621,6 +3623,8 @@ const struct powerpc_operand powerpc_operands[] =
#define PSWM WS + 1
/* The BO16 field in a BD8 form instruction. */
#define BO16 PSWM
+ /* The pst field in a SVRM form instruction. */
+#define pst PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@@ -3658,6 +3662,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
#define S SP + 1
@@ -3825,6 +3830,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
#define HH DDD + 1
+#define mo0 HH
{ 0x3, 13, NULL, NULL, 0 },
#define SVi HH + 1
@@ -3853,6 +3859,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SVrm SVzd + 1
{ 0xf, 7, NULL, NULL, 0 },
+
+#define mi1 SVrm + 1
+ { 0x3, 17, NULL, NULL, 0 },
+
+#define mi2 mi1 + 1
+ { 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4735,6 +4747,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVM_MASK SVM (0x3f, 0x3f)
+/* An SVRM form instruction. */
+#define SVRM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVRM_MASK SVRM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6812,6 +6830,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v5 7/7] ppc/svp64: support svindex instruction
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (5 preceding siblings ...)
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
@ 2022-06-26 19:00 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
7 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-06-26 19:00 UTC (permalink / raw)
To: binutils
Cc: Alan Modra, Luke Leighton, Jan Beulich, Nick Alcock,
Richard Earnshaw, Andreas Schwab, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svindex
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svindex.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svindex.s | 8 ++++++++
opcodes/ppc-opc.c | 14 ++++++++++++++
4 files changed, 39 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svindex.d
create mode 100644 gas/testsuite/gas/ppc/svindex.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a182cc81d7..12b4c9dac0 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -158,3 +158,4 @@ run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
run_dump_test "svremap"
+run_dump_test "svindex"
diff --git a/gas/testsuite/gas/ppc/svindex.d b/gas/testsuite/gas/ppc/svindex.d
new file mode 100644
index 0000000000..73bda73287
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (29 00 00 58|58 00 00 29) svindex r0,0,1,0,0,0,0
+.*: (29 00 e0 5b|5b e0 00 29) svindex r31,0,1,0,0,0,0
+.*: (29 00 1f 58|58 1f 00 29) svindex r0,31,1,0,0,0,0
+.*: (29 f8 00 58|58 00 f8 29) svindex r0,0,32,0,0,0,0
+.*: (29 06 00 58|58 00 06 29) svindex r0,0,1,3,0,0,0
+.*: (29 01 00 58|58 00 01 29) svindex r0,0,1,0,1,0,0
+.*: (a9 00 00 58|58 00 00 a9) svindex r0,0,1,0,0,1,0
+.*: (69 00 00 58|58 00 00 69) svindex r0,0,1,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svindex.s b/gas/testsuite/gas/ppc/svindex.s
new file mode 100644
index 0000000000..ab256c433b
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.s
@@ -0,0 +1,8 @@
+svindex 0,0,1,0,0,0,0
+svindex 31,0,1,0,0,0,0
+svindex 0,31,1,0,0,0,0
+svindex 0,0,32,0,0,0,0
+svindex 0,0,1,3,0,0,0
+svindex 0,0,1,0,1,0,0
+svindex 0,0,1,0,0,1,0
+svindex 0,0,1,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 8e56f88a6c..84b7d90c22 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3557,6 +3557,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
#define DCTL UIMM
+#define rmm UIMM
{ 0x1f, 16, NULL, NULL, 0 },
/* The 3-bit UIMM field in a VX form instruction. */
@@ -3649,6 +3650,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RMC or CY field in a Z23 form instruction. */
#define RMC A_L + 1
#define CY RMC
+#define ew RMC
{ 0x3, 9, NULL, NULL, 0 },
#define R RMC + 1
@@ -3837,12 +3839,15 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
#define vf SVi + 1
+#define sk vf
{ 0x1, 6, NULL, NULL, 0 },
#define vs vf + 1
+#define mm vs
{ 0x1, 7, NULL, NULL, 0 },
#define ms vs + 1
+#define yx ms
{ 0x1, 8, NULL, NULL, 0 },
#define SVLcr ms + 1
@@ -3855,6 +3860,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
#define SVzd SVyd + 1
+#define SVd SVzd
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
#define SVrm SVzd + 1
@@ -4753,6 +4759,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVRM_MASK SVRM (0x3f, 0x3f)
+/* An SVI form instruction. */
+#define SVI(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVI_MASK SVI (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6830,6 +6842,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svindex", SVI(22,41), SVI_MASK, SVP64, PPCVLE, {RS, rmm, SVd, ew, yx, mm, sk}},
+
{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
--
2.36.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (6 preceding siblings ...)
2022-06-26 19:00 ` [PATCH v5 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
` (8 more replies)
7 siblings, 9 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
These patches add support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
Changes since v5:
- Introduced an SVG field, acting as TO field alias (SVI-FORM).
Changes since v4:
- Introduced svindex instruction along with SVI form.
- Fixed svstep test so that ranges for operand 0 are correct.
- Updated commit messages with the links to instructions.
- Renamed SVRMf field to SVrm.
Changes since v3:
- Applied the correct version of patches.
Changes since v2:
- All patches now have the description including links to docs.
- A new operand flag is introduced for ranges 1..n instead of 0..n-1.
- All tests are rewritten for simplicity's sake.
Changes since v1:
- Aliased instruction fields now appear after the original ones.
Dmitry Selyutin (7):
ppc/svp64: support LibreSOC architecture
ppc: introduce non-zero operand flag
ppc/svp64: support setvl instructions
ppc/svp64: support svstep instructions
ppc/svp64: support svshape instruction
ppc/svp64: support svremap instruction
ppc/svp64: support svindex instruction
gas/config/tc-ppc.c | 24 ++++++++--
gas/testsuite/gas/ppc/ppc.exp | 6 +++
gas/testsuite/gas/ppc/setvl.d | 15 ++++++
gas/testsuite/gas/ppc/setvl.s | 7 +++
gas/testsuite/gas/ppc/svindex.d | 16 +++++++
gas/testsuite/gas/ppc/svindex.s | 8 ++++
gas/testsuite/gas/ppc/svremap.d | 16 +++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++
gas/testsuite/gas/ppc/svshape.d | 13 +++++
gas/testsuite/gas/ppc/svshape.s | 5 ++
gas/testsuite/gas/ppc/svstep.d | 13 +++++
gas/testsuite/gas/ppc/svstep.s | 5 ++
include/opcode/ppc.h | 10 ++++
opcodes/ppc-dis.c | 8 ++++
opcodes/ppc-opc.c | 85 +++++++++++++++++++++++++++++++++
15 files changed, 236 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
create mode 100644 gas/testsuite/gas/ppc/svindex.d
create mode 100644 gas/testsuite/gas/ppc/svindex.s
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
` (7 subsequent siblings)
8 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
---
gas/config/tc-ppc.c | 2 ++
include/opcode/ppc.h | 3 +++
opcodes/ppc-dis.c | 5 +++++
opcodes/ppc-opc.c | 1 +
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 452fab1cbf..ffc99857e3 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1382,6 +1382,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e..d5752a42e6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5..f61e6518f1 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 7637d3e349..51da625e04 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4832,6 +4832,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 2/7] ppc: introduce non-zero operand flag
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
` (6 subsequent siblings)
8 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
---
gas/config/tc-ppc.c | 22 +++++++++++++++++++---
include/opcode/ppc.h | 7 +++++++
opcodes/ppc-dis.c | 3 +++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index ffc99857e3..7bd2fe785d 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1656,10 +1656,16 @@ ppc_setup_opcodes (void)
all the 1's in the mask are contiguous. */
for (i = 0; i < num_powerpc_operands; ++i)
{
+
uint64_t mask = powerpc_operands[i].bitm;
+ unsigned long flags = powerpc_operands[i].flags;
uint64_t right_bit;
unsigned int j;
+ if ((flags & (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO)) ==
+ (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO))
+ as_bad ("mutually exclusive operand flags");
+
right_bit = mask & -mask;
mask += right_bit;
right_bit = mask & -mask;
@@ -1992,6 +1998,11 @@ ppc_insert_operand (uint64_t insn,
max = (max >> 1) & -right;
min = ~max & -right;
}
+ else if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ {
+ ++min;
+ ++max;
+ }
if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
max++;
@@ -2042,10 +2053,15 @@ ppc_insert_operand (uint64_t insn,
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
- else if (operand->shift >= 0)
- insn |= (val & operand->bitm) << operand->shift;
else
- insn |= (val & operand->bitm) >> -operand->shift;
+ {
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ --val;
+ if (operand->shift >= 0)
+ insn |= (val & operand->bitm) << operand->shift;
+ else
+ insn |= (val & operand->bitm) >> -operand->shift;
+ }
return insn;
}
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index d5752a42e6..df06671db4 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -463,6 +463,13 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_FCR (0x1000000)
#define PPC_OPERAND_UDI (0x2000000)
+/*
+ * Valid range of operand is 1..n rather than 0..n-1.
+ * Before encoding, the operand value is decremented.
+ * After decoding. the operand value is incremented.
+ */
+#define PPC_OPERAND_NONZERO 0x4000000
+
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
static inline int64_t
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index f61e6518f1..d5b23c8a75 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -545,6 +545,9 @@ operand_value_powerpc (const struct powerpc_operand *operand,
}
}
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ ++value;
+
return value;
}
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 3/7] ppc/svp64: support setvl instructions
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-08-15 6:18 ` Jan Beulich
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
` (5 subsequent siblings)
8 siblings, 1 reply; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/setvl/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 2 ++
gas/testsuite/gas/ppc/setvl.d | 15 +++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 7 +++++++
opcodes/ppc-opc.c | 23 +++++++++++++++++++++++
4 files changed, 47 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 9844ce7e4a..70d6960d42 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -154,3 +154,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..a241c64fd1
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,15 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (37 00 00 58|58 00 00 37) setvl. r0,r0,1,0,0,0
+.*: (36 00 00 58|58 00 00 36) setvl r0,r0,1,0,0,0
+.*: (36 00 e0 5b|5b e0 00 36) setvl r31,r0,1,0,0,0
+.*: (36 00 1f 58|58 1f 00 36) setvl r0,r31,1,0,0,0
+.*: (36 7e 00 58|58 00 7e 36) setvl r0,r0,64,0,0,0
+.*: (76 00 00 58|58 00 00 76) setvl r0,r0,1,1,0,0
+.*: (b6 00 00 58|58 00 00 b6) setvl r0,r0,1,0,1,0
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..b7f1825b54
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,7 @@
+setvl. 0,0,1,0,0,0
+setvl 0,0,1,0,0,0
+setvl 31,0,1,0,0,0
+setvl 0,31,1,0,0,0
+setvl 0,0,64,0,0,0
+setvl 0,0,1,1,0,0
+setvl 0,0,1,0,1,0
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 51da625e04..1c9dd5bd7b 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,7 @@ extract_thds (uint64_t insn,
return value;
}
+
\f
/* The operands table.
@@ -3825,6 +3826,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4700,6 +4713,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6769,6 +6789,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 4/7] ppc/svp64: support svstep instructions
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (2 preceding siblings ...)
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
` (4 subsequent siblings)
8 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/svstep/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svstep.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svstep.s | 5 +++++
opcodes/ppc-opc.c | 3 +++
4 files changed, 22 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svstep.d
create mode 100644 gas/testsuite/gas/ppc/svstep.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 70d6960d42..d126d03109 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -156,3 +156,4 @@ run_dump_test "pr27676"
run_dump_test "raw"
run_dump_test "setvl"
+run_dump_test "svstep"
diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644
index 0000000000..5ce2c2570c
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (27 00 00 58|58 00 00 27) svstep. r0,1,0
+.*: (26 00 00 58|58 00 00 26) svstep r0,1,0
+.*: (26 00 e0 5b|5b e0 00 26) svstep r31,1,0
+.*: (26 7e 00 58|58 00 7e 26) svstep r0,64,0
+.*: (66 00 00 58|58 00 00 66) svstep r0,1,1
diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644
index 0000000000..b073b2e467
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,5 @@
+svstep. 0,1,0
+svstep 0,1,0
+svstep 31,1,0
+svstep 0,64,0
+svstep 0,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 1c9dd5bd7b..99f4c147cf 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6789,6 +6789,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 5/7] ppc/svp64: support svshape instruction
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (3 preceding siblings ...)
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
` (3 subsequent siblings)
8 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svshape
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svshape.d | 13 +++++++++++++
gas/testsuite/gas/ppc/svshape.s | 5 +++++
opcodes/ppc-opc.c | 23 +++++++++++++++++++++++
4 files changed, 42 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svshape.d
create mode 100644 gas/testsuite/gas/ppc/svshape.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index d126d03109..ea1c591a1e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -157,3 +157,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
+run_dump_test "svshape"
diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d
new file mode 100644
index 0000000000..8244741ed3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (19 00 e0 5b|5b e0 00 19) svshape 32,1,1,0,0
+.*: (19 00 1f 58|58 1f 00 19) svshape 1,32,1,0,0
+.*: (19 f8 00 58|58 00 f8 19) svshape 1,1,32,0,0
+.*: (99 07 00 58|58 00 07 99) svshape 1,1,1,15,0
+.*: (59 00 00 58|58 00 00 59) svshape 1,1,1,0,1
diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s
new file mode 100644
index 0000000000..c83373ba37
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svshape.s
@@ -0,0 +1,5 @@
+svshape 32,1,1,0,0
+svshape 1,32,1,0,0
+svshape 1,1,32,0,0
+svshape 1,1,1,15,0
+svshape 1,1,1,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 99f4c147cf..bf77083037 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3838,6 +3838,21 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
{ 0x1, 8, NULL, NULL, 0 },
+
+#define SVLcr ms + 1
+ { 0x1, 5, NULL, NULL, 0 },
+
+#define SVxd SVLcr + 1
+ { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVyd SVxd + 1
+ { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVzd SVyd + 1
+ { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define SVrm SVzd + 1
+ { 0xf, 7, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4720,6 +4735,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(rc)) & 1))
#define SVL_MASK SVL (0x3f, 0x1f, 1)
+/* An SVM form instruction. */
+#define SVM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVM_MASK SVM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6792,6 +6813,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
{"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
+{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVrm, vf}},
+
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 6/7] ppc/svp64: support svremap instruction
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (4 preceding siblings ...)
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
` (2 subsequent siblings)
8 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svremap
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++++++
opcodes/ppc-opc.c | 20 ++++++++++++++++++++
4 files changed, 45 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index ea1c591a1e..9f02fa75c2 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -158,3 +158,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
+run_dump_test "svremap"
diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d
new file mode 100644
index 0000000000..18646ec37d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0
+.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0
+.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0
+.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0
+.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0
+.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0
+.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0
+.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s
new file mode 100644
index 0000000000..860040afc5
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.s
@@ -0,0 +1,8 @@
+svremap 0,0,0,0,0,0,0
+svremap 31,0,0,0,0,0,0
+svremap 0,3,0,0,0,0,0
+svremap 0,0,3,0,0,0,0
+svremap 0,0,0,3,0,0,0
+svremap 0,0,0,0,3,0,0
+svremap 0,0,0,0,0,3,0
+svremap 0,3,0,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index bf77083037..fa1ffa5698 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2850,6 +2850,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RM field in an X form instruction. */
#define RM BOP + 1
#define DD RM
+#define mo1 RM
{ 0x3, 11, NULL, NULL, 0 },
#define BH RM + 1
@@ -3508,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define DUI TO
+#define SVme TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -3621,6 +3623,8 @@ const struct powerpc_operand powerpc_operands[] =
#define PSWM WS + 1
/* The BO16 field in a BD8 form instruction. */
#define BO16 PSWM
+ /* The pst field in a SVRM form instruction. */
+#define pst PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@@ -3658,6 +3662,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
#define S SP + 1
@@ -3825,6 +3830,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
#define HH DDD + 1
+#define mo0 HH
{ 0x3, 13, NULL, NULL, 0 },
#define SVi HH + 1
@@ -3853,6 +3859,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SVrm SVzd + 1
{ 0xf, 7, NULL, NULL, 0 },
+
+#define mi1 SVrm + 1
+ { 0x3, 17, NULL, NULL, 0 },
+
+#define mi2 mi1 + 1
+ { 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4741,6 +4753,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVM_MASK SVM (0x3f, 0x3f)
+/* An SVRM form instruction. */
+#define SVRM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVRM_MASK SVRM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6818,6 +6836,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 7/7] ppc/svp64: support svindex instruction
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (5 preceding siblings ...)
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
@ 2022-07-25 13:10 ` Dmitry Selyutin
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-08-11 9:14 ` Alan Modra
8 siblings, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-25 13:10 UTC (permalink / raw)
To: binutils; +Cc: Alan Modra, Luke Kenneth Casson Leighton, Dmitry Selyutin
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svindex
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svindex.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svindex.s | 8 ++++++++
opcodes/ppc-opc.c | 15 +++++++++++++++
4 files changed, 40 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svindex.d
create mode 100644 gas/testsuite/gas/ppc/svindex.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 9f02fa75c2..53c2d0dc32 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -159,3 +159,4 @@ run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
run_dump_test "svremap"
+run_dump_test "svindex"
diff --git a/gas/testsuite/gas/ppc/svindex.d b/gas/testsuite/gas/ppc/svindex.d
new file mode 100644
index 0000000000..73bda73287
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (29 00 00 58|58 00 00 29) svindex r0,0,1,0,0,0,0
+.*: (29 00 e0 5b|5b e0 00 29) svindex r31,0,1,0,0,0,0
+.*: (29 00 1f 58|58 1f 00 29) svindex r0,31,1,0,0,0,0
+.*: (29 f8 00 58|58 00 f8 29) svindex r0,0,32,0,0,0,0
+.*: (29 06 00 58|58 00 06 29) svindex r0,0,1,3,0,0,0
+.*: (29 01 00 58|58 00 01 29) svindex r0,0,1,0,1,0,0
+.*: (a9 00 00 58|58 00 00 a9) svindex r0,0,1,0,0,1,0
+.*: (69 00 00 58|58 00 00 69) svindex r0,0,1,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svindex.s b/gas/testsuite/gas/ppc/svindex.s
new file mode 100644
index 0000000000..ab256c433b
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.s
@@ -0,0 +1,8 @@
+svindex 0,0,1,0,0,0,0
+svindex 31,0,1,0,0,0,0
+svindex 0,31,1,0,0,0,0
+svindex 0,0,32,0,0,0,0
+svindex 0,0,1,3,0,0,0
+svindex 0,0,1,0,1,0,0
+svindex 0,0,1,0,0,1,0
+svindex 0,0,1,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fa1ffa5698..1e791e57c3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3510,6 +3510,7 @@ const struct powerpc_operand powerpc_operands[] =
#define TO TBR + 1
#define DUI TO
#define SVme TO
+#define SVG TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -3557,6 +3558,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
#define DCTL UIMM
+#define rmm UIMM
{ 0x1f, 16, NULL, NULL, 0 },
/* The 3-bit UIMM field in a VX form instruction. */
@@ -3649,6 +3651,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RMC or CY field in a Z23 form instruction. */
#define RMC A_L + 1
#define CY RMC
+#define ew RMC
{ 0x3, 9, NULL, NULL, 0 },
#define R RMC + 1
@@ -3837,12 +3840,15 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
#define vf SVi + 1
+#define sk vf
{ 0x1, 6, NULL, NULL, 0 },
#define vs vf + 1
+#define mm vs
{ 0x1, 7, NULL, NULL, 0 },
#define ms vs + 1
+#define yx ms
{ 0x1, 8, NULL, NULL, 0 },
#define SVLcr ms + 1
@@ -3855,6 +3861,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
#define SVzd SVyd + 1
+#define SVd SVzd
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
#define SVrm SVzd + 1
@@ -4759,6 +4766,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVRM_MASK SVRM (0x3f, 0x3f)
+/* An SVI form instruction. */
+#define SVI(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVI_MASK SVI (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6836,6 +6849,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svindex", SVI(22,41), SVI_MASK, SVP64, PPCVLE, {SVG, rmm, SVd, ew, yx, mm, sk}},
+
{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
--
2.37.0
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (6 preceding siblings ...)
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
@ 2022-07-26 13:14 ` Dmitry Selyutin
2022-07-27 4:53 ` Alan Modra
2022-08-11 9:14 ` Alan Modra
8 siblings, 1 reply; 62+ messages in thread
From: Dmitry Selyutin @ 2022-07-26 13:14 UTC (permalink / raw)
To: Binutils, Alan Modra; +Cc: Luke Kenneth Casson Leighton
On Mon, Jul 25, 2022, 16:10 Dmitry Selyutin <ghostmansd@gmail.com> wrote:
> These patches add support for LibreSOC machine and SVP64 extension flag
> for PowerPC architecture.
Hi Alan, can we submit this? I got a confirmation that copyrights
assignment is done, so hopefully we can start submitting patches.
The original thread became way too large, perhaps I should send all these
patches as part of the new thread. What do you think?
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-07-27 4:53 ` Alan Modra
2022-07-27 6:38 ` lkcl
0 siblings, 1 reply; 62+ messages in thread
From: Alan Modra @ 2022-07-27 4:53 UTC (permalink / raw)
To: Dmitry Selyutin; +Cc: Binutils, Luke Kenneth Casson Leighton
On Tue, Jul 26, 2022 at 04:14:28PM +0300, Dmitry Selyutin wrote:
> On Mon, Jul 25, 2022, 16:10 Dmitry Selyutin <ghostmansd@gmail.com> wrote:
>
> > These patches add support for LibreSOC machine and SVP64 extension flag
> > for PowerPC architecture.
>
>
> Hi Alan, can we submit this? I got a confirmation that copyrights
> assignment is done, so hopefully we can start submitting patches.
Sorry, no. I have yet to see your assignment in the GNU
copyright.list file, and until that happens it is not done. That's
the file that I am required to check as a GNU project maintainer, and
unlike some I don't see much sense in tearing down FSF procedures or
governance. Last entry in the file on fencepost.gnu.org is 2022-07-20
so I guess your assignment might take a few days more.
> The original thread became way too large, perhaps I should send all these
> patches as part of the new thread. What do you think?
No, please don't repost unless you find a major reason that an older
patch needs revision.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns
2022-07-27 4:53 ` Alan Modra
@ 2022-07-27 6:38 ` lkcl
0 siblings, 0 replies; 62+ messages in thread
From: lkcl @ 2022-07-27 6:38 UTC (permalink / raw)
To: Alan Modra, Dmitry Selyutin; +Cc: Binutils
On July 27, 2022 5:53:48 AM GMT+01:00, Alan Modra <amodra@gmail.com> wrote:
> No, please don't repost unless you find a major reason that an older
> patch needs revision.
thank you for patiently informing us of contributor procedures alan.
appreciate there are lots of hoops and a lot you have to coordinate.
l.
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
` (7 preceding siblings ...)
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
@ 2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
8 siblings, 2 replies; 62+ messages in thread
From: Alan Modra @ 2022-08-11 9:14 UTC (permalink / raw)
To: Dmitry Selyutin; +Cc: binutils, Luke Kenneth Casson Leighton
On Mon, Jul 25, 2022 at 04:10:13PM +0300, Dmitry Selyutin wrote:
> These patches add support for LibreSOC machine and SVP64 extension flag
> for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
> Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
> Prefixed instruction format implementing SV. Funded by NLnet through EU
> Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
> submitted via the OpenPOWER Foundation ISA Working Group via the
> newly-created External RFC Process.
Hi Dmitry,
Now that your copyright assignment is complete, I've pushed this
series. I made a few changes, most notably to ppc/svindex.d so that
the test passed.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH 0/5] ppc/svp64: support SVP64 and its first insns
2022-08-11 9:14 ` Alan Modra
@ 2022-08-11 10:48 ` lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
1 sibling, 0 replies; 62+ messages in thread
From: lkcl @ 2022-08-11 10:48 UTC (permalink / raw)
To: Alan Modra; +Cc: Dmitry Selyutin, binutils
On Thursday, August 11, 2022, Alan Modra <amodra@gmail.com> wrote:
> On Mon, Jul 25, 2022 at 04:10:13PM +0300, Dmitry Selyutin wrote:
> Hi Dmitry,
> Now that your copyright assignment is complete, I've pushed this
> series. I made a few changes, most notably to ppc/svindex.d so that
> the test passed.
with many thanks, Alan, we have some draft scalar instructions
to add (OPF External RFCs to accompany them over time) and it
will be a lot easier now. Less patchsets to maintain.
Also fyi I have added Pack/Unpack to SVP64 (a generalisation
of VSX vpack and vunpack extended to vec2/3/4 and applying
to multiple instructions, LDST immediates are the obvious
ones, sv.fmv as well, which other ops need more thought)
This will mean however that some of opc-ppc-svp64.c/h will
be re-generated, with new SVP64 classifications and room
in the 24-bit for Pack and Unpack bits.
Just a headsup what to expect.
Also many many thanks to Dmitry for patiently maintaining this
patch series whilst the Copyright assignment was being
processed.
L.
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns
2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
@ 2022-08-12 3:30 ` Dmitry Selyutin
1 sibling, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-08-12 3:30 UTC (permalink / raw)
To: Alan Modra; +Cc: binutils, Luke Kenneth Casson Leighton
On Thu, Aug 11, 2022 at 12:14 PM Alan Modra <amodra@gmail.com> wrote:
> Hi Dmitry,
> Now that your copyright assignment is complete, I've pushed this
> series. I made a few changes, most notably to ppc/svindex.d so that
> the test passed.
Hi Alan, thank you for your help and guidance! I'll publish some new
patches soon.
--
Best regards,
Dmitry Selyutin
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
@ 2022-08-15 6:18 ` Jan Beulich
2022-08-15 12:58 ` lkcl
0 siblings, 1 reply; 62+ messages in thread
From: Jan Beulich @ 2022-08-15 6:18 UTC (permalink / raw)
To: Dmitry Selyutin; +Cc: Luke Kenneth Casson Leighton, binutils
On 25.07.2022 15:10, Dmitry Selyutin via Binutils wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/ppc/setvl.d
> @@ -0,0 +1,15 @@
> +#as: -mlibresoc
> +#objdump: -dr -Mlibresoc
> +
> +.*: file format .*
> +
> +
> +Disassembly of section \.text:
> +0+ <\.text>:
> +.*: (37 00 00 58|58 00 00 37) setvl. r0,r0,1,0,0,0
> +.*: (36 00 00 58|58 00 00 36) setvl r0,r0,1,0,0,0
> +.*: (36 00 e0 5b|5b e0 00 36) setvl r31,r0,1,0,0,0
> +.*: (36 00 1f 58|58 1f 00 36) setvl r0,r31,1,0,0,0
> +.*: (36 7e 00 58|58 00 7e 36) setvl r0,r0,64,0,0,0
> +.*: (76 00 00 58|58 00 00 76) setvl r0,r0,1,1,0,0
> +.*: (b6 00 00 58|58 00 00 b6) setvl r0,r0,1,0,1,0
Out of curiosity - was it intentional to omit a case with the last
operand non-zero?
> @@ -6769,6 +6789,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
> {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
>
> +{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
> +{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
> +
> {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
> {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
> {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
According to the web page SETVL has a number of pseudos. I guess
you've omitted those for simplicity in the initial submission.
I'd like to point out though that the web page isn't really
crystal clear as to, in particular, the Rc field's applicability
to every one of the pseudos. (There's also a typo or two which
makes things a little ambiguous, but there it's reasonably clear
what is actually meant.)
Jan
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions
2022-08-15 6:18 ` Jan Beulich
@ 2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
0 siblings, 2 replies; 62+ messages in thread
From: lkcl @ 2022-08-15 12:58 UTC (permalink / raw)
To: Jan Beulich; +Cc: Dmitry Selyutin, binutils
On Mon, Aug 15, 2022 at 7:18 AM Jan Beulich <jbeulich@suse.com> wrote:
> On 25.07.2022 15:10, Dmitry Selyutin via Binutils wrote:
> > +Disassembly of section \.text:
> > +0+ <\.text>:
> > +.*: (37 00 00 58|58 00 00 37) setvl. r0,r0,1,0,0,0
> Out of curiosity - was it intentional to omit a case with the last
> operand non-zero?
one for Dmitry - i believe these are all auto-generated?
> > @@ -6769,6 +6789,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> > +{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
> > +{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
> According to the web page SETVL has a number of pseudos.
yes.
> I guess you've omitted those for simplicity in the initial submission.
and because there's a python-based (very-easy-to-hack) program
which does the same job as gas, turning SVP64 assembler into
".long xxx; v3.0opcode", and it doesn't have pseudo-ops.
> I'd like to point out though that the web page isn't really
> crystal clear as to, in particular, the Rc field's applicability
> to every one of the pseudos.
ah appreciated, i've added examples. more will be needed now that
there's also setvl-from-CTR as well.
> (There's also a typo or two which
> makes things a little ambiguous, but there it's reasonably clear
> what is actually meant.)
appreciated. any feedback is more than welcome. context there:
despite now being an Open ISA the amount of attention Power is
getting is surprisingly low. hence any assistance and feedback
is all the more precious.
l.
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions
2022-08-15 12:58 ` lkcl
@ 2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
1 sibling, 0 replies; 62+ messages in thread
From: Dmitry Selyutin @ 2022-08-15 13:08 UTC (permalink / raw)
To: lkcl; +Cc: Jan Beulich, binutils
On Mon, Aug 15, 2022 at 9:18 AM Jan Beulich <jbeulich@suse.com> wrote:
> Out of curiosity - was it intentional to omit a case with the last
> operand non-zero?
Nice catch! This was not intentional, I'll submit the patch to handle
this case. Perhaps I either forgot to add this line, or removed it
somehow...
On Mon, Aug 15, 2022 at 3:59 PM lkcl <luke.leighton@gmail.com> wrote:
> one for Dmitry - i believe these are all auto-generated?
Except for the very first revisions with huge tests, I added the tests
manually. One of the issues for generation is that we don't, in fact,
maintain information about whether some operands should be non-zero.
Another issue was that, until very recently, we had to generate the
instructions manually, not from the parsed fields. In fact, we still
encode these instructions manually even now, but at least now we have
instruments to stop doing it.
For now, I'll simply update the test; in an ideal world, yes, we
should generate these tests.
--
Best regards,
Dmitry Selyutin
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions
2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
@ 2022-08-21 14:53 ` Jan Beulich
2022-08-21 16:04 ` lkcl
1 sibling, 1 reply; 62+ messages in thread
From: Jan Beulich @ 2022-08-21 14:53 UTC (permalink / raw)
To: lkcl; +Cc: Dmitry Selyutin, binutils
On 15.08.2022 14:58, lkcl wrote:
> On Mon, Aug 15, 2022 at 7:18 AM Jan Beulich <jbeulich@suse.com> wrote:
>> I'd like to point out though that the web page isn't really
>> crystal clear as to, in particular, the Rc field's applicability
>> to every one of the pseudos.
>
> ah appreciated, i've added examples. more will be needed now that
> there's also setvl-from-CTR as well.
Since you've added the further examples without altering the first
register operand for the expansion of setvli - is that really meant
to be r5, not r0?
>> (There's also a typo or two which
>> makes things a little ambiguous, but there it's reasonably clear
>> what is actually meant.)
>
> appreciated. any feedback is more than welcome. context there:
> despite now being an Open ISA the amount of attention Power is
> getting is surprisingly low. hence any assistance and feedback
> is all the more precious.
Is there any preferred way for providing feedback, just in case I
would spot further little issues? I've responded to the patches
to binutils mainly because I didn't know anything "better" ...
Jan
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions
2022-08-21 14:53 ` Jan Beulich
@ 2022-08-21 16:04 ` lkcl
0 siblings, 0 replies; 62+ messages in thread
From: lkcl @ 2022-08-21 16:04 UTC (permalink / raw)
To: Jan Beulich; +Cc: Dmitry Selyutin, binutils
On Sun, Aug 21, 2022 at 3:53 PM Jan Beulich <jbeulich@suse.com> wrote:
> On 15.08.2022 14:58, lkcl wrote:
> > ah appreciated, i've added examples. more will be needed now that
> > there's also setvl-from-CTR as well.
>
> Since you've added the further examples without altering the first
> register operand for the expansion of setvli - is that really meant
> to be r5, not r0?
well-spotted: the addition of the CTR mode post-dates the creation
of those pseudo-ops, i've now corrected them. it is slightly irksome
that the cost of adding CTR mode was at the expense of losing the
ability to set RT to an immediate, but this may be achieved with
addi RT,0,#N. go figure.
> Is there any preferred way for providing feedback, just in case I
> would spot further little issues? I've responded to the patches
> to binutils mainly because I didn't know anything "better" ...
appreciated. in order of approx precedence (coincidentally,
reverse-convenience):
* directly on the bugtracker bugs.libre-soc.org although contact
me privately about that, i had to disable account-creation after
someone used the bugtracker to advertise juniper networks at us
* the mailing list (mailman: i can authorise sending permission if
you prefer not to subscribe: i.e. just send, and i'll deal with it)
https://lists.libre-soc.org/mailman/listinfo/libre-soc-dev
* IRC - libera.chat - #libre-soc channel: if you prefer there is a
Matrix Bridge (run by the libera team) and yet _another_ way
is via the OPF's mattermost bridge
https://chat.openpower.foundation/opf/channels/libre-soc
all messages are logged https://libre-soc.org/irclog/index.html
as we're under Audit Conditions (EU Funding, NLnet "works for
public good") everything is logged/public, but obviously if you're
used to FOSS then nothing's new :)
l.
^ permalink raw reply [flat|nested] 62+ messages in thread
end of thread, other threads:[~2022-08-21 16:04 UTC | newest]
Thread overview: 62+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
2022-06-21 11:55 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-21 18:25 ` Peter Bergner
2022-06-21 18:39 ` Peter Bergner
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
2022-06-22 6:44 ` Jan Beulich
2022-06-22 6:57 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
2022-06-23 19:58 ` lkcl
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 2/6] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-08-15 6:18 ` Jan Beulich
2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
2022-08-21 16:04 ` lkcl
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-27 4:53 ` Alan Modra
2022-07-27 6:38 ` lkcl
2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
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