* [PATCH 00/43] aarch64: Groundwork for SME2 support
@ 2023-03-30 10:23 Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
` (42 more replies)
0 siblings, 43 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This series of patches lays some groundwork for the aarch64 SME2 support.
It's a bit of a mixed bag, but most of the patches fall into two groups:
- Try to improve the error messages reported for invalid asm.
- Reorganise the code in ways that makes SME2 easier to add.
Each patch really stands alone, with its own justification.
I just thought it was worth lumping them into a series for
organisation reasons. Sorry that it's quite long.
Tested on aarch64-linux-gnu & pushed under GWP. I'm more than happy
to update/adjust/fix based on post-commit review though, so please
let me know if you spot anything you think should be changed.
Thanks,
Richard
Richard Sandiford (43):
aarch64: Fix PSEL opcode mask
aarch64: Restrict range of PRFM opcodes
aarch64: Fix SVE2 register/immediate distinction
aarch64: Make SME instructions use F_STRICT
aarch64: Use aarch64_operand_error more widely
aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*
aarch64: Add REG_TYPE_ZATHV
aarch64: Move vectype_to_qualifier further up
aarch64: Rework parse_typed_reg interface
aarch64: Reuse parse_typed_reg for ZA tiles
aarch64: Consolidate ZA tile range checks
aarch64: Treat ZA as a register
aarch64: Rename za_tile_vector to za_index
aarch64: Make indexed_za use 64-bit immediates
aarch64: Pass aarch64_indexed_za to parsers
aarch64: Move ZA range checks to aarch64-opc.c
aarch64: Consolidate ZA slice parsing
aarch64: Commonise index parsing
aarch64: Move w12-w15 range check to libopcodes
aarch64: Tweak error for missing immediate offset
aarch64: Tweak errors for base & offset registers
aarch64: Tweak parsing of integer & FP registers
aarch64: Improve errors for malformed register lists
aarch64: Try to avoid inappropriate default errors
aarch64: Rework reporting of failed register checks
aarch64: Update operand_mismatch_kind_names
aarch64: Deprioritise AARCH64_OPDE_REG_LIST
aarch64: Add an error code for out-of-range registers
aarch64: Commonise checks for index operands
aarch64: Add an operand class for SVE register lists
aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield
aarch64: Tweak register list errors
aarch64: Try to report invalid variants against the closest match
aarch64: Tweak priorities of parsing-related errors
aarch64: Rename aarch64-tbl.h OP_SME_* macros
aarch64: Reorder some OP_SVE_* macros
aarch64: Add a aarch64_cpu_supports_inst_p helper
aarch64: Rename some of GAS's REG_TYPE_* macros
aarch64: Regularise FLD_* suffixes
aarch64: Resync field names
aarch64: Sort fields alphanumerically
aarch64: Add support for strided register lists
aarch64: Prefer register ranges & support wrapping
gas/config/tc-aarch64.c | 1729 +++++++++--------
.../aarch64/armv8_2-a-crypto-fp16-illegal.l | 6 +-
gas/testsuite/gas/aarch64/diagnostic.l | 49 +-
gas/testsuite/gas/aarch64/diagnostic.s | 23 +
gas/testsuite/gas/aarch64/illegal-bfloat16.l | 40 +-
gas/testsuite/gas/aarch64/illegal-fjcvtzs.l | 6 +-
gas/testsuite/gas/aarch64/illegal-ldapr.l | 6 +-
gas/testsuite/gas/aarch64/illegal-ldraa.l | 8 +-
gas/testsuite/gas/aarch64/illegal-lse.l | 456 ++---
gas/testsuite/gas/aarch64/illegal-memtag.l | 70 +-
gas/testsuite/gas/aarch64/illegal-sve2.l | 1709 ++++++++--------
gas/testsuite/gas/aarch64/illegal-sve2.s | 5 +
gas/testsuite/gas/aarch64/illegal.l | 6 +-
gas/testsuite/gas/aarch64/illegal.s | 5 +
gas/testsuite/gas/aarch64/legacy_reg_names.l | 4 +-
gas/testsuite/gas/aarch64/mops_invalid.l | 112 +-
.../gas/aarch64/neon-vfp-reglist-post.d | 184 +-
gas/testsuite/gas/aarch64/neon-vfp-reglist.d | 100 +-
gas/testsuite/gas/aarch64/reglist-1.d | 21 +
gas/testsuite/gas/aarch64/reglist-1.s | 15 +
gas/testsuite/gas/aarch64/reglist-2.d | 3 +
gas/testsuite/gas/aarch64/reglist-2.l | 8 +
gas/testsuite/gas/aarch64/reglist-2.s | 7 +
gas/testsuite/gas/aarch64/sme-2-illegal.l | 42 +-
gas/testsuite/gas/aarch64/sme-3-illegal.l | 20 +-
gas/testsuite/gas/aarch64/sme-4-illegal.l | 54 +-
gas/testsuite/gas/aarch64/sme-4-illegal.s | 12 +
gas/testsuite/gas/aarch64/sme-5-illegal.l | 91 +-
gas/testsuite/gas/aarch64/sme-5-illegal.s | 7 +
gas/testsuite/gas/aarch64/sme-6-illegal.l | 82 +-
gas/testsuite/gas/aarch64/sme-7-illegal.l | 51 +-
gas/testsuite/gas/aarch64/sme-7-illegal.s | 15 +
gas/testsuite/gas/aarch64/sme-8-illegal.l | 12 +-
gas/testsuite/gas/aarch64/sme-9-illegal.l | 37 +-
gas/testsuite/gas/aarch64/sme-9-illegal.s | 7 +
gas/testsuite/gas/aarch64/sme-9.d | 3 +
gas/testsuite/gas/aarch64/sme-9.s | 5 +
gas/testsuite/gas/aarch64/sme-illegal.l | 119 +-
gas/testsuite/gas/aarch64/sme-illegal.s | 1 +
gas/testsuite/gas/aarch64/sve-invalid.l | 44 +-
gas/testsuite/gas/aarch64/sve-invalid.s | 7 +
.../gas/aarch64/sve-reg-diagnostic.l | 16 +-
gas/testsuite/gas/aarch64/sve.d | 1612 +++++++--------
gas/testsuite/gas/aarch64/sve2.d | 30 +-
gas/testsuite/gas/aarch64/system.d | 18 +-
gas/testsuite/gas/aarch64/system.s | 5 +
gas/testsuite/gas/aarch64/tme-invalid.l | 6 +-
gas/testsuite/gas/aarch64/verbose-error.l | 2 +-
include/opcode/aarch64.h | 91 +-
opcodes/aarch64-asm.c | 30 +-
opcodes/aarch64-dis.c | 133 +-
opcodes/aarch64-opc-2.c | 38 +-
opcodes/aarch64-opc.c | 456 +++--
opcodes/aarch64-opc.h | 167 +-
opcodes/aarch64-tbl.h | 263 ++-
55 files changed, 4260 insertions(+), 3788 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/reglist-1.d
create mode 100644 gas/testsuite/gas/aarch64/reglist-1.s
create mode 100644 gas/testsuite/gas/aarch64/reglist-2.d
create mode 100644 gas/testsuite/gas/aarch64/reglist-2.l
create mode 100644 gas/testsuite/gas/aarch64/reglist-2.s
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 01/43] aarch64: Fix PSEL opcode mask
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
` (41 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
The opcode mask for PSEL was missing some bits, which meant
that some upcoming SME2 opcodes would be misinterpreted as PSELs.
---
gas/testsuite/gas/aarch64/sme-9.d | 3 +++
gas/testsuite/gas/aarch64/sme-9.s | 5 +++++
opcodes/aarch64-tbl.h | 2 +-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d
index ef314c61451..9a6175c3906 100644
--- a/gas/testsuite/gas/aarch64/sme-9.d
+++ b/gas/testsuite/gas/aarch64/sme-9.d
@@ -71,3 +71,6 @@ Disassembly of section \.text:
f4: 44cbc544 uclamp z4.d, z10.d, z11.d
f8: 25277c61 psel p1, p15, p3.b\[w15, 0\]
fc: 252778a2 psel p2, p14, p5.b\[w15, 0\]
+ 100: 25244200 \.inst 0x25244200 ; undefined
+ 104: 25244010 \.inst 0x25244010 ; undefined
+ 108: 25244210 \.inst 0x25244210 ; undefined
diff --git a/gas/testsuite/gas/aarch64/sme-9.s b/gas/testsuite/gas/aarch64/sme-9.s
index be8511fe3df..495a7f9fbf0 100644
--- a/gas/testsuite/gas/aarch64/sme-9.s
+++ b/gas/testsuite/gas/aarch64/sme-9.s
@@ -84,3 +84,8 @@ foo .req p1
bar .req w15
psel foo, p15, p3.b[w15, 0]
psel p2, p14, p5.b[bar, 0]
+
+// These were previously incorrectly decoded as PSELs.
+.inst 0x25244200
+.inst 0x25244010
+.inst 0x25244210
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 69703650471..96e6c136282 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- SME_INSN ("psel", 0x25204000, 0xff20c000, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+ SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 02/43] aarch64: Restrict range of PRFM opcodes
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
` (40 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
In the register-index forms of PRFM, the unallocated prefetch opcodes
24-31 have been reused for the encoding of the new RPRFM instruction.
The PRFM opcode space is now capped at 23 for these forms. The other
forms of PRFM are unaffected.
---
gas/testsuite/gas/aarch64/illegal.l | 6 +++++-
gas/testsuite/gas/aarch64/illegal.s | 5 +++++
gas/testsuite/gas/aarch64/system.d | 18 ++----------------
gas/testsuite/gas/aarch64/system.s | 5 +++++
opcodes/aarch64-opc.c | 9 +++++++++
5 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 65bd38afd7a..ae9bb939728 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -879,4 +879,8 @@
[^:]*:593: Error: .*`st2 {v0\.16b-v1\.16b}\[1\],\[x0\]'
[^:]*:594: Error: .*`st3 {v0\.16b-v2\.16b}\[2\],\[x0\]'
[^:]*:595: Error: .*`st4 {v0\.8b-v3\.8b}\[4\],\[x0\]'
-[^:]*:597: Error: .*
+[^:]*:597: Error: the register-index form of PRFM does not accept opcodes in the range 24-31 at operand 1 -- `prfm #0x18,\[sp,x15,lsl#0\]'
+[^:]*:598: Error: the register-index form of PRFM does not accept opcodes in the range 24-31 at operand 1 -- `prfm #0x1f,\[sp,x15,lsl#0\]'
+[^:]*:599: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm #0x20,\[sp,x15,lsl#0\]'
+[^:]*:600: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm #0x20,FOO'
+[^:]*:602: Error: .*
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index 384b673e8fb..6fb637ab923 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -594,4 +594,9 @@ one_label:
st3 {v0.16b-v2.16b}[2],[x0]
st4 {v0.8b-v3.8b}[4],[x0]
+ prfm #0x18, [sp, x15, lsl #0]
+ prfm #0x1f, [sp, x15, lsl #0]
+ prfm #0x20, [sp, x15, lsl #0]
+ prfm #0x20, FOO
+
// End (for errors during literal pool generation)
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index 93c84a72982..7e4bafbf1ff 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -330,43 +330,27 @@ Disassembly of section \.text:
.*: f9800c77 prfm #0x17, \[x3, #24\]
.*: d8000018 prfm #0x18, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bf8 prfm #0x18, \[sp, x15\]
-.*: f8be58f8 prfm #0x18, \[x7, w30, uxtw #3\]
.*: f9800c78 prfm #0x18, \[x3, #24\]
.*: d8000019 prfm #0x19, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bf9 prfm #0x19, \[sp, x15\]
-.*: f8be58f9 prfm #0x19, \[x7, w30, uxtw #3\]
.*: f9800c79 prfm #0x19, \[x3, #24\]
.*: d800001a prfm #0x1a, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfa prfm #0x1a, \[sp, x15\]
-.*: f8be58fa prfm #0x1a, \[x7, w30, uxtw #3\]
.*: f9800c7a prfm #0x1a, \[x3, #24\]
.*: d800001b prfm #0x1b, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfb prfm #0x1b, \[sp, x15\]
-.*: f8be58fb prfm #0x1b, \[x7, w30, uxtw #3\]
.*: f9800c7b prfm #0x1b, \[x3, #24\]
.*: d800001c prfm #0x1c, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfc prfm #0x1c, \[sp, x15\]
-.*: f8be58fc prfm #0x1c, \[x7, w30, uxtw #3\]
.*: f9800c7c prfm #0x1c, \[x3, #24\]
.*: d800001d prfm #0x1d, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfd prfm #0x1d, \[sp, x15\]
-.*: f8be58fd prfm #0x1d, \[x7, w30, uxtw #3\]
.*: f9800c7d prfm #0x1d, \[x3, #24\]
.*: d800001e prfm #0x1e, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bfe prfm #0x1e, \[sp, x15\]
-.*: f8be58fe prfm #0x1e, \[x7, w30, uxtw #3\]
.*: f9800c7e prfm #0x1e, \[x3, #24\]
.*: d800001f prfm #0x1f, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bff prfm #0x1f, \[sp, x15\]
-.*: f8be58ff prfm #0x1f, \[x7, w30, uxtw #3\]
.*: f9800c7f prfm #0x1f, \[x3, #24\]
.*: f9800c60 prfm pldl1keep, \[x3, #24\]
.*: f9800c61 prfm pldl1strm, \[x3, #24\]
@@ -386,3 +370,5 @@ Disassembly of section \.text:
.*: f9800c73 prfm pstl2strm, \[x3, #24\]
.*: f9800c74 prfm pstl3keep, \[x3, #24\]
.*: f9800c75 prfm pstl3strm, \[x3, #24\]
+.*: f8a04817 prfm #0x17, \[x0, w0, uxtw\]
+.*: f8a04818 \.inst 0xf8a04818 ; undefined
diff --git a/gas/testsuite/gas/aarch64/system.s b/gas/testsuite/gas/aarch64/system.s
index 4d24d9a7614..48e7bfeb103 100644
--- a/gas/testsuite/gas/aarch64/system.s
+++ b/gas/testsuite/gas/aarch64/system.s
@@ -70,8 +70,10 @@
.macro all_prefetchs op, from=0, to=31
\op \from, LABEL1
+ .if \from < 24
\op \from, [sp, x15, lsl #0]
\op \from, [x7, w30, uxtw #3]
+ .endif
\op \from, [x3, #24]
.if \to-\from
all_prefetchs \op, "(\from+1)", \to
@@ -91,3 +93,6 @@
.endr
.endr
.endr
+
+ .inst 0xf8a04817
+ .inst 0xf8a04818
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e271b0d5e8e..a0e6240592c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2599,6 +2599,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
}
break;
+ case AARCH64_OPND_PRFOP:
+ if (opcode->iclass == ldst_regoff && opnd->prfop->value >= 24)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("the register-index form of PRFM does"
+ " not accept opcodes in the range 24-31"));
+ return 0;
+ }
+ break;
default:
break;
}
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
` (39 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
GAS refuses to interpret register names like x0 as unadorned
immediates, due to the obvious potential for confusion with
register operands. (An explicit #x0 is OK.)
For compatibility reasons, we can't extend the set of registers
that GAS rejects for existing instructions. For example:
mov x0, z0
was valid code before SVE was added, so it needs to stay valid
code even when SVE is enabled. But we can make GAS reject newer
registers in newer instructions. The SVE instruction:
and z0.s, z0.s, z0.h
is therefore invalid, rather than z0.h being an immediate.
This patch extends the SVE behaviour to SVE2. The old call
to AARCH64_CPU_HAS_FEATURE was technically the wrong way around,
although it didn't matter in practice for base SVE instructions
since their avariants only set SVE.
---
gas/config/tc-aarch64.c | 4 +++-
gas/testsuite/gas/aarch64/illegal-sve2.l | 7 +++++++
gas/testsuite/gas/aarch64/illegal-sve2.s | 3 +++
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index eb28ea3dce2..67b0e61a7ff 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6350,7 +6350,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
clear_error ();
skip_whitespace (str);
- if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant))
+ if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
+ AARCH64_FEATURE_SVE
+ | AARCH64_FEATURE_SVE2))
imm_reg_type = REG_TYPE_R_Z_SP_BHSDQ_VZP;
else
imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 7656c2f91b1..c3ef21aa6d9 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -3328,3 +3328,10 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#33'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `xar z0\.d,z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z1\.s,p0/m,z1\.s,z0\.h'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sqshl z1\.s, p0/m, z1\.s, z0\.s
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sqshl z1\.b, p0/m, z1\.b, z0\.b
+[^ :]+:[0-9]+: Info: sqshl z1\.h, p0/m, z1\.h, z0\.h
+[^ :]+:[0-9]+: Info: sqshl z1\.d, p0/m, z1\.d, z0\.d
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s
index 8ad7fbf1d1b..3f3602a8474 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.s
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.s
@@ -2072,3 +2072,6 @@ xar z0.s, z0.s, z0.s, #0
xar z0.s, z0.s, z0.s, #33
xar z0.d, z0.d, z0.d, #0
xar z0.d, z0.d, z0.d, #64
+
+.equ z0.h, 1
+sqshl z1.s, p0/m, z1.s, z0.h
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 04/43] aarch64: Make SME instructions use F_STRICT
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (2 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
` (38 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch makes all SME instructions use F_STRICT, so that qualifiers
have to be provided explicitly rather than being inferred from other
operands. The main change is to move the qualifier setting from the
operand-level decoders to the opcode level.
This is one step towards consolidating the ZA parsing code and
extending it to handle SME2.
---
include/opcode/aarch64.h | 2 +
opcodes/aarch64-asm.c | 8 +++-
opcodes/aarch64-dis.c | 93 ++++++++++++++++++++--------------------
opcodes/aarch64-tbl.h | 18 ++++----
4 files changed, 64 insertions(+), 57 deletions(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d0a0b629d99..691247aa934 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -659,7 +659,9 @@ enum aarch64_insn_class
pcreladdr,
ic_system,
sme_misc,
+ sme_mov,
sme_ldr,
+ sme_psel,
sme_str,
sme_start,
sme_stop,
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e050197e8be..bfabcb9e3a2 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1852,6 +1852,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
int variant = 0;
switch (inst->opcode->iclass)
{
+ case sme_mov:
+ case sme_psel:
+ /* The variant is encoded as part of the immediate. */
+ break;
+
case sve_cpy:
insert_fields (&inst->value, aarch64_get_variant (inst),
0, 2, FLD_SVE_M_14, FLD_size);
@@ -1872,8 +1877,9 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
encoding. */
break;
+ case sme_misc:
case sve_misc:
- /* sve_misc instructions have only a single variant. */
+ /* These instructions have only a single variant. */
break;
case sve_movprfx:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 02ce8345979..01881ea377d 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1785,44 +1785,35 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
/* Deduce qualifier encoded in size and Q fields. */
if (fld_size == 0)
- info->qualifier = AARCH64_OPND_QLF_S_B;
- else if (fld_size == 1)
- info->qualifier = AARCH64_OPND_QLF_S_H;
- else if (fld_size == 2)
- info->qualifier = AARCH64_OPND_QLF_S_S;
- else if (fld_size == 3 && fld_q == 0)
- info->qualifier = AARCH64_OPND_QLF_S_D;
- else if (fld_size == 3 && fld_q == 1)
- info->qualifier = AARCH64_OPND_QLF_S_Q;
-
- info->za_tile_vector.index.regno = fld_rv + 12;
- info->za_tile_vector.v = fld_v;
-
- switch (info->qualifier)
{
- case AARCH64_OPND_QLF_S_B:
info->za_tile_vector.regno = 0;
info->za_tile_vector.index.imm = fld_zan_imm;
- break;
- case AARCH64_OPND_QLF_S_H:
+ }
+ else if (fld_size == 1)
+ {
info->za_tile_vector.regno = fld_zan_imm >> 3;
info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
- break;
- case AARCH64_OPND_QLF_S_S:
+ }
+ else if (fld_size == 2)
+ {
info->za_tile_vector.regno = fld_zan_imm >> 2;
info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
- break;
- case AARCH64_OPND_QLF_S_D:
+ }
+ else if (fld_size == 3 && fld_q == 0)
+ {
info->za_tile_vector.regno = fld_zan_imm >> 1;
info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
- break;
- case AARCH64_OPND_QLF_S_Q:
+ }
+ else if (fld_size == 3 && fld_q == 1)
+ {
info->za_tile_vector.regno = fld_zan_imm;
info->za_tile_vector.index.imm = 0;
- break;
- default:
- return false;
}
+ else
+ return false;
+
+ info->za_tile_vector.index.regno = fld_rv + 12;
+ info->za_tile_vector.v = fld_v;
return true;
}
@@ -1914,26 +1905,14 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
info->za_tile_vector.regno = fld_pn;
info->za_tile_vector.index.regno = fld_rm + 12;
- if (fld_tszh == 0x1 && fld_tszl == 0x0)
- {
- info->qualifier = AARCH64_OPND_QLF_S_D;
- imm = fld_i1;
- }
- else if (fld_tszl == 0x4)
- {
- info->qualifier = AARCH64_OPND_QLF_S_S;
- imm = (fld_i1 << 1) | fld_tszh;
- }
- else if ((fld_tszl & 0x3) == 0x2)
- {
- info->qualifier = AARCH64_OPND_QLF_S_H;
- imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
- }
- else if (fld_tszl & 0x1)
- {
- info->qualifier = AARCH64_OPND_QLF_S_B;
- imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
- }
+ if (fld_tszl & 0x1)
+ imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
+ else if (fld_tszl & 0x2)
+ imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
+ else if (fld_tszl & 0x4)
+ imm = (fld_i1 << 1) | fld_tszh;
+ else if (fld_tszh)
+ imm = fld_i1;
else
return false;
@@ -2975,6 +2954,25 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = 0;
switch (inst->opcode->iclass)
{
+ case sme_mov:
+ variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10);
+ if (variant >= 4 && variant < 7)
+ return false;
+ if (variant == 7)
+ variant = 4;
+ break;
+
+ case sme_psel:
+ i = extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl);
+ if (i == 0)
+ return false;
+ while ((i & 1) == 0)
+ {
+ i >>= 1;
+ variant += 1;
+ }
+ break;
+
case sve_cpy:
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
break;
@@ -3002,8 +3000,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = 3;
break;
+ case sme_misc:
case sve_misc:
- /* sve_misc instructions have only a single variant. */
+ /* These instructions have only a single variant. */
break;
case sve_movprfx:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 96e6c136282..6c2862eacf3 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2650,16 +2650,16 @@ static const aarch64_feature_set aarch64_feature_cssc =
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
- FLAGS, 0, TIED, NULL }
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \
- FLAGS, 0, TIED, NULL }
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \
- FLAGS, 0, TIED, NULL }
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
- FLAGS, CONSTRAINTS, TIED, NULL }
+ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@@ -5238,10 +5238,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
@@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+ SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 05/43] aarch64: Use aarch64_operand_error more widely
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (3 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
` (37 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
GAS's aarch64_instruction had its own cut-down error record,
but it's better for later patches if it reuses the binutils-wide
aarch64_operand_error instead. The main difference is that
aarch64_operand_error can store arguments to the error while
aarch64_instruction couldn't.
---
gas/config/tc-aarch64.c | 30 ++++++++----------------------
1 file changed, 8 insertions(+), 22 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 67b0e61a7ff..4e75946c684 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -155,11 +155,7 @@ struct aarch64_instruction
/* libopcodes structure for instruction intermediate representation. */
aarch64_inst base;
/* Record assembly errors found during the parsing. */
- struct
- {
- enum aarch64_operand_error_kind kind;
- const char *error;
- } parsing_error;
+ aarch64_operand_error parsing_error;
/* The condition that appears in the assembly line. */
int cond;
/* Relocation information (including the GAS internal fixup). */
@@ -195,8 +191,8 @@ static bool programmer_friendly_fixup (aarch64_instruction *);
static inline void
clear_error (void)
{
+ memset (&inst.parsing_error, 0, sizeof (inst.parsing_error));
inst.parsing_error.kind = AARCH64_OPDE_NIL;
- inst.parsing_error.error = NULL;
}
static inline bool
@@ -205,21 +201,11 @@ error_p (void)
return inst.parsing_error.kind != AARCH64_OPDE_NIL;
}
-static inline const char *
-get_error_message (void)
-{
- return inst.parsing_error.error;
-}
-
-static inline enum aarch64_operand_error_kind
-get_error_kind (void)
-{
- return inst.parsing_error.kind;
-}
-
static inline void
set_error (enum aarch64_operand_error_kind kind, const char *error)
{
+ memset (&inst.parsing_error, 0, sizeof (inst.parsing_error));
+ inst.parsing_error.index = -1;
inst.parsing_error.kind = kind;
inst.parsing_error.error = error;
}
@@ -7733,15 +7719,15 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (error_p ())
{
+ inst.parsing_error.index = i;
DEBUG_TRACE ("parsing FAIL: %s - %s",
- operand_mismatch_kind_names[get_error_kind ()],
- get_error_message ());
+ operand_mismatch_kind_names[inst.parsing_error.kind],
+ inst.parsing_error.error);
/* Record the operand error properly; this is useful when there
are multiple instruction templates for a mnemonic name, so that
later on, we can select the error that most closely describes
the problem. */
- record_operand_error (opcode, i, get_error_kind (),
- get_error_message ());
+ record_operand_error_info (opcode, &inst.parsing_error);
return false;
}
else
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (4 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
` (36 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
The ZA tile registers were called REG_TYPE_ZA, REG_TYPE_ZAH and
REG_TYPE_ZAV. However, a later patch wants to make plain "za"
a register type too, and REG_TYPE_ZA is the obvious name for that.
This patch therefore adds "T" (tile) to the existing names.
---
gas/config/tc-aarch64.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 4e75946c684..c8b4129202c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -283,9 +283,9 @@ struct reloc_entry
BASIC_REG_TYPE(VN) /* v[0-31] */ \
BASIC_REG_TYPE(ZN) /* z[0-31] */ \
BASIC_REG_TYPE(PN) /* p[0-15] */ \
- BASIC_REG_TYPE(ZA) /* za[0-15] */ \
- BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
- BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
+ BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
+ BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
+ BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
/* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
/* Typecheck: same, plus SVE registers. */ \
@@ -4297,7 +4297,7 @@ static int
parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier)
{
int regno;
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZA, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZAT, qualifier);
if (reg == NULL)
return PARSE_FAIL;
@@ -4448,12 +4448,12 @@ parse_sme_za_hv_tiles_operand (char **str,
const reg_entry *reg;
qh = qv = *str;
- if ((reg = parse_reg_with_qual (&qh, REG_TYPE_ZAH, qualifier)) != NULL)
+ if ((reg = parse_reg_with_qual (&qh, REG_TYPE_ZATH, qualifier)) != NULL)
{
*slice_indicator = HV_horizontal;
*str = qh;
}
- else if ((reg = parse_reg_with_qual (&qv, REG_TYPE_ZAV, qualifier)) != NULL)
+ else if ((reg = parse_reg_with_qual (&qv, REG_TYPE_ZATV, qualifier)) != NULL)
{
*slice_indicator = HV_vertical;
*str = qv;
@@ -4566,7 +4566,8 @@ parse_sme_zero_mask(char **str)
q = *str;
do
{
- const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA, &qualifier);
+ const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZAT,
+ &qualifier);
if (reg)
{
int regno = reg->number;
@@ -8266,13 +8267,13 @@ static const reg_entry reg_names[] = {
REGSET16 (p, PN), REGSET16 (P, PN),
/* SME ZA tile registers. */
- REGSET16 (za, ZA), REGSET16 (ZA, ZA),
+ REGSET16 (za, ZAT), REGSET16 (ZA, ZAT),
/* SME ZA tile registers (horizontal slice). */
- REGSET16S (za, h, ZAH), REGSET16S (ZA, H, ZAH),
+ REGSET16S (za, h, ZATH), REGSET16S (ZA, H, ZATH),
/* SME ZA tile registers (vertical slice). */
- REGSET16S (za, v, ZAV), REGSET16S (ZA, V, ZAV)
+ REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV)
};
#undef REGDEF
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (5 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
` (35 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch adds a multi-register type that includes both REG_TYPE_ZATH
and REG_TYPE_ZATV. This slightly simplifies the existing code, but the
main purpose is to enable later patches.
---
gas/config/tc-aarch64.c | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c8b4129202c..98091f564d9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -326,6 +326,8 @@ struct reloc_entry
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
| REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ /* A horizontal or vertical slice of a ZA tile. */ \
+ MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
/* Pseudo type to mark the end of the enumerator sequence. */ \
BASIC_REG_TYPE(MAX)
@@ -4248,7 +4250,7 @@ parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
char *q;
reg_entry *reg = parse_reg (str);
- if (reg != NULL && reg->type == reg_type)
+ if (reg != NULL && aarch64_check_reg_type (reg, reg_type))
{
if (!skip_past_char (str, '.'))
{
@@ -4440,26 +4442,19 @@ parse_sme_za_hv_tiles_operand (char **str,
int *imm,
aarch64_opnd_qualifier_t *qualifier)
{
- char *qh, *qv;
int regno;
int regno_limit;
int64_t imm_limit;
int64_t imm_value;
const reg_entry *reg;
- qh = qv = *str;
- if ((reg = parse_reg_with_qual (&qh, REG_TYPE_ZATH, qualifier)) != NULL)
- {
- *slice_indicator = HV_horizontal;
- *str = qh;
- }
- else if ((reg = parse_reg_with_qual (&qv, REG_TYPE_ZATV, qualifier)) != NULL)
- {
- *slice_indicator = HV_vertical;
- *str = qv;
- }
- else
+ reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
+ if (!reg)
return PARSE_FAIL;
+
+ *slice_indicator = (aarch64_check_reg_type (reg, REG_TYPE_ZATH)
+ ? HV_horizontal
+ : HV_vertical);
regno = reg->number;
switch (*qualifier)
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 08/43] aarch64: Move vectype_to_qualifier further up
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (6 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
` (34 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch just moves vectype_to_qualifier further up, so that
a later patch can call it at an earlier point in the file.
No behavioural change intended.
---
gas/config/tc-aarch64.c | 150 ++++++++++++++++++++--------------------
1 file changed, 75 insertions(+), 75 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 98091f564d9..7de0f5c83f6 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -694,6 +694,81 @@ first_error_fmt (const char *format, ...)
}
}
+/* Internal helper routine converting a vector_type_el structure *VECTYPE
+ to a corresponding operand qualifier. */
+
+static inline aarch64_opnd_qualifier_t
+vectype_to_qualifier (const struct vector_type_el *vectype)
+{
+ /* Element size in bytes indexed by vector_el_type. */
+ const unsigned char ele_size[5]
+ = {1, 2, 4, 8, 16};
+ const unsigned int ele_base [5] =
+ {
+ AARCH64_OPND_QLF_V_4B,
+ AARCH64_OPND_QLF_V_2H,
+ AARCH64_OPND_QLF_V_2S,
+ AARCH64_OPND_QLF_V_1D,
+ AARCH64_OPND_QLF_V_1Q
+ };
+
+ if (!vectype->defined || vectype->type == NT_invtype)
+ goto vectype_conversion_fail;
+
+ if (vectype->type == NT_zero)
+ return AARCH64_OPND_QLF_P_Z;
+ if (vectype->type == NT_merge)
+ return AARCH64_OPND_QLF_P_M;
+
+ gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
+
+ if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
+ {
+ /* Special case S_4B. */
+ if (vectype->type == NT_b && vectype->width == 4)
+ return AARCH64_OPND_QLF_S_4B;
+
+ /* Special case S_2H. */
+ if (vectype->type == NT_h && vectype->width == 2)
+ return AARCH64_OPND_QLF_S_2H;
+
+ /* Vector element register. */
+ return AARCH64_OPND_QLF_S_B + vectype->type;
+ }
+ else
+ {
+ /* Vector register. */
+ int reg_size = ele_size[vectype->type] * vectype->width;
+ unsigned offset;
+ unsigned shift;
+ if (reg_size != 16 && reg_size != 8 && reg_size != 4)
+ goto vectype_conversion_fail;
+
+ /* The conversion is by calculating the offset from the base operand
+ qualifier for the vector type. The operand qualifiers are regular
+ enough that the offset can established by shifting the vector width by
+ a vector-type dependent amount. */
+ shift = 0;
+ if (vectype->type == NT_b)
+ shift = 3;
+ else if (vectype->type == NT_h || vectype->type == NT_s)
+ shift = 2;
+ else if (vectype->type >= NT_d)
+ shift = 1;
+ else
+ gas_assert (0);
+
+ offset = ele_base [vectype->type] + (vectype->width >> shift);
+ gas_assert (AARCH64_OPND_QLF_V_4B <= offset
+ && offset <= AARCH64_OPND_QLF_V_1Q);
+ return offset;
+ }
+
+ vectype_conversion_fail:
+ first_error (_("bad vector arrangement type"));
+ return AARCH64_OPND_QLF_NIL;
+}
+
/* Register parsing. */
/* Generic register parser which is called by other specialized
@@ -5905,81 +5980,6 @@ opcode_lookup (char *base, char *dot, char *end)
return NULL;
}
-/* Internal helper routine converting a vector_type_el structure *VECTYPE
- to a corresponding operand qualifier. */
-
-static inline aarch64_opnd_qualifier_t
-vectype_to_qualifier (const struct vector_type_el *vectype)
-{
- /* Element size in bytes indexed by vector_el_type. */
- const unsigned char ele_size[5]
- = {1, 2, 4, 8, 16};
- const unsigned int ele_base [5] =
- {
- AARCH64_OPND_QLF_V_4B,
- AARCH64_OPND_QLF_V_2H,
- AARCH64_OPND_QLF_V_2S,
- AARCH64_OPND_QLF_V_1D,
- AARCH64_OPND_QLF_V_1Q
- };
-
- if (!vectype->defined || vectype->type == NT_invtype)
- goto vectype_conversion_fail;
-
- if (vectype->type == NT_zero)
- return AARCH64_OPND_QLF_P_Z;
- if (vectype->type == NT_merge)
- return AARCH64_OPND_QLF_P_M;
-
- gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
-
- if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
- {
- /* Special case S_4B. */
- if (vectype->type == NT_b && vectype->width == 4)
- return AARCH64_OPND_QLF_S_4B;
-
- /* Special case S_2H. */
- if (vectype->type == NT_h && vectype->width == 2)
- return AARCH64_OPND_QLF_S_2H;
-
- /* Vector element register. */
- return AARCH64_OPND_QLF_S_B + vectype->type;
- }
- else
- {
- /* Vector register. */
- int reg_size = ele_size[vectype->type] * vectype->width;
- unsigned offset;
- unsigned shift;
- if (reg_size != 16 && reg_size != 8 && reg_size != 4)
- goto vectype_conversion_fail;
-
- /* The conversion is by calculating the offset from the base operand
- qualifier for the vector type. The operand qualifiers are regular
- enough that the offset can established by shifting the vector width by
- a vector-type dependent amount. */
- shift = 0;
- if (vectype->type == NT_b)
- shift = 3;
- else if (vectype->type == NT_h || vectype->type == NT_s)
- shift = 2;
- else if (vectype->type >= NT_d)
- shift = 1;
- else
- gas_assert (0);
-
- offset = ele_base [vectype->type] + (vectype->width >> shift);
- gas_assert (AARCH64_OPND_QLF_V_4B <= offset
- && offset <= AARCH64_OPND_QLF_V_1Q);
- return offset;
- }
-
- vectype_conversion_fail:
- first_error (_("bad vector arrangement type"));
- return AARCH64_OPND_QLF_NIL;
-}
-
/* Process an optional operand that is found omitted from the assembly line.
Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
instruction's opcode entry while IDX is the index of this omitted operand.
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 09/43] aarch64: Rework parse_typed_reg interface
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (7 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
` (33 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
parse_typed_reg returned a register number and passed the
register type back using a pointer parameter. It seems simpler
to return the register entry instead, since that has both pieces
of information in one place.
The patch also replaces the boolean in_reg_list parameter with
a mask of flags. This hopefully makes calls easier to read
(more self-documenting than "true" or "false"), but more
importantly, it allows a later patch to add a second flag.
---
gas/config/tc-aarch64.c | 124 +++++++++++++++++-----------------------
1 file changed, 53 insertions(+), 71 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 7de0f5c83f6..8c3d627a08b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1006,19 +1006,19 @@ parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
/* Parse a register of the type TYPE.
- Return PARSE_FAIL if the string pointed by *CCP is not a valid register
+ Return null if the string pointed to by *CCP is not a valid register
name or the parsed register is not of TYPE.
- Otherwise return the register number, and optionally fill in the actual
- type of the register in *RTYPE when multiple alternatives were given, and
- return the register shape and element index information in *TYPEINFO.
+ Otherwise return the register, and optionally return the register
+ shape and element index information in *TYPEINFO.
- IN_REG_LIST should be set with TRUE if the caller is parsing a register
- list. */
+ FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list. */
-static int
-parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
- struct vector_type_el *typeinfo, bool in_reg_list)
+#define PTR_IN_REGLIST (1U << 0)
+
+static const reg_entry *
+parse_typed_reg (char **ccp, aarch64_reg_type type,
+ struct vector_type_el *typeinfo, unsigned int flags)
{
char *str = *ccp;
const reg_entry *reg = parse_reg (&str);
@@ -1036,14 +1036,14 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
if (typeinfo)
*typeinfo = atype;
set_default_error ();
- return PARSE_FAIL;
+ return NULL;
}
if (! aarch64_check_reg_type (reg, type))
{
DEBUG_TRACE ("reg type check failed");
set_default_error ();
- return PARSE_FAIL;
+ return NULL;
}
type = reg->type;
@@ -1053,12 +1053,12 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
if (*str == '.')
{
if (!parse_vector_type_for_operand (type, &parsetype, &str))
- return PARSE_FAIL;
+ return NULL;
}
else
{
if (!parse_predication_for_operand (&parsetype, &str))
- return PARSE_FAIL;
+ return NULL;
}
/* Register if of the form Vn.[bhsdq]. */
@@ -1092,13 +1092,13 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
if (!is_typed_vecreg)
{
first_error (_("this type of register can't be indexed"));
- return PARSE_FAIL;
+ return NULL;
}
- if (in_reg_list)
+ if (flags & PTR_IN_REGLIST)
{
first_error (_("index not allowed inside register list"));
- return PARSE_FAIL;
+ return NULL;
}
atype.defined |= NTA_HASINDEX;
@@ -1108,19 +1108,19 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
if (exp.X_op != O_constant)
{
first_error (_("constant expression required"));
- return PARSE_FAIL;
+ return NULL;
}
if (! skip_past_char (&str, ']'))
- return PARSE_FAIL;
+ return NULL;
atype.index = exp.X_add_number;
}
- else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
+ else if (!(flags & PTR_IN_REGLIST) && (atype.defined & NTA_HASINDEX) != 0)
{
/* Indexed vector register expected. */
first_error (_("indexed vector register expected"));
- return PARSE_FAIL;
+ return NULL;
}
/* A vector reg Vn should be typed or indexed. */
@@ -1132,44 +1132,25 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
if (typeinfo)
*typeinfo = atype;
- if (rtype)
- *rtype = type;
-
*ccp = str;
- return reg->number;
+ return reg;
}
/* Parse register.
- Return the register number on success; return PARSE_FAIL otherwise.
-
- If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
- the register (e.g. NEON double or quad reg when either has been requested).
+ Return the register on success; return null otherwise.
If this is a NEON vector register with additional type information, fill
in the struct pointed to by VECTYPE (if non-NULL).
- This parser does not handle register list. */
+ This parser does not handle register lists. */
-static int
+static const reg_entry *
aarch64_reg_parse (char **ccp, aarch64_reg_type type,
- aarch64_reg_type *rtype, struct vector_type_el *vectype)
+ struct vector_type_el *vectype)
{
- struct vector_type_el atype;
- char *str = *ccp;
- int reg = parse_typed_reg (&str, type, rtype, &atype,
- /*in_reg_list= */ false);
-
- if (reg == PARSE_FAIL)
- return PARSE_FAIL;
-
- if (vectype)
- *vectype = atype;
-
- *ccp = str;
-
- return reg;
+ return parse_typed_reg (ccp, type, vectype, 0);
}
static inline bool
@@ -1239,14 +1220,15 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
str++; /* skip over '-' */
val_range = val;
}
- val = parse_typed_reg (&str, type, NULL, &typeinfo,
- /*in_reg_list= */ true);
- if (val == PARSE_FAIL)
+ const reg_entry *reg = parse_typed_reg (&str, type, &typeinfo,
+ PTR_IN_REGLIST);
+ if (!reg)
{
set_first_syntax_error (_("invalid vector register in list"));
error = true;
continue;
}
+ val = reg->number;
/* reject [bhsd]n */
if (type == REG_TYPE_VN && typeinfo.defined == 0)
{
@@ -2271,18 +2253,18 @@ const pseudo_typeS md_pseudo_table[] = {
static bool
reg_name_p (char *str, aarch64_reg_type reg_type)
{
- int reg;
+ const reg_entry *reg;
/* Prevent the diagnostics state from being spoiled. */
if (error_p ())
return false;
- reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
+ reg = aarch64_reg_parse (&str, reg_type, NULL);
/* Clear the parsing error that may be set by the reg parser. */
clear_error ();
- if (reg == PARSE_FAIL)
+ if (!reg)
return false;
skip_whitespace (str);
@@ -4957,8 +4939,8 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
} while (0)
#define po_reg_or_fail(regtype) do { \
- val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
- if (val == PARSE_FAIL) \
+ reg = aarch64_reg_parse (&str, regtype, NULL); \
+ if (!reg) \
{ \
set_default_error (); \
goto failure; \
@@ -6344,7 +6326,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
int64_t val;
const reg_entry *reg;
int comma_skipped_p = 0;
- aarch64_reg_type rtype;
struct vector_type_el vectype;
aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier;
aarch64_opnd_info *info = &inst.base.operands[i];
@@ -6443,16 +6424,17 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Vd:
case AARCH64_OPND_SVE_Vm:
case AARCH64_OPND_SVE_Vn:
- val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
- if (val == PARSE_FAIL)
+ reg = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, NULL);
+ if (!reg)
{
first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
goto failure;
}
- gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
+ gas_assert (reg->type >= REG_TYPE_FP_B
+ && reg->type <= REG_TYPE_FP_Q);
- info->reg.regno = val;
- info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
+ info->reg.regno = reg->number;
+ info->qualifier = AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B);
break;
case AARCH64_OPND_SVE_Pd:
@@ -6483,8 +6465,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Vm:
reg_type = REG_TYPE_VN;
vector_reg:
- val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
- if (val == PARSE_FAIL)
+ reg = aarch64_reg_parse (&str, reg_type, &vectype);
+ if (!reg)
{
first_error (_(get_reg_expected_msg (reg_type)));
goto failure;
@@ -6492,7 +6474,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (vectype.defined & NTA_HASINDEX)
goto failure;
- info->reg.regno = val;
+ info->reg.regno = reg->number;
if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN)
&& vectype.type == NT_invtype)
/* Unqualified Pn and Zn registers are allowed in certain
@@ -6509,8 +6491,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_VdD1:
case AARCH64_OPND_VnD1:
- val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
- if (val == PARSE_FAIL)
+ reg = aarch64_reg_parse (&str, REG_TYPE_VN, &vectype);
+ if (!reg)
{
set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
goto failure;
@@ -6521,7 +6503,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
(_("the top half of a 128-bit FP/SIMD register is expected"));
goto failure;
}
- info->reg.regno = val;
+ info->reg.regno = reg->number;
/* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
here; it is correct for the purpose of encoding/decoding since
only the register number is explicitly encoded in the related
@@ -6545,8 +6527,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SM3_IMM2:
reg_type = REG_TYPE_VN;
vector_reg_index:
- val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
- if (val == PARSE_FAIL)
+ reg = aarch64_reg_parse (&str, reg_type, &vectype);
+ if (!reg)
{
first_error (_(get_reg_expected_msg (reg_type)));
goto failure;
@@ -6554,7 +6536,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
goto failure;
- info->reglane.regno = val;
+ info->reglane.regno = reg->number;
info->reglane.index = vectype.index;
info->qualifier = vectype_to_qualifier (&vectype);
if (info->qualifier == AARCH64_OPND_QLF_NIL)
@@ -6576,13 +6558,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
&& get_opcode_dependent_value (opcode) == 1
&& *str != '{')
{
- val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
- if (val == PARSE_FAIL)
+ reg = aarch64_reg_parse (&str, reg_type, &vectype);
+ if (!reg)
{
first_error (_(get_reg_expected_msg (reg_type)));
goto failure;
}
- info->reglist.first_regno = val;
+ info->reglist.first_regno = reg->number;
info->reglist.num_regs = 1;
}
else
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (8 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
` (32 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch reuses the general parse_typed_reg for ZA tiles.
This involves adding a way of suppressing the usual treatment
of register indices, since ZA indices look very different from
Advanced SIMD and SVE vector indices.
---
gas/config/tc-aarch64.c | 98 ++++++++++++++++++++---------------------
1 file changed, 47 insertions(+), 51 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8c3d627a08b..f9e85b3d803 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -906,7 +906,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
gas_assert (*ptr == '.');
ptr++;
- if (reg_type == REG_TYPE_ZN || reg_type == REG_TYPE_PN || !ISDIGIT (*ptr))
+ if (reg_type != REG_TYPE_VN || !ISDIGIT (*ptr))
{
width = 0;
goto elt_size;
@@ -938,7 +938,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
element_size = 64;
break;
case 'q':
- if (reg_type == REG_TYPE_ZN || width == 1)
+ if (reg_type != REG_TYPE_VN || width == 1)
{
type = NT_q;
element_size = 128;
@@ -1004,6 +1004,29 @@ parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
return true;
}
+/* Return true if CH is a valid suffix character for registers of
+ type TYPE. */
+
+static bool
+aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
+{
+ switch (type)
+ {
+ case REG_TYPE_VN:
+ case REG_TYPE_ZN:
+ case REG_TYPE_ZAT:
+ case REG_TYPE_ZATH:
+ case REG_TYPE_ZATV:
+ return ch == '.';
+
+ case REG_TYPE_PN:
+ return ch == '.' || ch == '/';
+
+ default:
+ return false;
+ }
+}
+
/* Parse a register of the type TYPE.
Return null if the string pointed to by *CCP is not a valid register
@@ -1012,9 +1035,13 @@ parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
Otherwise return the register, and optionally return the register
shape and element index information in *TYPEINFO.
- FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list. */
+ FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
+
+ FLAGS includes PTR_FULL_REG if the function should ignore any potential
+ register index. */
#define PTR_IN_REGLIST (1U << 0)
+#define PTR_FULL_REG (1U << 1)
static const reg_entry *
parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1047,8 +1074,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
}
type = reg->type;
- if ((type == REG_TYPE_VN || type == REG_TYPE_ZN || type == REG_TYPE_PN)
- && (*str == '.' || (type == REG_TYPE_PN && *str == '/')))
+ if (aarch64_valid_suffix_char_p (reg->type, *str))
{
if (*str == '.')
{
@@ -1064,7 +1090,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
/* Register if of the form Vn.[bhsdq]. */
is_typed_vecreg = true;
- if (type == REG_TYPE_ZN || type == REG_TYPE_PN)
+ if (type != REG_TYPE_VN)
{
/* The width is always variable; we don't allow an integer width
to be specified. */
@@ -1084,7 +1110,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
atype.width = parsetype.width;
}
- if (skip_past_char (&str, '['))
+ if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
{
expressionS exp;
@@ -4304,45 +4330,17 @@ static const reg_entry *
parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
aarch64_opnd_qualifier_t *qualifier)
{
- char *q;
-
- reg_entry *reg = parse_reg (str);
- if (reg != NULL && aarch64_check_reg_type (reg, reg_type))
- {
- if (!skip_past_char (str, '.'))
- {
- set_syntax_error (_("missing ZA tile element size separator"));
- return NULL;
- }
-
- q = *str;
- switch (TOLOWER (*q))
- {
- case 'b':
- *qualifier = AARCH64_OPND_QLF_S_B;
- break;
- case 'h':
- *qualifier = AARCH64_OPND_QLF_S_H;
- break;
- case 's':
- *qualifier = AARCH64_OPND_QLF_S_S;
- break;
- case 'd':
- *qualifier = AARCH64_OPND_QLF_S_D;
- break;
- case 'q':
- *qualifier = AARCH64_OPND_QLF_S_Q;
- break;
- default:
- return NULL;
- }
- q++;
+ struct vector_type_el vectype;
+ const reg_entry *reg = parse_typed_reg (str, reg_type, &vectype,
+ PTR_FULL_REG);
+ if (!reg)
+ return NULL;
- *str = q;
- return reg;
- }
+ *qualifier = vectype_to_qualifier (&vectype);
+ if (*qualifier == AARCH64_OPND_QLF_NIL)
+ return NULL;
- return NULL;
+ return reg;
}
/* Parse SME ZA tile encoded in <ZAda> assembler symbol.
@@ -4641,19 +4639,17 @@ parse_sme_zero_mask(char **str)
}
continue;
}
- else if (strncasecmp (q, "za", 2) == 0
- && !ISALNUM (q[2]))
+ clear_error ();
+ if (strncasecmp (q, "za", 2) == 0 && !ISALNUM (q[2]))
{
/* { ZA } is assembled as all-ones immediate. */
mask = 0xff;
q += 2;
continue;
}
- else
- {
- set_syntax_error (_("wrong ZA tile element format"));
- return PARSE_FAIL;
- }
+
+ set_syntax_error (_("wrong ZA tile element format"));
+ return PARSE_FAIL;
}
while (skip_past_char (&q, ','));
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 11/43] aarch64: Consolidate ZA tile range checks
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (9 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
` (31 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Now that all parsing of ZA tile names goes through parse_typed_reg,
we can check there for out-of-range tile numbers. The other check
performed by parse_sme_zada_operand was to reject .q, but that can
now be done via F_STRICT instead. (.q tiles are valid in other
contexts, so they shouldn't be rejected in parse_typed_reg.)
---
gas/config/tc-aarch64.c | 106 +++++----------------
gas/testsuite/gas/aarch64/sme-2-illegal.l | 8 +-
gas/testsuite/gas/aarch64/sme-3-illegal.l | 8 +-
gas/testsuite/gas/aarch64/sme-5-illegal.l | 30 +++---
gas/testsuite/gas/aarch64/sme-6-illegal.l | 30 +++---
gas/testsuite/gas/aarch64/sme-illegal.l | 108 +++++++++++++---------
6 files changed, 127 insertions(+), 163 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f9e85b3d803..5fb88f75a62 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -134,6 +134,7 @@ struct vector_type_el
{
enum vector_el_type type;
unsigned char defined;
+ unsigned element_size;
unsigned width;
int64_t index;
};
@@ -966,6 +967,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
parsed_type->type = type;
parsed_type->width = width;
+ parsed_type->element_size = element_size;
*str = ptr;
@@ -1056,6 +1058,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
atype.defined = 0;
atype.type = NT_invtype;
atype.width = -1;
+ atype.element_size = 0;
atype.index = 0;
if (reg == NULL)
@@ -1080,6 +1083,14 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
{
if (!parse_vector_type_for_operand (type, &parsetype, &str))
return NULL;
+ if ((reg->type == REG_TYPE_ZAT
+ || reg->type == REG_TYPE_ZATH
+ || reg->type == REG_TYPE_ZATV)
+ && reg->number * 8 >= parsetype.element_size)
+ {
+ set_syntax_error (_("ZA tile number out of range"));
+ return NULL;
+ }
}
else
{
@@ -1182,10 +1193,11 @@ aarch64_reg_parse (char **ccp, aarch64_reg_type type,
static inline bool
eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
{
- return
- e1.type == e2.type
- && e1.defined == e2.defined
- && e1.width == e2.width && e1.index == e2.index;
+ return (e1.type == e2.type
+ && e1.defined == e2.defined
+ && e1.width == e2.width
+ && e1.element_size == e2.element_size
+ && e1.index == e2.index);
}
/* This function parses a list of vector registers of type TYPE.
@@ -1234,6 +1246,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
typeinfo_first.defined = 0;
typeinfo_first.type = NT_invtype;
typeinfo_first.width = -1;
+ typeinfo_first.element_size = 0;
typeinfo_first.index = 0;
ret_val = 0;
val = -1;
@@ -4343,63 +4356,6 @@ parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
return reg;
}
-/* Parse SME ZA tile encoded in <ZAda> assembler symbol.
- Function return tile QUALIFIER on success.
-
- Tiles are in example format: za[0-9]\.[bhsd]
-
- Function returns <ZAda> register number or PARSE_FAIL.
-*/
-static int
-parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier)
-{
- int regno;
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZAT, qualifier);
-
- if (reg == NULL)
- return PARSE_FAIL;
- regno = reg->number;
-
- switch (*qualifier)
- {
- case AARCH64_OPND_QLF_S_B:
- if (regno != 0x00)
- {
- set_syntax_error (_("invalid ZA tile register number, expected za0"));
- return PARSE_FAIL;
- }
- break;
- case AARCH64_OPND_QLF_S_H:
- if (regno > 0x01)
- {
- set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
- return PARSE_FAIL;
- }
- break;
- case AARCH64_OPND_QLF_S_S:
- if (regno > 0x03)
- {
- /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
- set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
- return PARSE_FAIL;
- }
- break;
- case AARCH64_OPND_QLF_S_D:
- if (regno > 0x07)
- {
- /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
- set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
- return PARSE_FAIL;
- }
- break;
- default:
- set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
- return PARSE_FAIL;
- }
-
- return regno;
-}
-
/* Parse STR for unsigned, immediate (1-2 digits) in format:
#<imm>
@@ -4498,7 +4454,6 @@ parse_sme_za_hv_tiles_operand (char **str,
aarch64_opnd_qualifier_t *qualifier)
{
int regno;
- int regno_limit;
int64_t imm_limit;
int64_t imm_value;
const reg_entry *reg;
@@ -4515,23 +4470,18 @@ parse_sme_za_hv_tiles_operand (char **str,
switch (*qualifier)
{
case AARCH64_OPND_QLF_S_B:
- regno_limit = 0;
imm_limit = 15;
break;
case AARCH64_OPND_QLF_S_H:
- regno_limit = 1;
imm_limit = 7;
break;
case AARCH64_OPND_QLF_S_S:
- regno_limit = 3;
imm_limit = 3;
break;
case AARCH64_OPND_QLF_S_D:
- regno_limit = 7;
imm_limit = 1;
break;
case AARCH64_OPND_QLF_S_Q:
- regno_limit = 15;
imm_limit = 0;
break;
default:
@@ -4539,14 +4489,6 @@ parse_sme_za_hv_tiles_operand (char **str,
return PARSE_FAIL;
}
- /* Check if destination register ZA tile vector is in range for given
- instruction variant. */
- if (regno < 0 || regno > regno_limit)
- {
- set_syntax_error (_("ZA tile vector out of range"));
- return PARSE_FAIL;
- }
-
if (!parse_sme_za_hv_tiles_operand_index (str, vector_select_register,
&imm_value))
return PARSE_FAIL;
@@ -4621,16 +4563,16 @@ parse_sme_zero_mask(char **str)
if (reg)
{
int regno = reg->number;
- if (qualifier == AARCH64_OPND_QLF_S_B && regno == 0)
+ if (qualifier == AARCH64_OPND_QLF_S_B)
{
/* { ZA0.B } is assembled as all-ones immediate. */
mask = 0xff;
}
- else if (qualifier == AARCH64_OPND_QLF_S_H && regno < 2)
+ else if (qualifier == AARCH64_OPND_QLF_S_H)
mask |= 0x55 << regno;
- else if (qualifier == AARCH64_OPND_QLF_S_S && regno < 4)
+ else if (qualifier == AARCH64_OPND_QLF_S_S)
mask |= 0x11 << regno;
- else if (qualifier == AARCH64_OPND_QLF_S_D && regno < 8)
+ else if (qualifier == AARCH64_OPND_QLF_S_D)
mask |= 0x01 << regno;
else
{
@@ -7546,10 +7488,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
- val = parse_sme_zada_operand (&str, &qualifier);
- if (val == PARSE_FAIL)
+ reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier);
+ if (!reg)
goto failure;
- info->reg.regno = val;
+ info->reg.regno = reg->number;
info->qualifier = qualifier;
break;
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index d36456175fe..994c6f15951 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -1,8 +1,8 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.b,p0/m,za1h\.b\[w12,#0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.h,p0/m,za2h\.h\[w12,#0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.b,p0/m,za1h\.b\[w12,#0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.h,p0/m,za2h\.h\[w12,#0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]'
[^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]'
diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l
index 8babf4c7251..6b2791d6267 100644
--- a/gas/testsuite/gas/aarch64/sme-3-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l
@@ -1,8 +1,8 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za1v\.b\[w12,#0\],p0/m,z0.b'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,#0\],p0/m,z0.b'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index c2f8bc92dd8..ec1e989df5b 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -5,32 +5,32 @@
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]'
[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x0,lsl#2\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index 233c12af15a..4fe36135f6e 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -5,32 +5,32 @@
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]'
[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `st1q {za0v.q\[w12\]},p0,\[x0,x0,lsl#2\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]'
-[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-illegal.l b/gas/testsuite/gas/aarch64/sme-illegal.l
index 19d22daad67..efc9b800656 100644
--- a/gas/testsuite/gas/aarch64/sme-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-illegal.l
@@ -1,95 +1,117 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addha za4.s,p0/m,p1/m,z1.s'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addha za15.s,p2/m,p3/m,z2.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za4.s,p0/m,p1/m,z1.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za15.s,p2/m,p3/m,z2.s'
[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.s,p2/m,p3/m,z2.d'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d'
[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.d,p2/m,p3/m,z2.s'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addva za4.s,p0/m,p1/m,z1.s'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addva za15.s,p2/m,p3/m,z2.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addva za4.s,p0/m,p1/m,z1.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addva za15.s,p2/m,p3/m,z2.s'
[^:]*:[0-9]+: Error: operand mismatch -- `addva za0.s,p2/m,p3/m,z2.d'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: addva za0.d, p2/m, p3/m, z2.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addva za8.d,p0/m,p1/m,z1.d'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addva za15.d,p2/m,p3/m,z2.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addva za8.d,p0/m,p1/m,z1.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addva za15.d,p2/m,p3/m,z2.d'
[^:]*:[0-9]+: Error: operand mismatch -- `addva za0.d,p2/m,p3/m,z2.s'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: addva za0.d, p2/m, p3/m, z2.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `bfmopa za4.s,p0/m,p1/m,z1.h,z4.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `bfmopa za4.s,p0/m,p1/m,z1.h,z4.h'
[^:]*:[0-9]+: Error: operand mismatch -- `bfmopa za0.s,p2/m,p3/m,z2.s,z3.s'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: bfmopa za0.s, p2/m, p3/m, z2.h, z3.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `bfmops za4.s,p0/m,p1/m,z1.h,z4.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `bfmops za4.s,p0/m,p1/m,z1.h,z4.h'
[^:]*:[0-9]+: Error: operand mismatch -- `bfmops za0.s,p2/m,p3/m,z2.s,z3.s'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: bfmops za0.s, p2/m, p3/m, z2.h, z3.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.s,z4.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.s,z4.s'
[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.s,p6/m,p7/m,z4.d,z1.d'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: fmopa za0.d, p6/m, p7/m, z4.d, z1.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `fmopa za8.d,p0/m,p1/m,z1.d,z8.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmopa za8.d,p0/m,p1/m,z1.d,z8.d'
[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.d,p2/m,p3/m,z2.s,z7.s'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: fmopa za0.d, p2/m, p3/m, z2.d, z7.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.h,z4.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.h,z4.h'
[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za1.s,p2/m,p3/m,z2.q,z3.q'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: fmopa za1.d, p2/m, p3/m, z2.d, z3.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmops za4.s,p0/m,p1/m,z1.s,z4.s'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmops za4.s,p0/m,p1/m,z1.s,z4.s'
[^:]*:[0-9]+: Error: operand mismatch -- `fmops za1.s,p2/m,p3/m,z2.q,z3.q'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: fmops za1.d, p2/m, p3/m, z2.d, z3.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `fmops za8.d,p0/m,p1/m,z1.d,z8.d'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmops za8.d,p0/m,p1/m,z1.d,z8.d'
[^:]*:[0-9]+: Error: operand mismatch -- `fmops za0.d,p2/m,p3/m,z2.s,z7.s'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: fmops za0.d, p2/m, p3/m, z2.d, z7.d
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmops za8.s,p0/m,p1/m,z1.h,z4.h'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `fmops za1.q,p2/m,p3/m,z2.h,z3.h'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `smopa za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `smopa za1.q,p2/m,p3/m,z2.b,z3.b'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `smopa za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmops za8.s,p0/m,p1/m,z1.h,z4.h'
+[^:]*:[0-9]+: Error: operand mismatch -- `fmops za1.q,p2/m,p3/m,z2.h,z3.h'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: fmops za1.d, p2/m, p3/m, z2.d, z3.d
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smopa za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `smopa za1.q,p2/m,p3/m,z2.b,z3.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: smopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smopa za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `smopa za1.d,p2/m,p3/m,z2.h,z7.q'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: smopa za1.d, p2/m, p3/m, z2.h, z7.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `smops za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `smops za1.q,p2/m,p3/m,z2.b,z3.b'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `smops za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smops za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `smops za1.q,p2/m,p3/m,z2.b,z3.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: smops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `smops za1.d,p2/m,p3/m,z2.h,z7.q'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: smops za1.d, p2/m, p3/m, z2.h, z7.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `sumopa za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumopa za1.q,p2/m,p3/m,z2.s,z3.s'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `sumopa za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `sumopa za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `sumopa za1.q,p2/m,p3/m,z2.s,z3.s'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sumopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `sumopa za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `sumopa za1.d,p2/m,p3/m,z2.h,z7.q'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: sumopa za1.d, p2/m, p3/m, z2.h, z7.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `sumops za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumops za1.q,p2/m,p3/m,z2.b,z3.b'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `sumops za8.d,p0/m,p1/m,z1.h,z8.h'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumops za1.q,p2/m,p3/m,z2.h,z7.h'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `umopa za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umopa za1.q,p2/m,p3/m,z2.b,z3.b'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `umopa za8.d,p0/m,p1/m,z1.h,z8.h'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umopa za1.q,p2/m,p3/m,z2.h,z7.h'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `umops za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umops za1.q,p2/m,p3/m,z2.b,z3.b'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `umops za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `sumops za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `sumops za1.q,p2/m,p3/m,z2.b,z3.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sumops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `sumops za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: operand mismatch -- `sumops za1.q,p2/m,p3/m,z2.h,z7.h'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sumops za1.d, p2/m, p3/m, z2.h, z7.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umopa za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `umopa za1.q,p2/m,p3/m,z2.b,z3.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: umopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umopa za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: operand mismatch -- `umopa za1.q,p2/m,p3/m,z2.h,z7.h'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: umopa za1.d, p2/m, p3/m, z2.h, z7.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umops za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `umops za1.q,p2/m,p3/m,z2.b,z3.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: umops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `umops za1.d,p2/m,p3/m,z2.d,z7.d'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: umops za1.d, p2/m, p3/m, z2.h, z7.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `usmopa za4.s,p0/m,p1/m,z1.b,z4.b'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `usmopa za1.q,p2/m,p3/m,z2.b,z3.b'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `usmopa za8.d,p0/m,p1/m,z1.h,z8.h'
-[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `usmopa za1.q,p2/m,p3/m,z2.h,z7.h'
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `usmops za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmopa za4.s,p0/m,p1/m,z1.b,z4.b'
+[^:]*:[0-9]+: Error: operand mismatch -- `usmopa za1.q,p2/m,p3/m,z2.b,z3.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: usmopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmopa za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: operand mismatch -- `usmopa za1.q,p2/m,p3/m,z2.h,z7.h'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: usmopa za1.d, p2/m, p3/m, z2.h, z7.h
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmops za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.s,p2/m,p3/m,z2.s,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z3.h
-[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `usmops za8.d,p0/m,p1/m,z1.h,z8.h'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.d,p2/m,p3/m,z2.d,z7.d'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z7.h
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 12/43] aarch64: Treat ZA as a register
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (10 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
` (30 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
We already treat the ZA tiles ZA0-ZA15 as registers. This patch
does the same for ZA itself. parse_sme_zero_mask can then parse
ZA tiles and ZA in the same way, through parsed_type_reg.
One important effect of going through parsed_type_reg (in general)
is that it allows ZA to take qualifiers. This is necessary for many
SME2 instructions.
However, to support existing unqualified uses of ZA, parse_reg_with_qual
needs to treat the qualiier as optional. Hopefully the net effect is
to give better error messages, since now that SME2 makes "za.<T>"
valid in some contexts, it might be natural to use it (incorrectly)
in ZERO too.
While there, the patch also tweaks the error messages for invalid
ZA tiles, to try to make some cases more specific.
For now, parse_sme_za_array just uses parse_reg, rather than
parse_typed_reg/parse_reg_with_qual. A later patch consolidates
the parsing further.
---
gas/config/tc-aarch64.c | 73 +++++++++++++++--------
gas/testsuite/gas/aarch64/sme-4-illegal.l | 52 +++++++++-------
gas/testsuite/gas/aarch64/sme-4-illegal.s | 10 ++++
opcodes/aarch64-opc-2.c | 2 +-
opcodes/aarch64-tbl.h | 2 +-
5 files changed, 91 insertions(+), 48 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5fb88f75a62..26588cb4596 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -284,6 +284,7 @@ struct reloc_entry
BASIC_REG_TYPE(VN) /* v[0-31] */ \
BASIC_REG_TYPE(ZN) /* z[0-31] */ \
BASIC_REG_TYPE(PN) /* p[0-15] */ \
+ BASIC_REG_TYPE(ZA) /* za */ \
BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
@@ -327,6 +328,8 @@ struct reloc_entry
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
| REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ /* The whole of ZA or a single tile. */ \
+ MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
/* A horizontal or vertical slice of a ZA tile. */ \
MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
/* Pseudo type to mark the end of the enumerator sequence. */ \
@@ -1016,6 +1019,7 @@ aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
{
case REG_TYPE_VN:
case REG_TYPE_ZN:
+ case REG_TYPE_ZA:
case REG_TYPE_ZAT:
case REG_TYPE_ZATH:
case REG_TYPE_ZATV:
@@ -4349,9 +4353,14 @@ parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
if (!reg)
return NULL;
- *qualifier = vectype_to_qualifier (&vectype);
- if (*qualifier == AARCH64_OPND_QLF_NIL)
- return NULL;
+ if (vectype.type == NT_invtype)
+ *qualifier = AARCH64_OPND_QLF_NIL;
+ else
+ {
+ *qualifier = vectype_to_qualifier (&vectype);
+ if (*qualifier == AARCH64_OPND_QLF_NIL)
+ return NULL;
+ }
return reg;
}
@@ -4558,10 +4567,23 @@ parse_sme_zero_mask(char **str)
q = *str;
do
{
- const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZAT,
+ const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT,
&qualifier);
- if (reg)
- {
+ if (!reg)
+ return PARSE_FAIL;
+
+ if (reg->type == REG_TYPE_ZA)
+ {
+ if (qualifier != AARCH64_OPND_QLF_NIL)
+ {
+ set_syntax_error ("ZA should not have a size suffix");
+ return PARSE_FAIL;
+ }
+ /* { ZA } is assembled as all-ones immediate. */
+ mask = 0xff;
+ }
+ else
+ {
int regno = reg->number;
if (qualifier == AARCH64_OPND_QLF_S_B)
{
@@ -4574,24 +4596,23 @@ parse_sme_zero_mask(char **str)
mask |= 0x11 << regno;
else if (qualifier == AARCH64_OPND_QLF_S_D)
mask |= 0x01 << regno;
+ else if (qualifier == AARCH64_OPND_QLF_S_Q)
+ {
+ set_syntax_error (_("ZA tile masks do not operate at .Q"
+ " granularity"));
+ return PARSE_FAIL;
+ }
+ else if (qualifier == AARCH64_OPND_QLF_NIL)
+ {
+ set_syntax_error (_("missing ZA tile size"));
+ return PARSE_FAIL;
+ }
else
{
- set_syntax_error (_("wrong ZA tile element format"));
+ set_syntax_error (_("invalid ZA tile"));
return PARSE_FAIL;
}
- continue;
- }
- clear_error ();
- if (strncasecmp (q, "za", 2) == 0 && !ISALNUM (q[2]))
- {
- /* { ZA } is assembled as all-ones immediate. */
- mask = 0xff;
- q += 2;
- continue;
}
-
- set_syntax_error (_("wrong ZA tile element format"));
- return PARSE_FAIL;
}
while (skip_past_char (&q, ','));
@@ -4646,15 +4667,13 @@ parse_sme_list_of_64bit_tiles (char **str)
static int
parse_sme_za_array (char **str, int *imm)
{
- char *p, *q;
+ char *q;
int regno;
int64_t imm_value;
- p = q = *str;
- while (ISALPHA (*q))
- q++;
-
- if ((q - p != 2) || strncasecmp ("za", p, q - p) != 0)
+ q = *str;
+ const reg_entry *reg = parse_reg (&q);
+ if (!reg || reg->type != REG_TYPE_ZA)
{
set_syntax_error (_("expected ZA array"));
return PARSE_FAIL;
@@ -8181,6 +8200,10 @@ static const reg_entry reg_names[] = {
/* SVE predicate registers. */
REGSET16 (p, PN), REGSET16 (P, PN),
+ /* SME ZA. We model this as a register because it acts syntactically
+ like ZA0H, supporting qualifier suffixes and indexing. */
+ REGDEF (za, 0, ZA), REGDEF (ZA, 0, ZA),
+
/* SME ZA tile registers. */
REGSET16 (za, ZAT), REGSET16 (ZA, ZAT),
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index ae7d6543410..b61832e4223 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -1,29 +1,39 @@
[^:]*: Assembler messages:
[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za8\.d}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0\.d,za8.d}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za2\.h}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za4\.s}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za1\.s,za4.s}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0\.d,za3.s,za2.h}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za1.b}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za8\.d}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za8.d}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za2\.h}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za4\.s}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za1\.s,za4.s}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za3.s,za2.h}'
+[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za1.b}'
[^:]*:[0-9]+: Error: unexpected comma after the mnemonic name `zero' -- `zero ,'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,'
[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero }'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,,}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,za0.d}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0.d,}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0.d,za1.d,}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za,}'
-[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za.}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,,}'
+[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,za0.d}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za1.d,}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za,}'
+[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
-[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za_}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za_}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {zaX}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {zax}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zaX}'
+[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zax}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
+[^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}'
+[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.b}'
+[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.h}'
+[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.s}'
+[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.d}'
+[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.q}'
+[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za.2d}'
+[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za0.2d}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0h\.b}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0v\.b}'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.s b/gas/testsuite/gas/aarch64/sme-4-illegal.s
index db0fbf6c7c0..3d81942f724 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.s
@@ -30,3 +30,13 @@ zero { za0 }
zero { zax }
zero { za{ }
zero { za} }
+zero { za0.q }
+zero { za.b }
+zero { za.h }
+zero { za.s }
+zero { za.d }
+zero { za.q }
+zero { za.2d }
+zero { za0.2d }
+zero { za0h.b }
+zero { za0v.b }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 4da9fd608b9..6e22690b994 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -239,7 +239,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "list of 64-bit ZA element tiles"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"},
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6c2862eacf3..ff0b04af794 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5921,7 +5921,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
- F(FLD_SME_zero_mask), "list of 64-bit ZA element tiles") \
+ F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \
"an SME horizontal or vertical vector access register") \
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 13/43] aarch64: Rename za_tile_vector to za_index
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (11 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
` (29 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
za_tile_vector is also used for indexing ZA as a whole, rather than
just for indexing tiles. The former is more common than the latter
in SME2, so this patch generalises the name to "indexed_za".
The patch also names the associated structure, so that later patches
can reuse it during parsing.
---
gas/config/tc-aarch64.c | 18 +++++++++---------
include/opcode/aarch64.h | 23 +++++++++++++----------
opcodes/aarch64-asm.c | 18 +++++++++---------
opcodes/aarch64-dis.c | 34 +++++++++++++++++-----------------
opcodes/aarch64-opc.c | 20 ++++++++++----------
5 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 26588cb4596..b06a9379f2e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7185,9 +7185,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (val == PARSE_FAIL)
goto failure;
- info->za_tile_vector.regno = val;
- info->za_tile_vector.index.regno = index_base_reg;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.regno = val;
+ info->indexed_za.index.regno = index_base_reg;
+ info->indexed_za.index.imm = imm;
info->qualifier = qualifier;
break;
}
@@ -7535,10 +7535,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
&qualifier);
if (val == PARSE_FAIL)
goto failure;
- info->za_tile_vector.regno = val;
- info->za_tile_vector.index.regno = vector_select_register;
- info->za_tile_vector.index.imm = imm;
- info->za_tile_vector.v = slice_indicator;
+ info->indexed_za.regno = val;
+ info->indexed_za.index.regno = vector_select_register;
+ info->indexed_za.index.imm = imm;
+ info->indexed_za.v = slice_indicator;
info->qualifier = qualifier;
break;
}
@@ -7556,8 +7556,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
val = parse_sme_za_array (&str, &imm);
if (val == PARSE_FAIL)
goto failure;
- info->za_tile_vector.index.regno = val;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.index.regno = val;
+ info->indexed_za.index.imm = imm;
break;
}
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 691247aa934..4a554df2b36 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1108,6 +1108,18 @@ extern const aarch64_cond aarch64_conds[16];
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
\f
+/* Information about a reference to part of ZA. */
+struct aarch64_indexed_za
+{
+ int regno; /* <ZAn> */
+ struct
+ {
+ int regno; /* <Wv> */
+ int imm; /* <imm> */
+ } index;
+ unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
+};
+
/* Structure representing an operand. */
struct aarch64_opnd_info
@@ -1172,16 +1184,7 @@ struct aarch64_opnd_info
} sysreg;
/* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */
- struct
- {
- int regno; /* <ZAn> */
- struct
- {
- int regno; /* <Wv> */
- int imm; /* <imm> */
- } index;
- unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
- } za_tile_vector;
+ struct aarch64_indexed_za indexed_za;
const aarch64_cond *cond;
/* The encoding of the PSTATE field. */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index bfabcb9e3a2..73ee15a0257 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1340,10 +1340,10 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self,
{
int fld_size;
int fld_q;
- int fld_v = info->za_tile_vector.v;
- int fld_rv = info->za_tile_vector.index.regno - 12;
- int fld_zan_imm = info->za_tile_vector.index.imm;
- int regno = info->za_tile_vector.regno;
+ int fld_v = info->indexed_za.v;
+ int fld_rv = info->indexed_za.index.regno - 12;
+ int fld_zan_imm = info->indexed_za.index.imm;
+ int regno = info->indexed_za.regno;
switch (info->qualifier)
{
@@ -1410,8 +1410,8 @@ aarch64_ins_sme_za_array (const aarch64_operand *self,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- int regno = info->za_tile_vector.index.regno - 12;
- int imm = info->za_tile_vector.index.imm;
+ int regno = info->indexed_za.index.regno - 12;
+ int imm = info->indexed_za.index.imm;
insert_field (self->fields[0], code, regno, 0);
insert_field (self->fields[1], code, imm, 0);
return true;
@@ -1464,9 +1464,9 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- int fld_pn = info->za_tile_vector.regno;
- int fld_rm = info->za_tile_vector.index.regno - 12;
- int imm = info->za_tile_vector.index.imm;
+ int fld_pn = info->indexed_za.regno;
+ int fld_rm = info->indexed_za.index.regno - 12;
+ int imm = info->indexed_za.index.imm;
int fld_i1, fld_tszh, fld_tshl;
insert_field (self->fields[0], code, fld_rm, 0);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 01881ea377d..eabcc9ee586 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1786,34 +1786,34 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
/* Deduce qualifier encoded in size and Q fields. */
if (fld_size == 0)
{
- info->za_tile_vector.regno = 0;
- info->za_tile_vector.index.imm = fld_zan_imm;
+ info->indexed_za.regno = 0;
+ info->indexed_za.index.imm = fld_zan_imm;
}
else if (fld_size == 1)
{
- info->za_tile_vector.regno = fld_zan_imm >> 3;
- info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
+ info->indexed_za.regno = fld_zan_imm >> 3;
+ info->indexed_za.index.imm = fld_zan_imm & 0x07;
}
else if (fld_size == 2)
{
- info->za_tile_vector.regno = fld_zan_imm >> 2;
- info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
+ info->indexed_za.regno = fld_zan_imm >> 2;
+ info->indexed_za.index.imm = fld_zan_imm & 0x03;
}
else if (fld_size == 3 && fld_q == 0)
{
- info->za_tile_vector.regno = fld_zan_imm >> 1;
- info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
+ info->indexed_za.regno = fld_zan_imm >> 1;
+ info->indexed_za.index.imm = fld_zan_imm & 0x01;
}
else if (fld_size == 3 && fld_q == 1)
{
- info->za_tile_vector.regno = fld_zan_imm;
- info->za_tile_vector.index.imm = 0;
+ info->indexed_za.regno = fld_zan_imm;
+ info->indexed_za.index.imm = 0;
}
else
return false;
- info->za_tile_vector.index.regno = fld_rv + 12;
- info->za_tile_vector.v = fld_v;
+ info->indexed_za.index.regno = fld_rv + 12;
+ info->indexed_za.v = fld_v;
return true;
}
@@ -1847,8 +1847,8 @@ aarch64_ext_sme_za_array (const aarch64_operand *self,
{
int regno = extract_field (self->fields[0], code, 0) + 12;
int imm = extract_field (self->fields[1], code, 0);
- info->za_tile_vector.index.regno = regno;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.index.regno = regno;
+ info->indexed_za.index.imm = imm;
return true;
}
@@ -1902,8 +1902,8 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0);
int imm;
- info->za_tile_vector.regno = fld_pn;
- info->za_tile_vector.index.regno = fld_rm + 12;
+ info->indexed_za.regno = fld_pn;
+ info->indexed_za.index.regno = fld_rm + 12;
if (fld_tszl & 0x1)
imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
@@ -1916,7 +1916,7 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
else
return false;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.index.imm = imm;
return true;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a0e6240592c..bbbac418f91 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2770,7 +2770,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
case sme_str:
assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array);
assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL);
- if (inst->operands[0].za_tile_vector.index.imm
+ if (inst->operands[0].indexed_za.index.imm
!= inst->operands[1].addr.offset.imm)
{
if (mismatch_detail)
@@ -3556,11 +3556,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s%s[%s, %s]%s",
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
style_reg (styler, "za%d%c.%s",
- opnd->za_tile_vector.regno,
- opnd->za_tile_vector.v == 1 ? 'v' : 'h',
+ opnd->indexed_za.regno,
+ opnd->indexed_za.v == 1 ? 'v' : 'h',
aarch64_get_qualifier_name (opnd->qualifier)),
- style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
- style_imm (styler, "%d", opnd->za_tile_vector.index.imm),
+ style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+ style_imm (styler, "%d", opnd->indexed_za.index.imm),
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
break;
@@ -3571,8 +3571,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_ZA_array:
snprintf (buf, size, "%s[%s, %s]",
style_reg (styler, "za"),
- style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
- style_imm (styler, "%d", opnd->za_tile_vector.index.imm));
+ style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+ style_imm (styler, "%d", opnd->indexed_za.index.imm));
break;
case AARCH64_OPND_SME_SM_ZA:
@@ -3582,10 +3582,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_PnT_Wm_imm:
snprintf (buf, size, "%s[%s, %s]",
- style_reg (styler, "p%d.%s", opnd->za_tile_vector.regno,
+ style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
aarch64_get_qualifier_name (opnd->qualifier)),
- style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
- style_imm (styler, "%d", opnd->za_tile_vector.index.imm));
+ style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+ style_imm (styler, "%d", opnd->indexed_za.index.imm));
break;
case AARCH64_OPND_CRn:
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (12 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
` (28 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
A later patch moves the range checking for ZA vector select
offsets from gas to libopcodes. That in turn requires the
immediate field to be big enough to support all parsed values.
This shouldn't be a particularly size-sensitive structure,
so there should be no memory problems with doing this.
---
include/opcode/aarch64.h | 2 +-
opcodes/aarch64-opc.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4a554df2b36..aeb3d9a9721 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1115,7 +1115,7 @@ struct aarch64_indexed_za
struct
{
int regno; /* <Wv> */
- int imm; /* <imm> */
+ int64_t imm; /* <imm> */
} index;
unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
};
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index bbbac418f91..c92b4e80e35 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3560,7 +3560,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
opnd->indexed_za.v == 1 ? 'v' : 'h',
aarch64_get_qualifier_name (opnd->qualifier)),
style_reg (styler, "w%d", opnd->indexed_za.index.regno),
- style_imm (styler, "%d", opnd->indexed_za.index.imm),
+ style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
break;
@@ -3572,7 +3572,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s[%s, %s]",
style_reg (styler, "za"),
style_reg (styler, "w%d", opnd->indexed_za.index.regno),
- style_imm (styler, "%d", opnd->indexed_za.index.imm));
+ style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
break;
case AARCH64_OPND_SME_SM_ZA:
@@ -3585,7 +3585,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
aarch64_get_qualifier_name (opnd->qualifier)),
style_reg (styler, "w%d", opnd->indexed_za.index.regno),
- style_imm (styler, "%d", opnd->indexed_za.index.imm));
+ style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
break;
case AARCH64_OPND_CRn:
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (13 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
` (27 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
ZA indices have more parts than most operands, so passing these
parts around individually is more awkward than for other operand
types. Things aren't too bad at the moment, but SME2 adds two
further pieces: an offset range and a vector group size.
This patch therefore replaces arguments for the individual pieces
with a single argument for the index as a whole.
---
gas/config/tc-aarch64.c | 230 ++++++++++++++--------------------------
1 file changed, 78 insertions(+), 152 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b06a9379f2e..0db2ba080d1 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -114,17 +114,6 @@ enum vector_el_type
NT_merge
};
-/* SME horizontal or vertical slice indicator, encoded in "V".
- Values:
- 0 - Horizontal
- 1 - vertical
-*/
-enum sme_hv_slice
-{
- HV_horizontal = 0,
- HV_vertical = 1
-};
-
/* Bits for DEFINED field in vector_type_el. */
#define NTA_HASTYPE 1
#define NTA_HASINDEX 2
@@ -4389,16 +4378,10 @@ parse_sme_immediate (char **str, int64_t *imm)
[<Wv>, #<imm>]
where <Wv> is in W12-W15 range and # is optional for immediate.
- Function performs extra check for mandatory immediate value if REQUIRE_IMM
- is set to true.
+ Return true on success, populating OPND with the parsed index. */
- On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
- IMM output.
-*/
static bool
-parse_sme_za_hv_tiles_operand_index (char **str,
- int *vector_select_register,
- int64_t *imm)
+parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
{
const reg_entry *reg;
@@ -4416,7 +4399,7 @@ parse_sme_za_hv_tiles_operand_index (char **str,
set_syntax_error (_("expected vector select register W12-W15"));
return false;
}
- *vector_select_register = reg->number;
+ opnd->index.regno = reg->number;
if (!skip_past_char (str, ',')) /* Optional index offset immediate. */
{
@@ -4424,7 +4407,7 @@ parse_sme_za_hv_tiles_operand_index (char **str,
return false;
}
- if (!parse_sme_immediate (str, imm))
+ if (!parse_sme_immediate (str, &opnd->index.imm))
{
set_syntax_error (_("index offset immediate expected"));
return false;
@@ -4440,10 +4423,9 @@ parse_sme_za_hv_tiles_operand_index (char **str,
}
/* Parse SME ZA horizontal or vertical vector access to tiles.
- Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
- vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
- contains <Wv> select register and corresponding optional IMMEDIATE.
- In addition QUALIFIER is extracted.
+ Return true on success, populating OPND with information about
+ the indexed tile and QUALIFIER with the qualifier that was applied
+ to the tile name.
Field format examples:
@@ -4452,29 +4434,21 @@ parse_sme_za_hv_tiles_operand_index (char **str,
<ZAn><HV>.S[<Wv>, #<imm>]
<ZAn><HV>.D[<Wv>, #<imm>]
<ZAn><HV>.Q[<Wv>, #<imm>]
-
- Function returns <ZAda> register number or PARSE_FAIL.
*/
-static int
+static bool
parse_sme_za_hv_tiles_operand (char **str,
- enum sme_hv_slice *slice_indicator,
- int *vector_select_register,
- int *imm,
- aarch64_opnd_qualifier_t *qualifier)
+ struct aarch64_indexed_za *opnd,
+ aarch64_opnd_qualifier_t *qualifier)
{
- int regno;
int64_t imm_limit;
- int64_t imm_value;
const reg_entry *reg;
reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
if (!reg)
- return PARSE_FAIL;
+ return false;
- *slice_indicator = (aarch64_check_reg_type (reg, REG_TYPE_ZATH)
- ? HV_horizontal
- : HV_vertical);
- regno = reg->number;
+ opnd->v = aarch64_check_reg_type (reg, REG_TYPE_ZATV);
+ opnd->regno = reg->number;
switch (*qualifier)
{
@@ -4495,56 +4469,47 @@ parse_sme_za_hv_tiles_operand (char **str,
break;
default:
set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
- return PARSE_FAIL;
+ return false;
}
- if (!parse_sme_za_hv_tiles_operand_index (str, vector_select_register,
- &imm_value))
- return PARSE_FAIL;
+ if (!parse_sme_za_index (str, opnd))
+ return false;
/* Check if optional index offset is in the range for instruction
variant. */
- if (imm_value < 0 || imm_value > imm_limit)
+ if (opnd->index.imm < 0 || opnd->index.imm > imm_limit)
{
set_syntax_error (_("index offset out of range"));
- return PARSE_FAIL;
+ return false;
}
- *imm = imm_value;
-
- return regno;
+ return true;
}
+/* Like parse_sme_za_hv_tiles_operand, but expect braces around the
+ operand. */
-static int
+static bool
parse_sme_za_hv_tiles_operand_with_braces (char **str,
- enum sme_hv_slice *slice_indicator,
- int *vector_select_register,
- int *imm,
+ struct aarch64_indexed_za *opnd,
aarch64_opnd_qualifier_t *qualifier)
{
- int regno;
-
if (!skip_past_char (str, '{'))
{
set_syntax_error (_("expected '{'"));
- return PARSE_FAIL;
+ return false;
}
- regno = parse_sme_za_hv_tiles_operand (str, slice_indicator,
- vector_select_register, imm,
- qualifier);
-
- if (regno == PARSE_FAIL)
- return PARSE_FAIL;
+ if (!parse_sme_za_hv_tiles_operand (str, opnd, qualifier))
+ return false;
if (!skip_past_char (str, '}'))
{
set_syntax_error (_("expected '}'"));
- return PARSE_FAIL;
+ return false;
}
- return regno;
+ return true;
}
/* Parse list of up to eight 64-bit element tile names separated by commas in
@@ -4662,35 +4627,34 @@ parse_sme_list_of_64bit_tiles (char **str)
ZA[<Wv>, <imm>]
ZA[<Wv>, #<imm>]
- Function returns <Wv> or PARSE_FAIL.
-*/
-static int
-parse_sme_za_array (char **str, int *imm)
+ Return true on success, populating OPND with information about
+ the operand. */
+
+static bool
+parse_sme_za_array (char **str, struct aarch64_indexed_za *opnd)
{
char *q;
- int regno;
- int64_t imm_value;
q = *str;
const reg_entry *reg = parse_reg (&q);
if (!reg || reg->type != REG_TYPE_ZA)
{
set_syntax_error (_("expected ZA array"));
- return PARSE_FAIL;
+ return false;
}
+ opnd->regno = -1;
- if (! parse_sme_za_hv_tiles_operand_index (&q, ®no, &imm_value))
- return PARSE_FAIL;
+ if (! parse_sme_za_index (&q, opnd))
+ return false;
- if (imm_value < 0 || imm_value > 15)
+ if (opnd->index.imm < 0 || opnd->index.imm > 15)
{
set_syntax_error (_("offset out of range"));
- return PARSE_FAIL;
+ return false;
}
- *imm = imm_value;
*str = q;
- return regno;
+ return true;
}
/* Parse streaming mode operand for SMSTART and SMSTOP.
@@ -4726,23 +4690,19 @@ parse_sme_sm_za (char **str)
<Pn>.<T>[<Wv>, <imm>]
<Pn>.<T>[<Wv>, #<imm>]
- On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
- <imm> to IMM.
- Function returns <Pn>, or PARSE_FAIL.
-*/
-static int
-parse_sme_pred_reg_with_index(char **str,
- int *index_base_reg,
- int *imm,
- aarch64_opnd_qualifier_t *qualifier)
+ Return true on success, populating OPND with information about the index
+ and setting QUALIFIER to <T>. */
+
+static bool
+parse_sme_pred_reg_with_index (char **str, struct aarch64_indexed_za *opnd,
+ aarch64_opnd_qualifier_t *qualifier)
{
int regno;
int64_t imm_limit;
- int64_t imm_value;
const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
if (reg == NULL)
- return PARSE_FAIL;
+ return false;
regno = reg->number;
switch (*qualifier)
@@ -4761,21 +4721,20 @@ parse_sme_pred_reg_with_index(char **str,
break;
default:
set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
- return PARSE_FAIL;
+ return false;
}
+ opnd->regno = regno;
- if (! parse_sme_za_hv_tiles_operand_index (str, index_base_reg, &imm_value))
- return PARSE_FAIL;
+ if (! parse_sme_za_index (str, opnd))
+ return false;
- if (imm_value < 0 || imm_value > imm_limit)
+ if (opnd->index.imm < 0 || opnd->index.imm > imm_limit)
{
set_syntax_error (_("element index out of range for given variant"));
- return PARSE_FAIL;
+ return false;
}
- *imm = imm_value;
-
- return regno;
+ return true;
}
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
@@ -7175,22 +7134,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_PnT_Wm_imm:
/* <Pn>.<T>[<Wm>, #<imm>] */
- {
- int index_base_reg;
- int imm;
- val = parse_sme_pred_reg_with_index (&str,
- &index_base_reg,
- &imm,
- &qualifier);
- if (val == PARSE_FAIL)
- goto failure;
-
- info->indexed_za.regno = val;
- info->indexed_za.index.regno = index_base_reg;
- info->indexed_za.index.imm = imm;
- info->qualifier = qualifier;
- break;
- }
+ if (!parse_sme_pred_reg_with_index (&str, &info->indexed_za,
+ &qualifier))
+ goto failure;
+ info->qualifier = qualifier;
+ break;
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
@@ -7517,49 +7465,27 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZA_HV_idx_src:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
- {
- enum sme_hv_slice slice_indicator;
- int vector_select_register;
- int imm;
-
- if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr)
- val = parse_sme_za_hv_tiles_operand_with_braces (&str,
- &slice_indicator,
- &vector_select_register,
- &imm,
- &qualifier);
- else
- val = parse_sme_za_hv_tiles_operand (&str, &slice_indicator,
- &vector_select_register,
- &imm,
- &qualifier);
- if (val == PARSE_FAIL)
- goto failure;
- info->indexed_za.regno = val;
- info->indexed_za.index.regno = vector_select_register;
- info->indexed_za.index.imm = imm;
- info->indexed_za.v = slice_indicator;
- info->qualifier = qualifier;
- break;
- }
+ if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
+ ? !parse_sme_za_hv_tiles_operand_with_braces (&str,
+ &info->indexed_za,
+ &qualifier)
+ : !parse_sme_za_hv_tiles_operand (&str, &info->indexed_za,
+ &qualifier))
+ goto failure;
+ info->qualifier = qualifier;
+ break;
- case AARCH64_OPND_SME_list_of_64bit_tiles:
- val = parse_sme_list_of_64bit_tiles (&str);
- if (val == PARSE_FAIL)
- goto failure;
- info->imm.value = val;
- break;
+ case AARCH64_OPND_SME_list_of_64bit_tiles:
+ val = parse_sme_list_of_64bit_tiles (&str);
+ if (val == PARSE_FAIL)
+ goto failure;
+ info->imm.value = val;
+ break;
- case AARCH64_OPND_SME_ZA_array:
- {
- int imm;
- val = parse_sme_za_array (&str, &imm);
- if (val == PARSE_FAIL)
- goto failure;
- info->indexed_za.index.regno = val;
- info->indexed_za.index.imm = imm;
- break;
- }
+ case AARCH64_OPND_SME_ZA_array:
+ if (!parse_sme_za_array (&str, &info->indexed_za))
+ goto failure;
+ break;
case AARCH64_OPND_MOPS_ADDR_Rd:
case AARCH64_OPND_MOPS_ADDR_Rs:
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (14 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
` (26 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch moves the range checks on ZA vector select offsets from
gas to libopcodes. Doing the checks there means that the error
messages contain the expected range. It also fits in better
with the error severity scheme, which becomes important later.
(This is because out-of-range indices are treated as more severe than
syntax errors, on the basis that parsing must have succeeded if we get
to the point of checking the completed opcode.)
The patch also adds a new check_za_access function for checking
ZA accesses. That's a bit over the top for one offset check, but the
function becomes more complex with later patches.
sme-9-illegal.s checked for an invalid .q suffix using:
psel p1, p15, p3.q[w15]
but this is doubly invalid because it misses the immediate part
of the index. The patch keeps that test but adds another with
a zero index, so that .q is the only thing wrong.
The aarch64-tbl.h change includes neatening up the backslash
positions.
---
gas/config/tc-aarch64.c | 81 ++---------------------
gas/testsuite/gas/aarch64/sme-2-illegal.l | 10 +--
gas/testsuite/gas/aarch64/sme-3-illegal.l | 10 +--
gas/testsuite/gas/aarch64/sme-5-illegal.l | 38 +++++------
gas/testsuite/gas/aarch64/sme-6-illegal.l | 38 +++++------
gas/testsuite/gas/aarch64/sme-7-illegal.l | 20 +++---
gas/testsuite/gas/aarch64/sme-9-illegal.l | 18 +++--
gas/testsuite/gas/aarch64/sme-9-illegal.s | 2 +
include/opcode/aarch64.h | 1 +
opcodes/aarch64-opc-2.c | 8 +--
opcodes/aarch64-opc.c | 45 +++++++++++++
opcodes/aarch64-tbl.h | 39 +++++------
12 files changed, 145 insertions(+), 165 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0db2ba080d1..ba7f543e033 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4440,50 +4440,14 @@ parse_sme_za_hv_tiles_operand (char **str,
struct aarch64_indexed_za *opnd,
aarch64_opnd_qualifier_t *qualifier)
{
- int64_t imm_limit;
- const reg_entry *reg;
-
- reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
if (!reg)
return false;
opnd->v = aarch64_check_reg_type (reg, REG_TYPE_ZATV);
opnd->regno = reg->number;
- switch (*qualifier)
- {
- case AARCH64_OPND_QLF_S_B:
- imm_limit = 15;
- break;
- case AARCH64_OPND_QLF_S_H:
- imm_limit = 7;
- break;
- case AARCH64_OPND_QLF_S_S:
- imm_limit = 3;
- break;
- case AARCH64_OPND_QLF_S_D:
- imm_limit = 1;
- break;
- case AARCH64_OPND_QLF_S_Q:
- imm_limit = 0;
- break;
- default:
- set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
- return false;
- }
-
- if (!parse_sme_za_index (str, opnd))
- return false;
-
- /* Check if optional index offset is in the range for instruction
- variant. */
- if (opnd->index.imm < 0 || opnd->index.imm > imm_limit)
- {
- set_syntax_error (_("index offset out of range"));
- return false;
- }
-
- return true;
+ return parse_sme_za_index (str, opnd);
}
/* Like parse_sme_za_hv_tiles_operand, but expect braces around the
@@ -4644,17 +4608,8 @@ parse_sme_za_array (char **str, struct aarch64_indexed_za *opnd)
}
opnd->regno = -1;
- if (! parse_sme_za_index (&q, opnd))
- return false;
-
- if (opnd->index.imm < 0 || opnd->index.imm > 15)
- {
- set_syntax_error (_("offset out of range"));
- return false;
- }
-
*str = q;
- return true;
+ return parse_sme_za_index (str, opnd);
}
/* Parse streaming mode operand for SMSTART and SMSTOP.
@@ -4697,43 +4652,15 @@ static bool
parse_sme_pred_reg_with_index (char **str, struct aarch64_indexed_za *opnd,
aarch64_opnd_qualifier_t *qualifier)
{
- int regno;
- int64_t imm_limit;
const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
-
if (reg == NULL)
return false;
- regno = reg->number;
- switch (*qualifier)
- {
- case AARCH64_OPND_QLF_S_B:
- imm_limit = 15;
- break;
- case AARCH64_OPND_QLF_S_H:
- imm_limit = 7;
- break;
- case AARCH64_OPND_QLF_S_S:
- imm_limit = 3;
- break;
- case AARCH64_OPND_QLF_S_D:
- imm_limit = 1;
- break;
- default:
- set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
- return false;
- }
- opnd->regno = regno;
+ opnd->regno = reg->number;
if (! parse_sme_za_index (str, opnd))
return false;
- if (opnd->index.imm < 0 || opnd->index.imm > imm_limit)
- {
- set_syntax_error (_("element index out of range for given variant"));
- return false;
- }
-
return true;
}
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index 994c6f15951..eaf1b975a81 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -4,11 +4,11 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]'
[^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.d,p7/m,za7v\.d\[w15,#2\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 3 -- `mova z31\.d,p7/m,za7v\.d\[w15,#2\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]'
[^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l
index 6b2791d6267..cb8fe4ef47a 100644
--- a/gas/testsuite/gas/aarch64/sme-3-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l
@@ -4,8 +4,8 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za7v\.d\[w15,#2\],p7/m,z31.d'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za15v\.q\[w15,#1\],p7/m,z31.q'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `mova za7v\.d\[w15,#2\],p7/m,z31.d'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za15v\.q\[w15,#1\],p7/m,z31.q'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index ec1e989df5b..d706a169f3a 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -8,41 +8,41 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {za0h.b\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0h.h\[w12,0\]},p0/z,\[x0,x1,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {za3v.s\[w12,3\]},p7/z,\[x0,x1,lsl#3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index 4fe36135f6e..d2a3f3ca09e 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -8,38 +8,38 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
-[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index 913bd0ee8d1..242c5ec75d3 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -3,8 +3,8 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]'
@@ -14,8 +14,8 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]'
@@ -23,11 +23,11 @@
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w15,15\],\[sp,#15,mul#4\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,13\],\[x17,#23,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,13\],\[x17,#23,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]'
-[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
index 6bab29fd36b..4d4520c55bd 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -1,13 +1,21 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: wrong predicate register element size, allowed b, h, s and d at operand 3 -- `psel p1,p15,p3.q\[w15\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w12\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.q\[w15\]'
+[^:]*:[0-9]+: Error: operand mismatch -- `psel p1,p15,p3.q\[w15,#0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: psel p1, p15, p3.b\[w15, 0\]
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
+[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
+[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]'
-[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
-[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
-[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
-[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
+[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]'
[^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: revd z0.q, p0/m, z0.q
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s
index 308d52cebe2..88d25fca10b 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s
@@ -1,6 +1,8 @@
/* Scalable Matrix Extension (SME). */
+psel p1, p15, p3.b[w12]
psel p1, p15, p3.q[w15]
+psel p1, p15, p3.q[w15, #0]
psel p1, p15, p3.b[w11]
psel p8, p11, p15.h[w16]
psel p2, p7, p15.s[w3]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index aeb3d9a9721..cc0ddf08989 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -225,6 +225,7 @@ enum aarch64_operand_class
AARCH64_OPND_CLASS_SIMD_REGLIST,
AARCH64_OPND_CLASS_SVE_REG,
AARCH64_OPND_CLASS_PRED_REG,
+ AARCH64_OPND_CLASS_ZA_ACCESS,
AARCH64_OPND_CLASS_ADDRESS,
AARCH64_OPND_CLASS_IMMEDIATE,
AARCH64_OPND_CLASS_SYSTEM,
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 6e22690b994..3603f2c8c9b 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -236,12 +236,12 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index c92b4e80e35..746edde7516 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1438,6 +1438,22 @@ set_other_error (aarch64_operand_error *mismatch_detail, int idx,
set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
}
+/* Check that indexed ZA operand OPND has a vector select offset
+ in the range [0, MAX_VALUE]. */
+
+static bool
+check_za_access (const aarch64_opnd_info *opnd,
+ aarch64_operand_error *mismatch_detail, int idx,
+ int max_value)
+{
+ if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_value))
+ {
+ set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value);
+ return false;
+ }
+ return true;
+}
+
/* General constraint checking based on operand code.
Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
@@ -1574,11 +1590,40 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_SME_PnT_Wm_imm:
+ size = aarch64_get_qualifier_esize (opnd->qualifier);
+ max_value = 16 / size - 1;
+ if (!check_za_access (opnd, mismatch_detail, idx, max_value))
+ return 0;
+ break;
+
default:
break;
}
break;
+ case AARCH64_OPND_CLASS_ZA_ACCESS:
+ switch (type)
+ {
+ case AARCH64_OPND_SME_ZA_HV_idx_src:
+ case AARCH64_OPND_SME_ZA_HV_idx_dest:
+ case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
+ size = aarch64_get_qualifier_esize (opnd->qualifier);
+ max_value = 16 / size - 1;
+ if (!check_za_access (opnd, mismatch_detail, idx, max_value))
+ return 0;
+ break;
+
+ case AARCH64_OPND_SME_ZA_array:
+ if (!check_za_access (opnd, mismatch_detail, idx, 15))
+ return 0;
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
case AARCH64_OPND_CLASS_PRED_REG:
if (opnd->reg.regno >= 8
&& get_operand_fields_width (get_operand_from_code (type)) == 3)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ff0b04af794..98b2b01b2a2 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5909,32 +5909,29 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
"a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
- "an SME ZA tile ZA0-ZA3") \
+ "an SME ZA tile ZA0-ZA3") \
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
- "an SME ZA tile ZA0-ZA7") \
- Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \
- F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5),\
- "an SME horizontal or vertical vector access register") \
- Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \
- F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2),\
- "an SME horizontal or vertical vector access register") \
+ "an SME ZA tile ZA0-ZA7") \
+ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \
+ F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \
+ "an SME horizontal or vertical vector access register") \
+ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \
+ F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \
+ "an SME horizontal or vertical vector access register") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
- Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
- F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
- Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
+ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
+ F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
+ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \
- "an SME horizontal or vertical vector access register") \
- Y(SVE_REG, sme_za_array, "SME_ZA_array", 0, \
- F(FLD_SME_Rv,FLD_imm4_2), \
- "ZA array") \
+ "an SME horizontal or vertical vector access register") \
+ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array", 0, \
+ F(FLD_SME_Rv,FLD_imm4_2), "ZA array") \
Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \
- F(FLD_Rn,FLD_imm4_2), \
- "memory offset") \
- Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \
- F(FLD_CRm), \
- "streaming mode") \
- Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
+ F(FLD_Rn,FLD_imm4_2), "memory offset") \
+ Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \
+ F(FLD_CRm), "streaming mode") \
+ Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
"Source scalable predicate register with index ") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 17/43] aarch64: Consolidate ZA slice parsing
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (15 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
` (25 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Now that parse_typed_reg checks the range of tile register numbers
and libopcodes checks the range of vector select offsets, there's
very little difference between the parsing of ZA tile indices,
ZA array indices, and PSEL indices. The main one is that ZA
array indices don't currently allow "za" to be qualified,
but we need to remove that restriction for SME2.
This patch therefore consolidates all three parsers into a single
routine, parameterised by the type of register that they expect.
---
gas/config/tc-aarch64.c | 94 ++++++-----------------
gas/testsuite/gas/aarch64/sme-7-illegal.l | 17 ++++
gas/testsuite/gas/aarch64/sme-7-illegal.s | 8 ++
gas/testsuite/gas/aarch64/sme-9-illegal.l | 7 ++
gas/testsuite/gas/aarch64/sme-9-illegal.s | 1 +
5 files changed, 55 insertions(+), 72 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ba7f543e033..e5185353013 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4422,25 +4422,27 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
return true;
}
-/* Parse SME ZA horizontal or vertical vector access to tiles.
+/* Parse a register of type REG_TYPE that might have an element type
+ qualifier and that is indexed by two values: a 32-bit register,
+ followed by an immediate. The 32-bit register must be W12-W15.
+ The range of the immediate varies by opcode and is checked in
+ libopcodes.
+
Return true on success, populating OPND with information about
- the indexed tile and QUALIFIER with the qualifier that was applied
- to the tile name.
+ the operand and setting QUALIFIER to the register qualifier.
Field format examples:
- ZA0<HV>.B[<Wv>, #<imm>]
- <ZAn><HV>.H[<Wv>, #<imm>]
- <ZAn><HV>.S[<Wv>, #<imm>]
- <ZAn><HV>.D[<Wv>, #<imm>]
- <ZAn><HV>.Q[<Wv>, #<imm>]
+ <Pm>.<T>[<Wv>< #<imm>]
+ ZA[<Wv>, #<imm>]
+ <ZAn><HV>.<T>[<Wv>, #<imm>]
*/
static bool
-parse_sme_za_hv_tiles_operand (char **str,
- struct aarch64_indexed_za *opnd,
- aarch64_opnd_qualifier_t *qualifier)
+parse_dual_indexed_reg (char **str, aarch64_reg_type reg_type,
+ struct aarch64_indexed_za *opnd,
+ aarch64_opnd_qualifier_t *qualifier)
{
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier);
if (!reg)
return false;
@@ -4464,7 +4466,7 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
return false;
}
- if (!parse_sme_za_hv_tiles_operand (str, opnd, qualifier))
+ if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier))
return false;
if (!skip_past_char (str, '}'))
@@ -4585,33 +4587,6 @@ parse_sme_list_of_64bit_tiles (char **str)
return regno;
}
-/* Parse ZA array operand used in e.g. STR and LDR instruction.
- Operand format:
-
- ZA[<Wv>, <imm>]
- ZA[<Wv>, #<imm>]
-
- Return true on success, populating OPND with information about
- the operand. */
-
-static bool
-parse_sme_za_array (char **str, struct aarch64_indexed_za *opnd)
-{
- char *q;
-
- q = *str;
- const reg_entry *reg = parse_reg (&q);
- if (!reg || reg->type != REG_TYPE_ZA)
- {
- set_syntax_error (_("expected ZA array"));
- return false;
- }
- opnd->regno = -1;
-
- *str = q;
- return parse_sme_za_index (str, opnd);
-}
-
/* Parse streaming mode operand for SMSTART and SMSTOP.
{SM | ZA}
@@ -4638,32 +4613,6 @@ parse_sme_sm_za (char **str)
return TOLOWER (p[0]);
}
-/* Parse the name of the source scalable predicate register, the index base
- register W12-W15 and the element index. Function performs element index
- limit checks as well as qualifier type checks.
-
- <Pn>.<T>[<Wv>, <imm>]
- <Pn>.<T>[<Wv>, #<imm>]
-
- Return true on success, populating OPND with information about the index
- and setting QUALIFIER to <T>. */
-
-static bool
-parse_sme_pred_reg_with_index (char **str, struct aarch64_indexed_za *opnd,
- aarch64_opnd_qualifier_t *qualifier)
-{
- const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
- if (reg == NULL)
- return false;
-
- opnd->regno = reg->number;
-
- if (! parse_sme_za_index (str, opnd))
- return false;
-
- return true;
-}
-
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
@@ -7060,9 +7009,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_PnT_Wm_imm:
- /* <Pn>.<T>[<Wm>, #<imm>] */
- if (!parse_sme_pred_reg_with_index (&str, &info->indexed_za,
- &qualifier))
+ if (!parse_dual_indexed_reg (&str, REG_TYPE_PN,
+ &info->indexed_za, &qualifier))
goto failure;
info->qualifier = qualifier;
break;
@@ -7396,8 +7344,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
? !parse_sme_za_hv_tiles_operand_with_braces (&str,
&info->indexed_za,
&qualifier)
- : !parse_sme_za_hv_tiles_operand (&str, &info->indexed_za,
- &qualifier))
+ : !parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
+ &info->indexed_za, &qualifier))
goto failure;
info->qualifier = qualifier;
break;
@@ -7410,8 +7358,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_ZA_array:
- if (!parse_sme_za_array (&str, &info->indexed_za))
+ if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
+ &info->indexed_za, &qualifier))
goto failure;
+ info->qualifier = qualifier;
break;
case AARCH64_OPND_MOPS_ADDR_Rd:
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index 242c5ec75d3..cee93c85bac 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -31,3 +31,20 @@
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]'
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.b\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.h\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.s\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.d\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.q\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
+[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `ldr za/z\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `ldr za.2b\[w12,0\],\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s
index 0d92d843a4f..0669fe16dd4 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s
@@ -37,3 +37,11 @@ ldr za[w13, -1], [x17, #1, mul vl]
str za[w13, -1], [x17, #1, mul vl]
ldr za[w13, 1], [x17, #-1, mul vl]
str za[w13, 1], [x17, #-1, mul vl]
+
+ldr za.b[w12, 0], [x0]
+ldr za.h[w12, 0], [x0]
+ldr za.s[w12, 0], [x0]
+ldr za.d[w12, 0], [x0]
+ldr za.q[w12, 0], [x0]
+ldr za/z[w12, 0], [x0]
+ldr za.2b[w12, 0], [x0]
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
index 4d4520c55bd..b0554c5168f 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -8,6 +8,13 @@
[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
+[^:]*:[0-9]+: Error: operand mismatch -- `psel p1,p15,p3\[w15,#0\]'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: psel p1, p15, p3.b\[w15, 0\]
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
+[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
+[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s
index 88d25fca10b..2351d711b64 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s
@@ -3,6 +3,7 @@
psel p1, p15, p3.b[w12]
psel p1, p15, p3.q[w15]
psel p1, p15, p3.q[w15, #0]
+psel p1, p15, p3[w15,#0]
psel p1, p15, p3.b[w11]
psel p8, p11, p15.h[w16]
psel p2, p7, p15.s[w3]
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 18/43] aarch64: Commonise index parsing
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (16 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
` (24 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Just a minor clean-up to factor out the index parsing, partly to
ensure that the error handling remains consistent. No behavioural
change intended.
---
gas/config/tc-aarch64.c | 42 ++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e5185353013..dafd5bc296c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1022,6 +1022,23 @@ aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
}
}
+/* Parse an index expression at *STR, storing it in *IMM on success. */
+
+static bool
+parse_index_expression (char **str, int64_t *imm)
+{
+ expressionS exp;
+
+ aarch64_get_expression (&exp, str, GE_NO_PREFIX, REJECT_ABSENT);
+ if (exp.X_op != O_constant)
+ {
+ first_error (_("constant expression required"));
+ return false;
+ }
+ *imm = exp.X_add_number;
+ return true;
+}
+
/* Parse a register of the type TYPE.
Return null if the string pointed to by *CCP is not a valid register
@@ -1116,8 +1133,6 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
{
- expressionS exp;
-
/* Reject Sn[index] syntax. */
if (!is_typed_vecreg)
{
@@ -1133,18 +1148,11 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
atype.defined |= NTA_HASINDEX;
- aarch64_get_expression (&exp, &str, GE_NO_PREFIX, REJECT_ABSENT);
-
- if (exp.X_op != O_constant)
- {
- first_error (_("constant expression required"));
- return NULL;
- }
+ if (!parse_index_expression (&str, &atype.index))
+ return NULL;
if (! skip_past_char (&str, ']'))
return NULL;
-
- atype.index = exp.X_add_number;
}
else if (!(flags & PTR_IN_REGLIST) && (atype.defined & NTA_HASINDEX) != 0)
{
@@ -1318,18 +1326,10 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
{
if (skip_past_char (&str, '['))
{
- expressionS exp;
-
- aarch64_get_expression (&exp, &str, GE_NO_PREFIX, REJECT_ABSENT);
- if (exp.X_op != O_constant)
- {
- set_first_syntax_error (_("constant expression required."));
- error = true;
- }
+ if (!parse_index_expression (&str, &typeinfo_first.index))
+ error = true;
if (! skip_past_char (&str, ']'))
error = true;
- else
- typeinfo_first.index = exp.X_add_number;
}
else
{
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (17 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
` (23 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
In SME, the vector select register had to be in the range
w12-w15, so it made sense to enforce that during parsing.
However, SME2 adds instructions for which the range is
w8-w11 instead.
This patch therefore moves the range check from the parsing
stage to the constraint-checking stage.
Also, the previous error used a capitalised range W12-W15,
whereas other register range errors used lowercase ranges
like p0-p7. A quick internal poll showed a preference for
the lowercase form, so the patch uses that.
The patch uses "selection register" rather than "vector
select register" so that the terminology extends more
naturally to PSEL.
---
gas/config/tc-aarch64.c | 15 ++++++-------
gas/testsuite/gas/aarch64/sme-2-illegal.l | 10 ++++-----
gas/testsuite/gas/aarch64/sme-5-illegal.l | 4 ++--
gas/testsuite/gas/aarch64/sme-6-illegal.l | 4 ++--
gas/testsuite/gas/aarch64/sme-7-illegal.l | 8 +++----
gas/testsuite/gas/aarch64/sme-9-illegal.l | 12 +++++++----
gas/testsuite/gas/aarch64/sme-9-illegal.s | 4 ++++
opcodes/aarch64-opc.c | 26 +++++++++++++++++------
8 files changed, 51 insertions(+), 32 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index dafd5bc296c..d938aa9eb83 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4372,11 +4372,10 @@ parse_sme_immediate (char **str, int64_t *imm)
return true;
}
-/* Parse index with vector select register and immediate:
+/* Parse index with selection register and immediate offset:
[<Wv>, <imm>]
[<Wv>, #<imm>]
- where <Wv> is in W12-W15 range and # is optional for immediate.
Return true on success, populating OPND with the parsed index. */
@@ -4391,12 +4390,11 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
return false;
}
- /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
+ /* The selection register, encoded in the 2-bit Rv field. */
reg = parse_reg (str);
- if (reg == NULL || reg->type != REG_TYPE_R_32
- || reg->number < 12 || reg->number > 15)
+ if (reg == NULL || reg->type != REG_TYPE_R_32)
{
- set_syntax_error (_("expected vector select register W12-W15"));
+ set_syntax_error (_("expected a 32-bit selection register"));
return false;
}
opnd->index.regno = reg->number;
@@ -4424,9 +4422,8 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
/* Parse a register of type REG_TYPE that might have an element type
qualifier and that is indexed by two values: a 32-bit register,
- followed by an immediate. The 32-bit register must be W12-W15.
- The range of the immediate varies by opcode and is checked in
- libopcodes.
+ followed by an immediate. The ranges of the register and the
+ immediate vary by opcode and are checked in libopcodes.
Return true on success, populating OPND with information about
the operand and setting QUALIFIER to the register qualifier.
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index eaf1b975a81..9d3495aebc0 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -11,12 +11,12 @@
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]'
[^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.h,p0/m,za0v\.h\[w12\. 0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
+[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0.q,p0/m,za0v\.q\[w12,\]'
[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12\.\]'
[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,abc\]'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index d706a169f3a..14d3cf456f3 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -1,6 +1,6 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index d2a3f3ca09e..b2527ead250 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -1,6 +1,6 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index cee93c85bac..cf4bca2cd20 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -1,22 +1,22 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w14,9\],\[x17,#9,mul#3\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w15,15\],\[sp,#15,mul#4\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w11,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `str za\[w11,0\],\[x0\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]'
[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]'
[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w14,9\],\[x17,#9,mul#3\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
index b0554c5168f..1a33420dc35 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -15,10 +15,14 @@
[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
-[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w11\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p8,p11,p15.h\[w16\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p2,p7,p15.s\[w3\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p1,p15,p3.b\[w11,#0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p8,p11,p15.h\[w16,#0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p2,p7,p15.s\[w3,#0\]'
+[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p13,p3,p1.d\[w17,#0\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s
index 2351d711b64..f59582eeb8b 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s
@@ -8,6 +8,10 @@ psel p1, p15, p3.b[w11]
psel p8, p11, p15.h[w16]
psel p2, p7, p15.s[w3]
psel p13, p3, p1.d[w17]
+psel p1, p15, p3.b[w11, #0]
+psel p8, p11, p15.h[w16, #0]
+psel p2, p7, p15.s[w3, #0]
+psel p13, p3, p1.d[w17, #0]
psel p5, p12, p9.b[w15, #16]
psel p1, p8, p6.h[w14, #8]
psel p8, p4, p15.s[w13, #4]
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 746edde7516..24cca9e8193 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1438,14 +1438,28 @@ set_other_error (aarch64_operand_error *mismatch_detail, int idx,
set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
}
-/* Check that indexed ZA operand OPND has a vector select offset
- in the range [0, MAX_VALUE]. */
+/* Check that indexed ZA operand OPND has:
+
+ - a selection register in the range [MIN_WREG, MIN_WREG + 3]
+
+ - an immediate offset in the range [0, MAX_VALUE]. */
static bool
check_za_access (const aarch64_opnd_info *opnd,
aarch64_operand_error *mismatch_detail, int idx,
- int max_value)
+ int min_wreg, int max_value)
{
+ if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
+ {
+ if (min_wreg == 12)
+ set_other_error (mismatch_detail, idx,
+ _("expected a selection register in the"
+ " range w12-w15"));
+ else
+ abort ();
+ return false;
+ }
+
if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_value))
{
set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value);
@@ -1593,7 +1607,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_PnT_Wm_imm:
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
- if (!check_za_access (opnd, mismatch_detail, idx, max_value))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value))
return 0;
break;
@@ -1610,12 +1624,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
- if (!check_za_access (opnd, mismatch_detail, idx, max_value))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value))
return 0;
break;
case AARCH64_OPND_SME_ZA_array:
- if (!check_za_access (opnd, mismatch_detail, idx, 15))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, 15))
return 0;
break;
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 20/43] aarch64: Tweak error for missing immediate offset
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (18 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
` (22 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch tweaks the error message that is printed when
a ZA-style index is missing the immediate offset.
---
gas/config/tc-aarch64.c | 6 +++---
gas/testsuite/gas/aarch64/sme-2-illegal.l | 12 ++++++------
gas/testsuite/gas/aarch64/sme-5-illegal.l | 4 ++--
gas/testsuite/gas/aarch64/sme-6-illegal.l | 2 +-
gas/testsuite/gas/aarch64/sme-9-illegal.l | 12 ++++++------
5 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d938aa9eb83..32375307b8e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4399,15 +4399,15 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
}
opnd->index.regno = reg->number;
- if (!skip_past_char (str, ',')) /* Optional index offset immediate. */
+ if (!skip_past_char (str, ','))
{
- set_syntax_error (_("expected ','"));
+ set_syntax_error (_("missing immediate offset"));
return false;
}
if (!parse_sme_immediate (str, &opnd->index.imm))
{
- set_syntax_error (_("index offset immediate expected"));
+ set_syntax_error (_("expected a constant immediate offset"));
return false;
}
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index 9d3495aebc0..b4ce9dc69fd 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -9,18 +9,18 @@
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 3 -- `mova z31\.d,p7/m,za7v\.d\[w15,#2\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]'
[^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b'
[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.h,p0/m,za0v\.h\[w12\. 0\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `mova z0\.h,p0/m,za0v\.h\[w12\. 0\]'
[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
-[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0.q,p0/m,za0v\.q\[w12,\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12\.\]'
-[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,abc\]'
-[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#abc\]'
+[^:]*:[0-9]+: Error: expected a constant immediate offset at operand 3 -- `mova z0.q,p0/m,za0v\.q\[w12,\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12\.\]'
+[^:]*:[0-9]+: Error: expected a constant immediate offset at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,abc\]'
+[^:]*:[0-9]+: Error: expected a constant immediate offset at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#abc\]'
[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,1a\]'
[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#1a\]'
[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,1a2\]'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index 14d3cf456f3..852f1547634 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -4,7 +4,7 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x0,lsl#2\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]'
@@ -48,4 +48,4 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {za3v.s\[w12,3\]},p7/z,\[x0,x1,lsl#3\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index b2527ead250..30aea0b75ea 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -4,7 +4,7 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]'
[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `st1q {za0v.q\[w12\]},p0,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 1 -- `st1q {za0v.q\[w12\]},p0,\[x0,x0,lsl#2\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
index 1a33420dc35..0243c9efcdf 100644
--- a/gas/testsuite/gas/aarch64/sme-9-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -1,6 +1,6 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w12\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.q\[w15\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `psel p1,p15,p3.b\[w12\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `psel p1,p15,p3.q\[w15\]'
[^:]*:[0-9]+: Error: operand mismatch -- `psel p1,p15,p3.q\[w15,#0\]'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: psel p1, p15, p3.b\[w15, 0\]
@@ -15,10 +15,10 @@
[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w11\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p8,p11,p15.h\[w16\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p2,p7,p15.s\[w3\]'
-[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `psel p1,p15,p3.b\[w11\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `psel p8,p11,p15.h\[w16\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `psel p2,p7,p15.s\[w3\]'
+[^:]*:[0-9]+: Error: missing immediate offset at operand 3 -- `psel p13,p3,p1.d\[w17\]'
[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p1,p15,p3.b\[w11,#0\]'
[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p8,p11,p15.h\[w16,#0\]'
[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p2,p7,p15.s\[w3,#0\]'
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 21/43] aarch64: Tweak errors for base & offset registers
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (19 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
` (21 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
parse_address_main currently uses get_reg_expected_msg to
report invalid base and offset registers, but the disadvantage
of doing that is that it isn't immediately clear which register
is wrong (the base or the offset).
A later patch moves away from using get_reg_expected_msg for failed
type checks, but doing that here didn't seem like the best approach.
The patch tries to use more tailored messages instead.
---
gas/config/tc-aarch64.c | 14 +-
gas/testsuite/gas/aarch64/diagnostic.l | 17 +-
gas/testsuite/gas/aarch64/diagnostic.s | 4 +
gas/testsuite/gas/aarch64/illegal-ldapr.l | 6 +-
gas/testsuite/gas/aarch64/illegal-ldraa.l | 8 +-
gas/testsuite/gas/aarch64/illegal-lse.l | 456 +++++++++---------
gas/testsuite/gas/aarch64/illegal-memtag.l | 18 +-
gas/testsuite/gas/aarch64/illegal-sve2.l | 68 +--
.../gas/aarch64/sve-reg-diagnostic.l | 10 +-
9 files changed, 308 insertions(+), 293 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 32375307b8e..ee88c8fe7c9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3819,10 +3819,18 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
/* [ */
+ bool alpha_base_p = ISALPHA (*p);
reg = aarch64_addr_reg_parse (&p, base_type, base_qualifier);
if (!reg || !aarch64_check_reg_type (reg, base_type))
{
- set_syntax_error (_(get_reg_expected_msg (base_type)));
+ if (reg
+ && aarch64_check_reg_type (reg, REG_TYPE_R_SP)
+ && *base_qualifier == AARCH64_OPND_QLF_W)
+ set_syntax_error (_("expected a 64-bit base register"));
+ else if (alpha_base_p)
+ set_syntax_error (_("invalid base register"));
+ else
+ set_syntax_error (_("expected a base register"));
return false;
}
operand->addr.base_regno = reg->number;
@@ -3838,7 +3846,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
{
if (!aarch64_check_reg_type (reg, offset_type))
{
- set_syntax_error (_(get_reg_expected_msg (offset_type)));
+ set_syntax_error (_("invalid offset register"));
return false;
}
@@ -3974,7 +3982,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
/* [Xn],Xm */
if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
{
- set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
+ set_syntax_error (_("invalid offset register"));
return false;
}
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 87cc4feee6f..99359891c5f 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -54,7 +54,7 @@
[^:]*:56: Error: operand 2 must be a floating-point register -- `fcmp d0,x0'
[^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
-[^:]*:59: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
+[^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
[^:]*:60: Error: writeback value must be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr'
[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
@@ -116,10 +116,10 @@
[^:]*:126: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16'
[^:]*:127: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `adr x2,:got:s1'
[^:]*:128: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `ldr x0,\[x0,:got:s1\]'
-[^:]*:131: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[wsp,#8\]!'
-[^:]*:132: Error: 64-bit integer or SP register expected at operand 3 -- `ldp x6,x29,\[w7,#8\]!'
-[^:]*:133: Error: 64-bit integer or SP register expected at operand 2 -- `str x30,\[w11,#8\]!'
-[^:]*:134: Error: 64-bit integer or SP register expected at operand 3 -- `stp x8,x27,\[wsp,#8\]!'
+[^:]*:131: Error: expected a 64-bit base register at operand 2 -- `ldr x1,\[wsp,#8\]!'
+[^:]*:132: Error: expected a 64-bit base register at operand 3 -- `ldp x6,x29,\[w7,#8\]!'
+[^:]*:133: Error: expected a 64-bit base register at operand 2 -- `str x30,\[w11,#8\]!'
+[^:]*:134: Error: expected a 64-bit base register at operand 3 -- `stp x8,x27,\[wsp,#8\]!'
[^:]*:214: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[-1\]'
[^:]*:217: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[2\]'
[^:]*:218: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[64\]'
@@ -144,8 +144,8 @@
[^:]*:256: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[-1\],\[x0\]'
[^:]*:259: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[16\],\[x0\]'
[^:]*:260: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[67\],\[x0\]'
-[^:]*:267: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr'
-[^:]*:268: Error: integer or zero register expected at operand 2 -- `str x1,\[x2,sp\]'
+[^:]*:267: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr'
+[^:]*:268: Error: invalid offset register at operand 2 -- `str x1,\[x2,sp\]'
[^:]*:271: Error: relocation not allowed at operand 3 -- `ldnp x1,x2,\[x3,#:lo12:foo\]'
[^:]*:272: Error: invalid addressing mode at operand 2 -- `ld1 {v0\.4s},\[x3,#:lo12:foo\]'
[^:]*:273: Error: the optional immediate offset can only be 0 at operand 2 -- `stuminl x0,\[x3,#:lo12:foo\]'
@@ -183,3 +183,6 @@
[^:]*:312: Warning: unpredictable load of register pair -- `ldxp x26,x26,\[x5\]'
[^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
[^:]*:315: Warning: unpredictable: identical base and status registers --`stlxp w3,w26,w26,\[x3\]'
+[^:]*:317: Error: expected a base register at operand 2 -- `ldr x0,\[1\]'
+[^:]*:318: Error: expected a base register at operand 2 -- `ldr x0,\[\]'
+[^:]*:319: Error: expected a base register at operand 2 -- `ldr x0,\[,xzr\]'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index 0ebe85ac59d..014e0abe332 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -313,3 +313,7 @@
ldxp x26, x1, [x26]
st4 {v0.16b-v3.16b}[4], [x0]
stlxp w3, w26, w26, [x3]
+
+ ldr x0, [1]
+ ldr x0, []
+ ldr x0, [,xzr]
diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l
index 8a91e79e8ef..5e3ca6d2e5c 100644
--- a/gas/testsuite/gas/aarch64/illegal-ldapr.l
+++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l
@@ -2,7 +2,7 @@
[^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]'
[^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]'
[^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]'
-[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]'
+[^:]+:5: Error: invalid base register at operand 2 -- `ldaprb w1,\[xz\]'
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]'
[^:]+:23: Info: macro .*
@@ -10,7 +10,7 @@
[^:]+:23: Info: macro .*
[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8'
[^:]+:23: Info: macro .*
-[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]'
+[^:]+:5: Error: invalid base register at operand 2 -- `ldaprh w1,\[xz\]'
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]'
[^:]+:23: Info: macro .*
@@ -18,7 +18,7 @@
[^:]+:23: Info: macro .*
[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8'
[^:]+:23: Info: macro .*
-[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]'
+[^:]+:5: Error: invalid base register at operand 2 -- `ldapr w1,\[xz\]'
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
[^:]+:23: Info: macro .*
diff --git a/gas/testsuite/gas/aarch64/illegal-ldraa.l b/gas/testsuite/gas/aarch64/illegal-ldraa.l
index 33fae2f4f29..b9a792298f6 100644
--- a/gas/testsuite/gas/aarch64/illegal-ldraa.l
+++ b/gas/testsuite/gas/aarch64/illegal-ldraa.l
@@ -5,7 +5,7 @@
[^:]+:12: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]'
[^:]+:13: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]'
[^:]+:14: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]'
-[^:]+:15: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
+[^:]+:15: Error: invalid base register at operand 2 -- `ldraa x0,\[xz\]'
[^:]+:16: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],'
[^:]+:17: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!'
[^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!'
@@ -13,7 +13,7 @@
[^:]+:20: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]!'
[^:]+:21: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]!'
[^:]+:22: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]!'
-[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
+[^:]+:23: Error: invalid base register at operand 2 -- `ldraa x0,\[xz\]'
[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldraa x0,\[x1\],#8'
[^:]+:27: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]'
[^:]+:28: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]'
@@ -21,7 +21,7 @@
[^:]+:30: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]'
[^:]+:31: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]'
[^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]'
-[^:]+:33: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
+[^:]+:33: Error: invalid base register at operand 2 -- `ldrab x0,\[xz\]'
[^:]+:34: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],'
[^:]+:35: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!'
[^:]+:36: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!'
@@ -29,5 +29,5 @@
[^:]+:38: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]!'
[^:]+:39: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]!'
[^:]+:40: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]!'
-[^:]+:41: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
+[^:]+:41: Error: invalid base register at operand 2 -- `ldrab x0,\[xz\]'
[^:]+:42: Error: invalid addressing mode at operand 2 -- `ldrab x0,\[x1\],#8'
diff --git a/gas/testsuite/gas/aarch64/illegal-lse.l b/gas/testsuite/gas/aarch64/illegal-lse.l
index b47108df161..7c87a84bccc 100644
--- a/gas/testsuite/gas/aarch64/illegal-lse.l
+++ b/gas/testsuite/gas/aarch64/illegal-lse.l
@@ -1,131 +1,131 @@
[^:]*: Assembler messages:
[^:]*:26: Error: operand mismatch -- `cas w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `cas w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `cas w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casa w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casa w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casa w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casl w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casl w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casal w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casal w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casb w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casb w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `cash w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `cash w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `cash w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casab w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casab w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `caslb w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `caslb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `caslb w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casalb w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casalb w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casah w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casah w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `caslh w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `caslh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `caslh w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `casalh w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casalh w2,w3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `cas w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `cas x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `cas x2,x3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `casa w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casa x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `casa x2,x3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `casl w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `casl x2,x3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `casal w0,x1,\[x2\]'
[^:]*:68: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `casal x2,x3,\[w4\]'
[^:]*:68: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swp w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swp w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swp w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpa w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpa w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpl w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpal w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpb w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpb w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swph w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swph w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swph w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpab w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpab w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swplb w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swplb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swplb w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpalb w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpalb w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpah w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpah w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swplh w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swplh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swplh w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `swpalh w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpalh w2,w3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `swp w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swp x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swp x2,x3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpa x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swpa x2,x3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swpl x2,x3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
[^:]*:69: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swpal x2,x3,\[w4\]'
[^:]*:69: *Info: macro .*
[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]'
[^:]*:70: *Info: macro .*
@@ -133,7 +133,7 @@
[^:]*:70: *Info: macro .*
[^:]*:49: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]'
[^:]*:70: *Info: macro .*
-[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `casp x4,x5,x6,x7,\[w8\]'
+[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `casp x4,x5,x6,x7,\[w8\]'
[^:]*:70: *Info: macro .*
[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]'
[^:]*:70: *Info: macro .*
@@ -141,7 +141,7 @@
[^:]*:70: *Info: macro .*
[^:]*:49: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]'
[^:]*:70: *Info: macro .*
-[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]'
+[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]'
[^:]*:70: *Info: macro .*
[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]'
[^:]*:70: *Info: macro .*
@@ -149,7 +149,7 @@
[^:]*:70: *Info: macro .*
[^:]*:49: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]'
[^:]*:70: *Info: macro .*
-[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]'
+[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]'
[^:]*:70: *Info: macro .*
[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]'
[^:]*:70: *Info: macro .*
@@ -157,1061 +157,1061 @@
[^:]*:70: *Info: macro .*
[^:]*:49: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]'
[^:]*:70: *Info: macro .*
-[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]'
+[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]'
[^:]*:70: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldadd w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldadda w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddal w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddalb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddalh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldadd x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldadda x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldaddl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldaddal x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclr w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclra w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclral w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclralb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclralh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclr x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclra x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclrl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclral x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeor w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeora w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeoral w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeoralb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeoralh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeor x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeora x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeorl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeoral x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldset w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldset w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldseta w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetal w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldseth w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldseth w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldseth w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetalb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetalh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldset x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldset x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldseta x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsetl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsetal x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmax w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxa w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxal w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxalb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxalh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmax x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmaxa x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmaxl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmaxal x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmin w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmina w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminal w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminalb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminalh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmin x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmina x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsminl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsminal x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumax w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxa w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxal w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxalb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxalh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumax x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumaxa x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumaxl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumaxal x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumin w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumina w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminl w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminal w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminab w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminab w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminab w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminlb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalb w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminalb w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminah w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminah w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminah w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminlh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:26: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalh w2,w3,\[w4\]'
+[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminalh w2,w3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumin x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumina x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `lduminl x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
[^:]*:30: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal x2,x3,\[w4\]'
+[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `lduminal x2,x3,\[w4\]'
[^:]*:56: *Info: macro .*
[^:]*:71: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stadd w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stadd w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `staddb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `staddh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `staddlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `staddlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stadd x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stadd x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `staddl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `staddl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclr w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclr w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stclrb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stclrh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stclrlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stclrlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stclr x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stclr x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stclrl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steor w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steor w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `steorb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `steorh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `steorlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `steorlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `steor x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `steor x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `steorl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `steorl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stset w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stset w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsetb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stseth x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stseth w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stseth w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsetlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsetlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stset x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stset x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsetl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmax w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsmaxb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsmaxh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsmaxlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsmaxlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsmax x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsmaxl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmin w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsminb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsminh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsminlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stsminlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsmin x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsminl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumax w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumax w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stumaxb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stumaxh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stumaxlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stumaxlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumax x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stumax x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stumaxl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumin w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumin w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminl w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stuminb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stuminh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stuminlb x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlb w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminlb w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
[^:]*:37: Error: operand mismatch -- `stuminlh x0,\[x2\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlh w2,\[w3\]'
+[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminlh w2,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumin x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stumin x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
-[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl x0,\[w3\]'
+[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stuminl x0,\[w3\]'
[^:]*:62: *Info: macro .*
[^:]*:72: *Info: macro .*
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 67ec2831a52..7e48f0a71e9 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -34,22 +34,22 @@
[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stg x2,\[xzr,#0\]'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stg x2,\[xzr,#0\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `st2g x2,\[xzr,#0\]!'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzg x2,\[xzr\],#0'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stz2g x2,\[xzr,#0\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzgm x0,\[xzr\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldg x0,\[xzr,#16\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgm x0,\[xzr\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgm x0,\[xzr\]'
+[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index c3ef21aa6d9..6241de123db 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -493,8 +493,8 @@
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -510,8 +510,8 @@
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
@@ -520,8 +520,8 @@
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -540,8 +540,8 @@
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -551,8 +551,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
@@ -563,8 +563,8 @@
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -576,8 +576,8 @@
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -589,8 +589,8 @@
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -600,8 +600,8 @@
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@@ -611,8 +611,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `match p0\.h,p0/z,z0\.b,z0\.b'
@@ -2217,8 +2217,8 @@
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,z0\.d\]'
@@ -2228,8 +2228,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
@@ -2238,8 +2238,8 @@
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,z0\.d\]'
@@ -2252,8 +2252,8 @@
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,z0\.d\]'
@@ -2263,8 +2263,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
@@ -2273,8 +2273,8 @@
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,z0\.d\]'
@@ -2284,8 +2284,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]'
-[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
-[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `subhnb z0\.h,z0\.h,z0\.h'
diff --git a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
index b0ade281acc..34d6634714a 100644
--- a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
+++ b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
@@ -3,11 +3,11 @@
.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0'
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b'
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b'
-.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[s0\]'
-.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[z0\]'
-.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[z0\.s\]'
-.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[p0\]'
-.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[p0\.b\]'
+.*: Error: invalid base register at operand 2 -- `ldr x1,\[s0\]'
+.*: Error: invalid base register at operand 2 -- `ldr x1,\[z0\]'
+.*: Error: invalid base register at operand 2 -- `ldr x1,\[z0\.s\]'
+.*: Error: invalid base register at operand 2 -- `ldr x1,\[p0\]'
+.*: Error: invalid base register at operand 2 -- `ldr x1,\[p0\.b\]'
.*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl p0\.b\]'
.*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl#p0\.b\]'
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#x0'
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (20 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
` (20 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Integer registers were parsed indirectly through
aarch64_reg_parse_32_64 (and thus aarch64_addr_reg_parse) rather
than directly through parse_reg. This was because we need the
qualifier associated with the register, and the logic to calculate
that was buried in aarch64_addr_reg_parse.
The code that parses FP registers had the same need, but it
open-coded the calculation of the qualifier.
This patch tries to handle both cases in the same way. It is
needed by a later patch that tries to improve the register-related
diagnostics.
---
gas/config/tc-aarch64.c | 71 ++++++++++++++++++++++++-----------------
1 file changed, 42 insertions(+), 29 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ee88c8fe7c9..e8dfcb81bdf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -801,6 +801,38 @@ parse_reg (char **ccp)
return reg;
}
+/* Return the operand qualifier associated with all uses of REG, or
+ AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
+ that qualifiers don't apply to REG or that qualifiers are added
+ using suffixes. */
+
+static aarch64_opnd_qualifier_t
+inherent_reg_qualifier (const reg_entry *reg)
+{
+ switch (reg->type)
+ {
+ case REG_TYPE_R_32:
+ case REG_TYPE_SP_32:
+ case REG_TYPE_Z_32:
+ return AARCH64_OPND_QLF_W;
+
+ case REG_TYPE_R_64:
+ case REG_TYPE_SP_64:
+ case REG_TYPE_Z_64:
+ return AARCH64_OPND_QLF_X;
+
+ case REG_TYPE_FP_B:
+ case REG_TYPE_FP_H:
+ case REG_TYPE_FP_S:
+ case REG_TYPE_FP_D:
+ case REG_TYPE_FP_Q:
+ return AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B);
+
+ default:
+ return AARCH64_OPND_QLF_NIL;
+ }
+}
+
/* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
return FALSE. */
static bool
@@ -828,18 +860,6 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
switch (reg->type)
{
- case REG_TYPE_R_32:
- case REG_TYPE_SP_32:
- case REG_TYPE_Z_32:
- *qualifier = AARCH64_OPND_QLF_W;
- break;
-
- case REG_TYPE_R_64:
- case REG_TYPE_SP_64:
- case REG_TYPE_Z_64:
- *qualifier = AARCH64_OPND_QLF_X;
- break;
-
case REG_TYPE_ZN:
if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) == 0
|| str[0] != '.')
@@ -859,7 +879,10 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
break;
default:
- return NULL;
+ if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
+ return NULL;
+ *qualifier = inherent_reg_qualifier (reg);
+ break;
}
*ccp = str;
@@ -4744,15 +4767,15 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
} \
} while (0)
-#define po_int_reg_or_fail(reg_type) do { \
- reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
+#define po_int_fp_reg_or_fail(reg_type) do { \
+ reg = parse_reg (&str); \
if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
{ \
set_default_error (); \
goto failure; \
} \
info->reg.regno = reg->number; \
- info->qualifier = qualifier; \
+ info->qualifier = inherent_reg_qualifier (reg); \
} while (0)
#define po_imm_nc_or_fail() do { \
@@ -6163,7 +6186,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
case AARCH64_OPND_SVE_Rm:
- po_int_reg_or_fail (REG_TYPE_R_Z);
+ po_int_fp_reg_or_fail (REG_TYPE_R_Z);
/* In LS64 load/store instructions Rt register number must be even
and <=22. */
@@ -6186,7 +6209,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Rt_SP:
case AARCH64_OPND_SVE_Rn_SP:
case AARCH64_OPND_Rm_SP:
- po_int_reg_or_fail (REG_TYPE_R_SP);
+ po_int_fp_reg_or_fail (REG_TYPE_R_SP);
break;
case AARCH64_OPND_Rm_EXT:
@@ -6221,17 +6244,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Vd:
case AARCH64_OPND_SVE_Vm:
case AARCH64_OPND_SVE_Vn:
- reg = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, NULL);
- if (!reg)
- {
- first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
- goto failure;
- }
- gas_assert (reg->type >= REG_TYPE_FP_B
- && reg->type <= REG_TYPE_FP_Q);
-
- info->reg.regno = reg->number;
- info->qualifier = AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B);
+ po_int_fp_reg_or_fail (REG_TYPE_BHSDQ);
break;
case AARCH64_OPND_SVE_Pd:
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 23/43] aarch64: Improve errors for malformed register lists
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (21 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
` (19 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
parse_typed_reg is used for parsing both bare registers and
registers that occur in lists. If it doesn't see a register,
or sees an unexpected kind of register, it queues a default
error to report the problem. These default errors have the form
"operand N must be an X", where X comes from the operand table.
If there are multiple opcode entries that report default errors,
GAS tries to pick the most appropriate one, using the opcode
table order as a tiebreaker. But this can lead to cases where
a syntax error in a register list is reported against an opcode
that doesn't accept register lists. For example, the unlikely
error:
ext z0.b,{,},#0
is reported as:
operand 2 must be an SVE vector register -- `ext z0.b,{,},#0'
even though operand 2 can be a register list.
If we've parsed the opening '{' of a register list, and then see
something that isn't remotely register-like, it seems better to
report that directly as a syntax error, rather than rely on the
default error. The operand won't be a valid list of anything,
so there's no need to pick a specific Y in "operand N must be
a list of Y".
---
gas/config/tc-aarch64.c | 35 ++++++++++++++---------
gas/testsuite/gas/aarch64/illegal-sve2.l | 1 +
gas/testsuite/gas/aarch64/illegal-sve2.s | 1 +
gas/testsuite/gas/aarch64/sme-4-illegal.l | 16 +++++------
gas/testsuite/gas/aarch64/sve-invalid.l | 4 +++
gas/testsuite/gas/aarch64/sve-invalid.s | 5 ++++
6 files changed, 41 insertions(+), 21 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e8dfcb81bdf..596cc0f0813 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1083,6 +1083,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
struct vector_type_el *typeinfo, unsigned int flags)
{
char *str = *ccp;
+ bool isalpha = ISALPHA (*str);
const reg_entry *reg = parse_reg (&str);
struct vector_type_el atype;
struct vector_type_el parsetype;
@@ -1098,7 +1099,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
{
if (typeinfo)
*typeinfo = atype;
- set_default_error ();
+ if (!isalpha && (flags & PTR_IN_REGLIST))
+ set_fatal_syntax_error (_("syntax error in register list"));
+ else
+ set_default_error ();
return NULL;
}
@@ -4361,15 +4365,16 @@ parse_bti_operand (char **str,
REG_TYPE.QUALIFIER
Side effect: Update STR with current parse position of success.
-*/
+
+ FLAGS is as for parse_typed_reg. */
static const reg_entry *
parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
- aarch64_opnd_qualifier_t *qualifier)
+ aarch64_opnd_qualifier_t *qualifier, unsigned int flags)
{
struct vector_type_el vectype;
const reg_entry *reg = parse_typed_reg (str, reg_type, &vectype,
- PTR_FULL_REG);
+ PTR_FULL_REG | flags);
if (!reg)
return NULL;
@@ -4464,13 +4469,16 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
<Pm>.<T>[<Wv>< #<imm>]
ZA[<Wv>, #<imm>]
<ZAn><HV>.<T>[<Wv>, #<imm>]
-*/
+
+ FLAGS is as for parse_typed_reg. */
+
static bool
parse_dual_indexed_reg (char **str, aarch64_reg_type reg_type,
struct aarch64_indexed_za *opnd,
- aarch64_opnd_qualifier_t *qualifier)
+ aarch64_opnd_qualifier_t *qualifier,
+ unsigned int flags)
{
- const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier, flags);
if (!reg)
return false;
@@ -4494,7 +4502,8 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
return false;
}
- if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier))
+ if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier,
+ PTR_IN_REGLIST))
return false;
if (!skip_past_char (str, '}'))
@@ -4527,7 +4536,7 @@ parse_sme_zero_mask(char **str)
do
{
const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT,
- &qualifier);
+ &qualifier, PTR_IN_REGLIST);
if (!reg)
return PARSE_FAIL;
@@ -7028,7 +7037,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_PnT_Wm_imm:
if (!parse_dual_indexed_reg (&str, REG_TYPE_PN,
- &info->indexed_za, &qualifier))
+ &info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
break;
@@ -7348,7 +7357,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
- reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier);
+ reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0);
if (!reg)
goto failure;
info->reg.regno = reg->number;
@@ -7363,7 +7372,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
&info->indexed_za,
&qualifier)
: !parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
- &info->indexed_za, &qualifier))
+ &info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
break;
@@ -7377,7 +7386,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZA_array:
if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
- &info->indexed_za, &qualifier))
+ &info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
break;
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 6241de123db..2eab4120331 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -238,6 +238,7 @@
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eortb z32\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eortb z0\.s,z32\.s,z0\.s'
[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eortb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `ext z0\.b,{,},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s
index 3f3602a8474..4b6285c185e 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.s
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.s
@@ -166,6 +166,7 @@ eortb z32.h, z0.h, z0.h
eortb z0.s, z32.s, z0.s
eortb z0.s, z0.s, z32.s
+ext z0.b, {,}, #0
ext z0.b, { z0.b, z2.b }, #0
ext z0.h, { z0.b, z1.b }, #0
ext z0.b, { z0.h, z1.b }, #0
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index b61832e4223..72f62667768 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -8,16 +8,16 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za3.s,za2.h}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za1.b}'
[^:]*:[0-9]+: Error: unexpected comma after the mnemonic name `zero' -- `zero ,'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,'
[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero }'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,,}'
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,za0.d}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za1.d,}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,za0.d}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,za1.d,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za_}'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 32b7952436f..930d67328e6 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1204,3 +1204,7 @@
.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d\[0\]'
.*: Info: did you mean this\?
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: syntax error in register list at operand 1 -- `ld2b {},p0/z,\[x0\]'
+.*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]'
+.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]'
+.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b,},p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index 204721ee17a..ece2142b072 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1324,3 +1324,8 @@
udot z0.h, z1.h, z2.h[0]
udot z0.s, z1.s, z2.s[0]
udot z0.d, z1.d, z2.d[0]
+
+ ld2b {}, p0/z, [x0]
+ ld2b {.b}, p0/z, [x0]
+ ld2b {z0.b-}, p0/z, [x0]
+ ld2b {z0.b,}, p0/z, [x0]
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 24/43] aarch64: Try to avoid inappropriate default errors
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (22 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
` (18 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
After parsing a '{' and the first register, parse_typed_reg would
report errors in subsequent registers in the same way as for the
first register. It used set_default_error, which reports errors
of the form "operand N must be X".
The problem is that if there are multiple opcode entries for the
same mnemonic, there could be several matches that lead to a
default error. There's no guarantee that the default error for
the register list is the one that will be chosen.
To take an example from the testsuite:
ext z0.b,{z31.b,z32.b},#0
gave:
operand 2 must be an SVE vector register
with the error being reported against the single-vector version
of ext, even though the operand is clearly a list.
This patch uses set_fatal_syntax_error to bump the priority of the
error once we're sure that the operand is a list of the right type.
---
gas/config/tc-aarch64.c | 21 +++++++++++++++++----
gas/testsuite/gas/aarch64/illegal-sve2.l | 2 +-
gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 ++
gas/testsuite/gas/aarch64/sme-4-illegal.s | 2 ++
gas/testsuite/gas/aarch64/sve-invalid.l | 2 ++
gas/testsuite/gas/aarch64/sve-invalid.s | 2 ++
6 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 596cc0f0813..616454b584e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1073,10 +1073,14 @@ parse_index_expression (char **str, int64_t *imm)
FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
FLAGS includes PTR_FULL_REG if the function should ignore any potential
- register index. */
+ register index.
+
+ FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
+ an operand that we can be confident that it is a good match. */
#define PTR_IN_REGLIST (1U << 0)
#define PTR_FULL_REG (1U << 1)
+#define PTR_GOOD_MATCH (1U << 2)
static const reg_entry *
parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1101,6 +1105,8 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
*typeinfo = atype;
if (!isalpha && (flags & PTR_IN_REGLIST))
set_fatal_syntax_error (_("syntax error in register list"));
+ else if (flags & PTR_GOOD_MATCH)
+ set_fatal_syntax_error (NULL);
else
set_default_error ();
return NULL;
@@ -1109,7 +1115,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
if (! aarch64_check_reg_type (reg, type))
{
DEBUG_TRACE ("reg type check failed");
- set_default_error ();
+ if (flags & PTR_GOOD_MATCH)
+ set_fatal_syntax_error (NULL);
+ else
+ set_default_error ();
return NULL;
}
type = reg->type;
@@ -1262,6 +1271,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
int i;
bool error = false;
bool expect_index = false;
+ unsigned int ptr_flags = PTR_IN_REGLIST;
if (*str != '{')
{
@@ -1288,7 +1298,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
val_range = val;
}
const reg_entry *reg = parse_typed_reg (&str, type, &typeinfo,
- PTR_IN_REGLIST);
+ ptr_flags);
if (!reg)
{
set_first_syntax_error (_("invalid vector register in list"));
@@ -1336,6 +1346,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
nb_regs++;
}
in_range = 0;
+ ptr_flags |= PTR_GOOD_MATCH;
}
while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
@@ -4530,13 +4541,14 @@ parse_sme_zero_mask(char **str)
char *q;
int mask;
aarch64_opnd_qualifier_t qualifier;
+ unsigned int ptr_flags = PTR_IN_REGLIST;
mask = 0x00;
q = *str;
do
{
const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT,
- &qualifier, PTR_IN_REGLIST);
+ &qualifier, ptr_flags);
if (!reg)
return PARSE_FAIL;
@@ -4581,6 +4593,7 @@ parse_sme_zero_mask(char **str)
return PARSE_FAIL;
}
}
+ ptr_flags |= PTR_GOOD_MATCH;
}
while (skip_past_char (&q, ','));
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 2eab4120331..13df21b4a4e 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -255,7 +255,7 @@
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z31\.b,z32\.b},#0'
+[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0'
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index 72f62667768..57d7d65c08c 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -16,6 +16,8 @@
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,za0.d}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,z1.d}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za32.d}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,za1.d,}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.s b/gas/testsuite/gas/aarch64/sme-4-illegal.s
index 3d81942f724..da4aa3da266 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.s
@@ -19,6 +19,8 @@ zero { , , }
zero { za0 }
zero { , za0.d }
zero { za0.d , }
+zero { za0.d, z1.d }
+zero { za0.d, za32.d }
zero { za0.d , za1.d , }
zero { za, }
zero { za. }
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 930d67328e6..b0750933612 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1208,3 +1208,5 @@
.*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]'
.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]'
.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b,},p0/z,\[x0\]'
+.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-z32\.b},p0/z,\[x0\]'
+.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-v1\.16b},p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index ece2142b072..b56a08dc15c 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1329,3 +1329,5 @@
ld2b {.b}, p0/z, [x0]
ld2b {z0.b-}, p0/z, [x0]
ld2b {z0.b,}, p0/z, [x0]
+ ld2b {z0.b-z32.b}, p0/z, [x0]
+ ld2b {z0.b-v1.16b}, p0/z, [x0]
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 25/43] aarch64: Rework reporting of failed register checks
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (23 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
` (17 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
There are many opcode table entries that share the same mnemonic.
Trying to parse an invalid assembly line will trigger an error for
each of these entries, but the specific error might vary from one
entry to another, depending on the exact nature of the problem.
GAS has quite an elaborate system for picking the most appropriate
error out of all the failed matches. And in many cases it works well.
However, one of the limitations is that the error is always reported
against a single opcode table entry. If that table entry isn't the
one that the user intended to use, then the error can end up being
overly specific.
This is particularly true if an instruction has a typoed register
name, or uses a type of register that is not accepted by any
opcode table entry. For example, one of the expected error
matches for an attempted SVE2 instruction is:
Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
even though the hypothetical user was presumably attempting to use
the SVE form of ADDP rather than the Advanced SIMD one. There are
many other instances of this in the testsuite.
The problem becomes especially acute with SME2, since many SME2
instructions reuse existing mnemonics. This could lead to us
reporting an SME-related error against a non-SME instruction,
or a non-SME-related error against an SME instruction.
This patch tries to improve things by collecting together all
the register types that an opcode table entry expected for a
given operand. It also records what kind of register was
actually seen, if any. It then tries to summarise all this
in a more directed way, falling back to a generic error if
the combination defies a neat summary.
The patch includes tests for all new messages except REG_TYPE_ZA,
which only triggers with SME2.
To test this, I created an assembly file that contained the cross
product of all known mnemonics and one example from each register
class. I then looked for cases where the new routines fell back on the
generic errors ("expected a register" or "unexpected register type").
I locally added dummy messages for each one until there were no
more hits. The patch adds a specimen instruction to diagnostics.s
for each of these combinations. In each case, the combination didn't
seem like something that could be summarised in a natural way, so the
generic messages seemed better. There's always going to be an element
of personal taste around this kind of thing though.
Adding more register types made 1<<REG_TYPE_MAX exceed the range
of the type, but we don't actually need/want 1<<REG_TYPE_MAX.
---
gas/config/tc-aarch64.c | 400 +++--
.../aarch64/armv8_2-a-crypto-fp16-illegal.l | 6 +-
gas/testsuite/gas/aarch64/diagnostic.l | 26 +-
gas/testsuite/gas/aarch64/diagnostic.s | 19 +
gas/testsuite/gas/aarch64/illegal-bfloat16.l | 40 +-
gas/testsuite/gas/aarch64/illegal-fjcvtzs.l | 6 +-
gas/testsuite/gas/aarch64/illegal-memtag.l | 52 +-
gas/testsuite/gas/aarch64/illegal-sve2.l | 1408 ++++++++---------
gas/testsuite/gas/aarch64/legacy_reg_names.l | 4 +-
gas/testsuite/gas/aarch64/mops_invalid.l | 112 +-
gas/testsuite/gas/aarch64/sme-2-illegal.l | 2 +-
gas/testsuite/gas/aarch64/sme-3-illegal.l | 2 +-
gas/testsuite/gas/aarch64/sme-4-illegal.l | 10 +-
gas/testsuite/gas/aarch64/sme-5-illegal.l | 15 +-
gas/testsuite/gas/aarch64/sme-5-illegal.s | 7 +
gas/testsuite/gas/aarch64/sme-6-illegal.l | 8 +-
gas/testsuite/gas/aarch64/sme-7-illegal.l | 6 +
gas/testsuite/gas/aarch64/sme-7-illegal.s | 7 +
gas/testsuite/gas/aarch64/sme-illegal.l | 1 +
gas/testsuite/gas/aarch64/sme-illegal.s | 1 +
gas/testsuite/gas/aarch64/sve-invalid.l | 30 +-
.../gas/aarch64/sve-reg-diagnostic.l | 6 +-
gas/testsuite/gas/aarch64/tme-invalid.l | 6 +-
23 files changed, 1202 insertions(+), 972 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 616454b584e..fac027ab7b8 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -161,6 +161,32 @@ static aarch64_instruction inst;
static bool parse_operands (char *, const aarch64_opcode *);
static bool programmer_friendly_fixup (aarch64_instruction *);
+/* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
+ data fields contain the following information:
+
+ data[0].i:
+ A mask of register types that would have been acceptable as bare
+ operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
+ is set if a general parsing error occured for an operand (that is,
+ an error not related to registers, and having no error string).
+
+ data[1].i:
+ A mask of register types that would have been acceptable inside
+ a register list. In addition, SEF_IN_REGLIST is set if the
+ operand contained a '{' and if we got to the point of trying
+ to parse a register inside a list.
+
+ data[2].i:
+ The mask associated with the register that was actually seen, or 0
+ if none. A nonzero value describes a register inside a register
+ list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
+ register.
+
+ The idea is that stringless errors from multiple opcode templates can
+ be ORed together to give a summary of the available alternatives. */
+#define SEF_DEFAULT_ERROR (1U << 31)
+#define SEF_IN_REGLIST (1U << 31)
+
/* Diagnostics inline function utilities.
These are lightweight utilities which should only be called by parse_operands
@@ -212,6 +238,14 @@ static inline void
set_default_error (void)
{
set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+ inst.parsing_error.data[0].i = SEF_DEFAULT_ERROR;
+}
+
+static inline void
+set_expected_error (unsigned int flags)
+{
+ set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+ inst.parsing_error.data[0].i = flags;
}
static inline void
@@ -317,17 +351,25 @@ struct reloc_entry
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
| REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ /* Any vector register. */ \
+ MULTI_REG_TYPE(VZ, REG_TYPE(VN) | REG_TYPE(ZN)) \
+ /* An SVE vector or predicate register. */ \
+ MULTI_REG_TYPE(ZP, REG_TYPE(ZN) | REG_TYPE(PN)) \
+ /* Any vector or predicate register. */ \
+ MULTI_REG_TYPE(VZP, REG_TYPE(VN) | REG_TYPE(ZN) | REG_TYPE(PN)) \
/* The whole of ZA or a single tile. */ \
MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
/* A horizontal or vertical slice of a ZA tile. */ \
MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
/* Pseudo type to mark the end of the enumerator sequence. */ \
- BASIC_REG_TYPE(MAX)
+ END_REG_TYPE(MAX)
#undef BASIC_REG_TYPE
#define BASIC_REG_TYPE(T) REG_TYPE_##T,
#undef MULTI_REG_TYPE
#define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
+#undef END_REG_TYPE
+#define END_REG_TYPE(T) BASIC_REG_TYPE(T)
/* Register type enumerators. */
typedef enum aarch64_reg_type_
@@ -342,6 +384,8 @@ typedef enum aarch64_reg_type_
#define REG_TYPE(T) (1 << REG_TYPE_##T)
#undef MULTI_REG_TYPE
#define MULTI_REG_TYPE(T,V) V,
+#undef END_REG_TYPE
+#define END_REG_TYPE(T) 0
/* Structure for a hash table entry for a register. */
typedef struct
@@ -361,84 +405,129 @@ static const unsigned reg_type_masks[] =
#undef BASIC_REG_TYPE
#undef REG_TYPE
#undef MULTI_REG_TYPE
+#undef END_REG_TYPE
#undef AARCH64_REG_TYPES
-/* Diagnostics used when we don't get a register of the expected type.
- Note: this has to synchronized with aarch64_reg_type definitions
- above. */
+/* We expected one of the registers in MASK to be specified. If a register
+ of some kind was specified, SEEN is a mask that contains that register,
+ otherwise it is zero.
+
+ If it is possible to provide a relatively pithy message that describes
+ the error exactly, return a string that does so, reporting the error
+ against "operand %d". Return null otherwise.
+
+ From a QoI perspective, any REG_TYPE_* that is passed as the first
+ argument to set_expected_reg_error should generally have its own message.
+ Providing messages for combinations of such REG_TYPE_*s can be useful if
+ it is possible to summarize the combination in a relatively natural way.
+ On the other hand, it seems better to avoid long lists of unrelated
+ things. */
+
static const char *
-get_reg_expected_msg (aarch64_reg_type reg_type)
+get_reg_expected_msg (unsigned int mask, unsigned int seen)
+{
+ /* First handle messages that use SEEN. */
+ if ((mask & reg_type_masks[REG_TYPE_ZAT])
+ && (seen & reg_type_masks[REG_TYPE_ZATHV]))
+ return N_("expected an unsuffixed ZA tile at operand %d");
+
+ if ((mask & reg_type_masks[REG_TYPE_ZATHV])
+ && (seen & reg_type_masks[REG_TYPE_ZAT]))
+ return N_("missing horizontal or vertical suffix at operand %d");
+
+ if ((mask & reg_type_masks[REG_TYPE_ZA])
+ && (seen & (reg_type_masks[REG_TYPE_ZAT]
+ | reg_type_masks[REG_TYPE_ZATHV])))
+ return N_("expected 'za' rather than a ZA tile at operand %d");
+
+ /* Integer, zero and stack registers. */
+ if (mask == reg_type_masks[REG_TYPE_R_64])
+ return N_("expected a 64-bit integer register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_R_Z])
+ return N_("expected an integer or zero register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_R_SP])
+ return N_("expected an integer or stack pointer register at operand %d");
+
+ /* Floating-point and SIMD registers. */
+ if (mask == reg_type_masks[REG_TYPE_BHSDQ])
+ return N_("expected a scalar SIMD or floating-point register"
+ " at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_VN])
+ return N_("expected an Advanced SIMD vector register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_ZN])
+ return N_("expected an SVE vector register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_PN])
+ return N_("expected an SVE predicate register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_VZ])
+ return N_("expected a vector register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_ZP])
+ return N_("expected an SVE vector or predicate register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_VZP])
+ return N_("expected a vector or predicate register at operand %d");
+
+ /* ZA-related registers. */
+ if (mask == reg_type_masks[REG_TYPE_ZA])
+ return N_("expected a ZA array vector at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_ZA_ZAT])
+ return N_("expected 'za' or a ZA tile at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_ZAT])
+ return N_("expected a ZA tile at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_ZATHV])
+ return N_("expected a ZA tile slice at operand %d");
+
+ /* Integer and vector combos. */
+ if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VN]))
+ return N_("expected an integer register or Advanced SIMD vector register"
+ " at operand %d");
+ if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_ZN]))
+ return N_("expected an integer register or SVE vector register"
+ " at operand %d");
+ if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZ]))
+ return N_("expected an integer or vector register at operand %d");
+ if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_PN]))
+ return N_("expected an integer or predicate register at operand %d");
+ if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZP]))
+ return N_("expected an integer, vector or predicate register"
+ " at operand %d");
+
+ /* SVE and SME combos. */
+ if (mask == (reg_type_masks[REG_TYPE_ZN] | reg_type_masks[REG_TYPE_ZATHV]))
+ return N_("expected an SVE vector register or ZA tile slice"
+ " at operand %d");
+
+ return NULL;
+}
+
+/* Record that we expected a register of type TYPE but didn't see one.
+ REG is the register that we actually saw, or null if we didn't see a
+ recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
+ contents of a register list, otherwise it is zero. */
+
+static inline void
+set_expected_reg_error (aarch64_reg_type type, const reg_entry *reg,
+ unsigned int flags)
{
- const char *msg;
+ assert (flags == 0 || flags == SEF_IN_REGLIST);
+ set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+ if (flags & SEF_IN_REGLIST)
+ inst.parsing_error.data[1].i = reg_type_masks[type] | flags;
+ else
+ inst.parsing_error.data[0].i = reg_type_masks[type];
+ if (reg)
+ inst.parsing_error.data[2].i = reg_type_masks[reg->type];
+}
- switch (reg_type)
- {
- case REG_TYPE_R_32:
- msg = N_("integer 32-bit register expected");
- break;
- case REG_TYPE_R_64:
- msg = N_("integer 64-bit register expected");
- break;
- case REG_TYPE_R_N:
- msg = N_("integer register expected");
- break;
- case REG_TYPE_R64_SP:
- msg = N_("64-bit integer or SP register expected");
- break;
- case REG_TYPE_SVE_BASE:
- msg = N_("base register expected");
- break;
- case REG_TYPE_R_Z:
- msg = N_("integer or zero register expected");
- break;
- case REG_TYPE_SVE_OFFSET:
- msg = N_("offset register expected");
- break;
- case REG_TYPE_R_SP:
- msg = N_("integer or SP register expected");
- break;
- case REG_TYPE_R_Z_SP:
- msg = N_("integer, zero or SP register expected");
- break;
- case REG_TYPE_FP_B:
- msg = N_("8-bit SIMD scalar register expected");
- break;
- case REG_TYPE_FP_H:
- msg = N_("16-bit SIMD scalar or floating-point half precision "
- "register expected");
- break;
- case REG_TYPE_FP_S:
- msg = N_("32-bit SIMD scalar or floating-point single precision "
- "register expected");
- break;
- case REG_TYPE_FP_D:
- msg = N_("64-bit SIMD scalar or floating-point double precision "
- "register expected");
- break;
- case REG_TYPE_FP_Q:
- msg = N_("128-bit SIMD scalar or floating-point quad precision "
- "register expected");
- break;
- case REG_TYPE_R_Z_BHSDQ_V:
- case REG_TYPE_R_Z_SP_BHSDQ_VZP:
- msg = N_("register expected");
- break;
- case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
- msg = N_("SIMD scalar or floating-point register expected");
- break;
- case REG_TYPE_VN: /* any V reg */
- msg = N_("vector register expected");
- break;
- case REG_TYPE_ZN:
- msg = N_("SVE vector register expected");
- break;
- case REG_TYPE_PN:
- msg = N_("SVE predicate register expected");
- break;
- default:
- as_fatal (_("invalid register type %d"), reg_type);
- }
- return msg;
+/* Record that we expected a register list containing registers of type TYPE,
+ but didn't see the opening '{'. If we saw a register instead, REG is the
+ register that we saw, otherwise it is null. */
+
+static inline void
+set_expected_reglist_error (aarch64_reg_type type, const reg_entry *reg)
+{
+ set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+ inst.parsing_error.data[1].i = reg_type_masks[type];
+ if (reg)
+ inst.parsing_error.data[2].i = reg_type_masks[reg->type];
}
/* Some well known registers that we refer to directly elsewhere. */
@@ -1092,6 +1181,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
struct vector_type_el atype;
struct vector_type_el parsetype;
bool is_typed_vecreg = false;
+ unsigned int err_flags = (flags & PTR_IN_REGLIST) ? SEF_IN_REGLIST : 0;
atype.defined = 0;
atype.type = NT_invtype;
@@ -1108,7 +1198,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
else if (flags & PTR_GOOD_MATCH)
set_fatal_syntax_error (NULL);
else
- set_default_error ();
+ set_expected_reg_error (type, reg, err_flags);
return NULL;
}
@@ -1118,7 +1208,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
if (flags & PTR_GOOD_MATCH)
set_fatal_syntax_error (NULL);
else
- set_default_error ();
+ set_expected_reg_error (type, reg, err_flags);
return NULL;
}
type = reg->type;
@@ -1275,7 +1365,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
if (*str != '{')
{
- set_syntax_error (_("expecting {"));
+ set_expected_reglist_error (type, parse_reg (&str));
return PARSE_FAIL;
}
str++;
@@ -3612,7 +3702,7 @@ parse_shifter_operand (char **str, aarch64_opnd_info *operand,
if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
{
- set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
+ set_expected_reg_error (REG_TYPE_R_Z, reg, 0);
return false;
}
@@ -4110,7 +4200,7 @@ parse_x0_to_x30 (char **str, aarch64_opnd_info *operand)
const reg_entry *reg = parse_reg (str);
if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R_64))
{
- set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
+ set_expected_reg_error (REG_TYPE_R_64, reg, 0);
return false;
}
operand->reg.regno = reg->number;
@@ -4509,7 +4599,7 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
{
if (!skip_past_char (str, '{'))
{
- set_syntax_error (_("expected '{'"));
+ set_expected_reglist_error (REG_TYPE_ZATHV, parse_reg (str));
return false;
}
@@ -4783,17 +4873,14 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
#define po_reg_or_fail(regtype) do { \
reg = aarch64_reg_parse (&str, regtype, NULL); \
if (!reg) \
- { \
- set_default_error (); \
- goto failure; \
- } \
+ goto failure; \
} while (0)
#define po_int_fp_reg_or_fail(reg_type) do { \
reg = parse_reg (&str); \
if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
{ \
- set_default_error (); \
+ set_expected_reg_error (reg_type, reg, 0); \
goto failure; \
} \
info->reg.regno = reg->number; \
@@ -5389,6 +5476,64 @@ output_info (const char *format, ...)
(void) putc ('\n', stderr);
}
+/* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
+ relates to registers or register lists. If so, return a string that
+ reports the error against "operand %d", otherwise return null. */
+
+static const char *
+get_reg_error_message (const aarch64_operand_error *detail)
+{
+ /* Handle the case where we found a register that was expected
+ to be in a register list outside of a register list. */
+ if ((detail->data[1].i & detail->data[2].i) != 0
+ && (detail->data[1].i & SEF_IN_REGLIST) == 0)
+ return _("missing braces at operand %d");
+
+ /* If some opcodes expected a register, and we found a register,
+ complain about the difference. */
+ if (detail->data[2].i)
+ {
+ unsigned int expected = (detail->data[1].i & SEF_IN_REGLIST
+ ? detail->data[1].i & ~SEF_IN_REGLIST
+ : detail->data[0].i & ~SEF_DEFAULT_ERROR);
+ const char *msg = get_reg_expected_msg (expected, detail->data[2].i);
+ if (!msg)
+ msg = N_("unexpected register type at operand %d");
+ return msg;
+ }
+
+ /* Handle the case where we got to the point of trying to parse a
+ register within a register list, but didn't find a known register. */
+ if (detail->data[1].i & SEF_IN_REGLIST)
+ {
+ unsigned int expected = detail->data[1].i & ~SEF_IN_REGLIST;
+ const char *msg = get_reg_expected_msg (expected, 0);
+ if (!msg)
+ msg = _("invalid register list at operand %d");
+ return msg;
+ }
+
+ /* Punt if register-related problems weren't the only errors. */
+ if (detail->data[0].i & SEF_DEFAULT_ERROR)
+ return NULL;
+
+ /* Handle the case where the only acceptable things are registers. */
+ if (detail->data[1].i == 0)
+ {
+ const char *msg = get_reg_expected_msg (detail->data[0].i, 0);
+ if (!msg)
+ msg = _("expected a register at operand %d");
+ return msg;
+ }
+
+ /* Handle the case where the only acceptable things are register lists,
+ and there was no opening '{'. */
+ if (detail->data[0].i == 0)
+ return _("expected '{' at operand %d");
+
+ return _("expected a register or register list at operand %d");
+}
+
/* Output one operand error record. */
static void
@@ -5402,6 +5547,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
typedef void (*handler_t)(const char *format, ...);
handler_t handler = detail->non_fatal ? as_warn : as_bad;
+ const char *msg = detail->error;
switch (detail->kind)
{
@@ -5422,18 +5568,31 @@ output_operand_error_record (const operand_error_record *record, char *str)
break;
case AARCH64_OPDE_SYNTAX_ERROR:
+ if (!msg && idx >= 0)
+ {
+ msg = get_reg_error_message (detail);
+ if (msg)
+ {
+ char *full_msg = xasprintf (msg, idx + 1);
+ handler (_("%s -- `%s'"), full_msg, str);
+ free (full_msg);
+ break;
+ }
+ }
+ /* Fall through. */
+
case AARCH64_OPDE_RECOVERABLE:
case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
case AARCH64_OPDE_OTHER_ERROR:
/* Use the prepared error message if there is, otherwise use the
operand description string to describe the error. */
- if (detail->error != NULL)
+ if (msg != NULL)
{
if (idx < 0)
- handler (_("%s -- `%s'"), detail->error, str);
+ handler (_("%s -- `%s'"), msg, str);
else
handler (_("%s at operand %d -- `%s'"),
- detail->error, idx + 1, str);
+ msg, idx + 1, str);
}
else
{
@@ -5554,11 +5713,11 @@ output_operand_error_record (const operand_error_record *record, char *str)
case AARCH64_OPDE_OUT_OF_RANGE:
if (detail->data[0].i != detail->data[1].i)
handler (_("%s out of range %d to %d at operand %d -- `%s'"),
- detail->error ? detail->error : _("immediate value"),
+ msg ? msg : _("immediate value"),
detail->data[0].i, detail->data[1].i, idx + 1, str);
else
handler (_("%s must be %d at operand %d -- `%s'"),
- detail->error ? detail->error : _("immediate value"),
+ msg ? msg : _("immediate value"),
detail->data[0].i, idx + 1, str);
break;
@@ -5600,8 +5759,6 @@ output_operand_error_record (const operand_error_record *record, char *str)
static void
output_operand_error_report (char *str, bool non_fatal_only)
{
- int largest_error_pos;
- const char *msg = NULL;
enum aarch64_operand_error_kind kind;
operand_error_record *curr;
operand_error_record *head = operand_error_report.head;
@@ -5633,7 +5790,17 @@ output_operand_error_report (char *str, bool non_fatal_only)
for (curr = head; curr != NULL; curr = curr->next)
{
gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
- DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
+ if (curr->detail.kind == AARCH64_OPDE_SYNTAX_ERROR)
+ {
+ DEBUG_TRACE ("\t%s [%x, %x, %x]",
+ operand_mismatch_kind_names[curr->detail.kind],
+ curr->detail.data[0].i, curr->detail.data[1].i,
+ curr->detail.data[2].i);
+ }
+ else
+ {
+ DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
+ }
if (operand_error_higher_severity_p (curr->detail.kind, kind)
&& (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
kind = curr->detail.kind;
@@ -5642,7 +5809,6 @@ output_operand_error_report (char *str, bool non_fatal_only)
gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
/* Pick up one of errors of KIND to report. */
- largest_error_pos = -2; /* Index can be -1 which means unknown index. */
for (curr = head; curr != NULL; curr = curr->next)
{
/* If we don't want to print non-fatal errors then don't consider them
@@ -5654,13 +5820,23 @@ output_operand_error_report (char *str, bool non_fatal_only)
mismatching operand index. In the case of multiple errors with
the equally highest operand index, pick up the first one or the
first one with non-NULL error message. */
- if (curr->detail.index > largest_error_pos
- || (curr->detail.index == largest_error_pos && msg == NULL
- && curr->detail.error != NULL))
+ if (!record || curr->detail.index > record->detail.index)
+ record = curr;
+ else if (curr->detail.index == record->detail.index
+ && !record->detail.error)
{
- largest_error_pos = curr->detail.index;
- record = curr;
- msg = record->detail.error;
+ if (curr->detail.error)
+ record = curr;
+ else if (kind == AARCH64_OPDE_SYNTAX_ERROR)
+ {
+ record->detail.data[0].i |= curr->detail.data[0].i;
+ record->detail.data[1].i |= curr->detail.data[1].i;
+ record->detail.data[2].i |= curr->detail.data[2].i;
+ DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
+ operand_mismatch_kind_names[kind],
+ curr->detail.data[0].i, curr->detail.data[1].i,
+ curr->detail.data[2].i);
+ }
}
}
@@ -5675,9 +5851,9 @@ output_operand_error_report (char *str, bool non_fatal_only)
if (non_fatal_only && !record)
return;
- gas_assert (largest_error_pos != -2 && record != NULL);
+ gas_assert (record);
DEBUG_TRACE ("Pick up error kind %s to report",
- operand_mismatch_kind_names[record->detail.kind]);
+ operand_mismatch_kind_names[kind]);
/* Output. */
output_operand_error_record (record, str);
@@ -6299,10 +6475,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
vector_reg:
reg = aarch64_reg_parse (&str, reg_type, &vectype);
if (!reg)
- {
- first_error (_(get_reg_expected_msg (reg_type)));
- goto failure;
- }
+ goto failure;
if (vectype.defined & NTA_HASINDEX)
goto failure;
@@ -6325,10 +6498,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_VnD1:
reg = aarch64_reg_parse (&str, REG_TYPE_VN, &vectype);
if (!reg)
- {
- set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
- goto failure;
- }
+ goto failure;
if (vectype.type != NT_d || vectype.index != 1)
{
set_fatal_syntax_error
@@ -6361,10 +6531,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
vector_reg_index:
reg = aarch64_reg_parse (&str, reg_type, &vectype);
if (!reg)
- {
- first_error (_(get_reg_expected_msg (reg_type)));
- goto failure;
- }
+ goto failure;
if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
goto failure;
@@ -6392,10 +6559,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
{
reg = aarch64_reg_parse (&str, reg_type, &vectype);
if (!reg)
- {
- first_error (_(get_reg_expected_msg (reg_type)));
- goto failure;
- }
+ goto failure;
info->reglist.first_regno = reg->number;
info->reglist.num_regs = 1;
}
diff --git a/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l b/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l
index d31a0b0b27e..066123d4475 100644
--- a/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l
+++ b/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l
@@ -1,9 +1,9 @@
[^:]+: Assembler messages:
-[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h X0,Q0,V1.2D'
+[^:]+:[0-9]+: Error: expected a scalar SIMD or floating-point register at operand 1 -- `sha512h X0,Q0,V1.2D'
[^:]+:[0-9]+: Error: operand mismatch -- `sha512h Q0,Q1,V2.16B'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512h q0, q1, v2.2d
-[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h2 X0,Q0,V1.2D'
+[^:]+:[0-9]+: Error: expected a scalar SIMD or floating-point register at operand 1 -- `sha512h2 X0,Q0,V1.2D'
[^:]+:[0-9]+: Error: operand mismatch -- `sha512h2 Q0,Q1,V2.16B'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512h2 q0, q1, v2.2d
@@ -11,7 +11,7 @@
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512su0 v1.2d, v2.2d
[^:]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `sha512su0 V0,V2.2D'
-[^:]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sha512su1 X0,X1,X2'
+[^:]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 1 -- `sha512su1 X0,X1,X2'
[^:]+:[0-9]+: Error: operand mismatch -- `sha512su1 V1.2D,V2.16B,V2.2D'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512su1 v1.2d, v2.2d, v2.2d
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 99359891c5f..52365319283 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -51,7 +51,7 @@
[^:]*:53: Error: invalid floating-point constant at operand 2 -- `fmov s3,1.01'
[^:]*:54: Error: invalid floating-point constant at operand 2 -- `fmov d3,1.01'
[^:]*:55: Error: immediate zero expected at operand 2 -- `fcmp d0,#1.0'
-[^:]*:56: Error: operand 2 must be a floating-point register -- `fcmp d0,x0'
+[^:]*:56: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fcmp d0,x0'
[^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
[^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
@@ -59,7 +59,7 @@
[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
[^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl#64'
-[^:]*:64: Error: operand 1 must be an integer register -- `adds sp,sp,2134,lsl#12'
+[^:]*:64: Error: expected an integer or zero register at operand 1 -- `adds sp,sp,2134,lsl#12'
[^:]*:65: Error: the optional immediate offset can only be 0 at operand 2 -- `ldxrb w2,\[x0,#1\]'
[^:]*:66: Error: invalid addressing mode at operand 2 -- `ldrb w0,x1,x2,sxtx'
[^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
@@ -98,11 +98,11 @@
[^:]*:100: Error: operand 3 must be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
[^:]*:101: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
[^:]*:102: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
-[^:]*:106: Error: operand 1 must be an integer register -- `ret kk'
+[^:]*:106: Error: expected an integer or zero register at operand 1 -- `ret kk'
[^:]*:107: Error: immediate operand required at operand 1 -- `clrex x0'
[^:]*:108: Error: immediate operand required at operand 1 -- `clrex w0'
[^:]*:109: Error: constant expression required at operand 1 -- `clrex kk'
-[^:]*:110: Error: operand 5 must be an integer register -- `sys #0,c0,c0,#0,kk'
+[^:]*:110: Error: expected an integer or zero register at operand 5 -- `sys #0,c0,c0,#0,kk'
[^:]*:111: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys #0,c0,c0,#0,'
[^:]*:113: Error: selected processor does not support `casp w0,w1,w2,w3,\[x4\]'
[^:]*:116: Warning: unpredictable load of register pair -- `ldp x0,x0,\[sp\]'
@@ -186,3 +186,21 @@
[^:]*:317: Error: expected a base register at operand 2 -- `ldr x0,\[1\]'
[^:]*:318: Error: expected a base register at operand 2 -- `ldr x0,\[\]'
[^:]*:319: Error: expected a base register at operand 2 -- `ldr x0,\[,xzr\]'
+[^:]*:321: Error: expected a vector or predicate register at operand 1 -- `zip2 x1'
+[^:]*:322: Error: expected an integer register or SVE vector register at operand 1 -- `uxtw d2'
+[^:]*:323: Error: unexpected register type at operand 1 -- `usra x3'
+[^:]*:324: Error: unexpected register type at operand 1 -- `ushr z4'
+[^:]*:325: Error: expected an integer register or Advanced SIMD vector register at operand 1 -- `umull z5'
+[^:]*:326: Error: expected an integer or vector register at operand 1 -- `umin d6'
+[^:]*:327: Error: unexpected register type at operand 1 -- `stur v7'
+[^:]*:328: Error: expected an SVE vector or predicate register at operand 1 -- `sel v8'
+[^:]*:329: Error: expected an integer, vector or predicate register at operand 1 -- `orn d9'
+[^:]*:330: Error: unexpected register type at operand 1 -- `frecpx v10'
+[^:]*:331: Error: expected an integer or predicate register at operand 1 -- `bics z11'
+[^:]*:332: Error: unexpected register type at operand 1 -- `rev wsp'
+[^:]*:333: Error: unexpected register type at operand 1 -- `orr b12'
+[^:]*:334: Error: unexpected register type at operand 1 -- `neg p13'
+[^:]*:335: Error: unexpected register type at operand 1 -- `fcvtpu za14h'
+[^:]*:336: Error: unexpected register type at operand 1 -- `fcmlt z15'
+[^:]*:337: Error: unexpected register type at operand 1 -- `clastb sp'
+[^:]*:338: Error: unexpected register type at operand 1 -- `ldr sp'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index 014e0abe332..5f3c7791180 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -317,3 +317,22 @@
ldr x0, [1]
ldr x0, []
ldr x0, [,xzr]
+
+ zip2 x1
+ uxtw d2
+ usra x3
+ ushr z4
+ umull z5
+ umin d6
+ stur v7
+ sel v8
+ orn d9
+ frecpx v10
+ bics z11
+ rev wsp
+ orr b12
+ neg p13
+ fcvtpu za14h
+ fcmlt z15
+ clastb sp
+ ldr sp
diff --git a/gas/testsuite/gas/aarch64/illegal-bfloat16.l b/gas/testsuite/gas/aarch64/illegal-bfloat16.l
index c20f132de38..e513c3cc64c 100644
--- a/gas/testsuite/gas/aarch64/illegal-bfloat16.l
+++ b/gas/testsuite/gas/aarch64/illegal-bfloat16.l
@@ -25,28 +25,28 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlalt z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlalb z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot v0\.2s,v1\.4h,v2\.2s\[3\]'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -61,18 +61,18 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.8h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.8h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.4h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.8h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v0\.h\[8\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v16\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -87,8 +87,8 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v0\.h\[8\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v16\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt h0,h1'
[^ :]+:[0-9]+: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
index 7a38ddca5a7..8431dc3b3a9 100644
--- a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
@@ -1,8 +1,8 @@
[^:]+: Assembler messages:
-[^:]+:8: Error: operand 1 must be an integer register -- `fjcvtzs d0,d1'
-[^:]+:9: Error: operand 1 must be an integer register -- `fjcvtzs s0,d1'
+[^:]+:8: Error: expected an integer or zero register at operand 1 -- `fjcvtzs d0,d1'
+[^:]+:9: Error: expected an integer or zero register at operand 1 -- `fjcvtzs s0,d1'
[^:]+:10: Error: operand mismatch -- `fjcvtzs x0,d1'
[^:]+:11: Error: operand mismatch -- `fjcvtzs w0,s1'
[^:]+:12: Error: operand mismatch -- `fjcvtzs w0,h1'
[^:]+:13: Error: operand mismatch -- `fjcvtzs w0,q1'
-[^:]+:14: Error: operand 2 must be a floating-point register -- `fjcvtzs w0,x1'
+[^:]+:14: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fjcvtzs w0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 7e48f0a71e9..476c345d366 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -18,38 +18,38 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldgm x4,\[x5,#16\]!'
[^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `stgm x2,\[x3,#16\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `stgm x4,\[x5,#16\]!'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
-[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
-[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `gmi x1,x2,sp'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `gmi sp,x2,x3'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `gmi x1,xzr,x3'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `addg xzr,x2,#0,#0'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subg x1,xzr,#0,#0'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `subp sp,x1,x2'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subp x1,xzr,x2'
-[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subp x1,x2,xzr'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `subps sp,x1,x2'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subps x1,xzr,x2'
-[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `irg xzr,x2,x3'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `irg x1,xzr,x3'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 3 -- `irg x1,x2,sp'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 3 -- `gmi x1,x2,sp'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gmi sp,x2,x3'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `gmi x1,xzr,x3'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `addg xzr,x2,#0,#0'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subg x1,xzr,#0,#0'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subp sp,x1,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subp x1,xzr,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subp x1,x2,xzr'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subps sp,x1,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subps x1,xzr,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subps x1,x2,xzr'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `cmpp xzr,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `cmpp x2,xzr'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stg x2,\[xzr,#0\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `st2g x2,\[xzr,#0\]!'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzg x2,\[xzr\],#0'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stz2g x2,\[xzr,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
-[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stg xzr,\[x2,#0\]'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `st2g xzr,\[x2,#0\]!'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stzg xzr,\[x2\],#0'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stz2g xzr,\[x2,#0\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stgp sp,x2,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 2 -- `stgp x1,sp,\[x3\]'
[^:]*:[0-9]+: Error: invalid base register at operand 3 -- `stgp x0,x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldg x0,\[xzr,#16\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzgm x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stzgm sp,\[x3\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldgm x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `ldgm sp,\[x3\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stgm x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stgm sp,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 13df21b4a4e..d41f6f23ba5 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -8,35 +8,35 @@
[^ :]+:[0-9]+: Info: adclb z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: adclb z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclb z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `adclb z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `adclb z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `adclb z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `adclt z0\.d,z0\.s,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: adclt z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: adclt z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclt z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `adclt z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `adclt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `adclt z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `addhnb z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: addhnb z0\.b, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: addhnb z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: addhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `addhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `addhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `addhnb z0\.b,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `addhnt z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: addhnt z0\.b, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: addhnt z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: addhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `addhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `addhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `addhnt z0\.b,z0\.h,z32\.h'
[^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `addp z0\.b,p0/m,z0\.b,z1\.b'
[^ :]+:[0-9]+: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `addp z0\.d,p1/m,z0\.d,z1\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `addp z0\.b,p0/z,z0\.b,z0\.b'
@@ -47,35 +47,35 @@
[^ :]+:[0-9]+: Info: addp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: addp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `addp z0\.h,p0/m,z1\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `addp z0\.s,p0/m,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `addp z32\.s,p0/m,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `addp z0\.s,p0/m,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aesd z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aesd z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aesd z0\.b,z0\.b,z32\.b'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aese z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aese z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aese z0\.b,z0\.b,z32\.b'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aesimc z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesimc z32\.b,z0\.b'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aesmc z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesmc z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesmc z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bcax z0\.d,z1\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.d,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -83,9 +83,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.h,z0\.d,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bcax z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl z0\.d,z1\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.d,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -93,9 +93,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.h,z0\.d,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bsl z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bsl z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bsl z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bsl z0\.d,z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl1n z0\.d,z1\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.d,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -103,9 +103,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.h,z0\.d,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bsl1n z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl1n z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bsl1n z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bsl1n z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bsl1n z0\.d,z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl2n z0\.d,z1\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.d,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -113,9 +113,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.h,z0\.d,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bsl2n z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl2n z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bsl2n z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bsl2n z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bsl2n z0\.d,z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bdep z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bdep z0\.b, z0\.b, z0\.b
@@ -123,9 +123,9 @@
[^ :]+:[0-9]+: Info: bdep z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: bdep z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: bdep z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bdep z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bdep z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bdep z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bdep z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bdep z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bdep z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bext z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bext z0\.b, z0\.b, z0\.b
@@ -133,9 +133,9 @@
[^ :]+:[0-9]+: Info: bext z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: bext z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: bext z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bext z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bext z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bext z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bext z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bext z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bext z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `bgrp z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bgrp z0\.b, z0\.b, z0\.b
@@ -143,9 +143,9 @@
[^ :]+:[0-9]+: Info: bgrp z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: bgrp z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: bgrp z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bgrp z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bgrp z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bgrp z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bgrp z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bgrp z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bgrp z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `cadd z18\.b,z17\.b,z21\.b,#90'
[^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `cadd z0\.b,z0\.b,z0\.b,#91'
[^ :]+:[0-9]+: Error: operand mismatch -- `cadd z0\.b,z0\.h,z0\.h,#90'
@@ -160,19 +160,19 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.d,z0\.b\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: cdot z0\.d, z0\.h, z0\.h\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cdot z0\.s,z0\.b,z8\.b\[0\],#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.d,z0\.h,z0\.h\[0\],#1'
[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.d,z0\.d,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: cdot z0\.d, z0\.h, z0\.h\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.d,z0\.h,z0\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.d,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.d,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.d,z32\.h,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cdot z0\.d,z0\.h,z16\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cdot z0\.s,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.s,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.s,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `cdot z0\.s,z0\.b,z32\.b,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.b,z0\.s,#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: cdot z0\.s, z0\.b, z0\.b, #0
@@ -184,25 +184,25 @@
[^ :]+:[0-9]+: Info: cdot z0\.d, z0\.h, z0\.h, #0
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: cdot z0\.s, z0\.b, z0\.b, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.h,z0\.h,z0\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.h,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.h,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cmla z0\.h,z32\.h,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cmla z0\.h,z0\.h,z8\.h\[0\],#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.h,z0\.h,z0\.d\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: cmla z0\.h, z0\.h, z0\.h\[0\], #0
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cmla z0\.h,z0\.h,z0\.h\[4\],#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.h,z0\.h,z0\.h\[0\],#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.s,z0\.s,z0\.s\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.s,z32\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.s,z0\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cmla z0\.s,z32\.s,z0\.s\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cmla z0\.s,z0\.s,z16\.s\[0\],#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.s,z0\.s,z0\.d\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: cmla z0\.h, z0\.h, z0\.h\[0\], #0
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `cmla z0\.s,z0\.s,z0\.s\[2\],#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.s,z0\.s,z0\.s\[0\],#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.b,z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.b,z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cmla z0\.b,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cmla z0\.b,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `cmla z0\.b,z0\.b,z32\.b,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.b,z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: cmla z0\.b, z0\.b, z0\.b, #0
@@ -225,9 +225,9 @@
[^ :]+:[0-9]+: Info: eorbt z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: eorbt z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: eorbt z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eorbt z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eorbt z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eorbt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `eorbt z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `eorbt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `eorbt z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `eortb z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: eortb z0\.b, z0\.b, z0\.b
@@ -235,9 +235,9 @@
[^ :]+:[0-9]+: Info: eortb z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: eortb z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: eortb z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eortb z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eortb z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eortb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `eortb z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `eortb z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `eortb z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `ext z0\.b,{,},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
@@ -250,16 +250,16 @@
[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b},#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ext z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `ext z32\.b,{z0\.b,z1\.b},#0'
[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ext z0\.b,{z32\.b,z33\.b},#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `faddp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `faddp z0\.h,p0/m,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `faddp z0\.h,p0/m,z1\.h,z0\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `faddp z0\.h,p0/z,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -274,18 +274,18 @@
[^ :]+:[0-9]+: Info: faddp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: faddp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtlt z0\.s,p0/m,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.s,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtlt z32\.s,p0/m,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.s,p8/m,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.s,p0/m,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtlt z0\.s,p0/m,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/z,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.d,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtlt z32\.d,p0/m,z0\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.d,p8/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.d,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtlt z0\.d,p0/m,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/m,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
@@ -293,27 +293,27 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtnt z0\.h,p0/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.h,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.h,p0/m,z0\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.h,p8/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.h,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.h,p0/m,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/m,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/z,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.s,p8/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.s,p0/m,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtx z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtx z32\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtx z0\.s,p8/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtx z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtx z0\.s,p0/m,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtx z0\.s, p0/m, z0\.d
@@ -322,9 +322,9 @@
[^ :]+:[0-9]+: Info: fcvtx z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtx z0\.s,p0/m,z2\.d'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtxnt z0\.s,p0/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtxnt z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtxnt z32\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtxnt z0\.s,p8/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtxnt z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtxnt z0\.s,p0/m,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtxnt z0\.s, p0/m, z0\.d
@@ -349,9 +349,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: flogb z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: flogb z0\.d, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `flogb z32\.h,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `flogb z32\.h,p0/m,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `flogb z0\.h,p8/m,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `flogb z0\.h,p0/m,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `flogb z0\.h,p0/m,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmaxnmp z0\.b,p0/m,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmaxnmp z0\.h, p0/m, z0\.h, z0\.h
@@ -365,9 +365,9 @@
[^ :]+:[0-9]+: Info: fmaxnmp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fmaxnmp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxnmp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxnmp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmaxnmp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxnmp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxnmp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fmaxnmp z0\.h,p0/m,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmaxp z0\.b,p0/m,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmaxp z0\.h, p0/m, z0\.h, z0\.h
@@ -381,9 +381,9 @@
[^ :]+:[0-9]+: Info: fmaxp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fmaxp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmaxp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fmaxp z0\.h,p0/m,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fminnmp z0\.b,p0/m,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fminnmp z0\.h, p0/m, z0\.h, z0\.h
@@ -397,9 +397,9 @@
[^ :]+:[0-9]+: Info: fminnmp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fminnmp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminnmp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminnmp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fminnmp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminnmp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminnmp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fminnmp z0\.h,p0/m,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fminp z0\.b,p0/m,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fminp z0\.h, p0/m, z0\.h, z0\.h
@@ -413,65 +413,65 @@
[^ :]+:[0-9]+: Info: fminp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fminp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fminp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fminp z0\.h,p0/m,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslb z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslb z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlslb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlslb z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.s,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlslb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslt z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslt z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlslt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlslt z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.s,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlslt z0\.s, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histcnt z32\.s,p0/z,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `histcnt z32\.s,p0/z,z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `histcnt z0\.s,p8/z,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histcnt z0\.s,p0/z,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `histcnt z0\.s,p0/z,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `histcnt z0\.s,p0/z,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `histcnt z0\.s,p0/z,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `histcnt z0\.s,p0/m,z0\.s,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: histcnt z0\.s, p0/z, z0\.s, z0\.s
@@ -482,9 +482,9 @@
[^ :]+:[0-9]+: Info: histcnt z0\.s, p0/z, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: histcnt z0\.d, p0/z, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histseg z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `histseg z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histseg z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `histseg z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `histseg z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `histseg z0\.b,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: histseg z0\.b, z0\.b, z0\.b
@@ -492,7 +492,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -509,7 +509,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/m,\[z0\.s\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
@@ -519,7 +519,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -539,7 +539,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -550,7 +550,7 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
@@ -562,7 +562,7 @@
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -575,7 +575,7 @@
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -588,7 +588,7 @@
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -599,7 +599,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -610,7 +610,7 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
@@ -621,10 +621,10 @@
[^ :]+:[0-9]+: Info: match p0\.b, p0/z, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: match p0\.h, p0/z, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `match p16\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `match p16\.b,p0/z,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `match p0\.b,p8/z,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `match p0\.b,p0/z,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `match p0\.b,p0/z,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `match p0\.b,p0/z,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `match p0\.b,p0/z,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mla z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -632,8 +632,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mla z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.s,z0\.s\[0\]'
@@ -642,8 +642,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mla z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.d,z0\.d\[0\]'
@@ -652,8 +652,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mla z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mls z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.h,z0\.h\[0\]'
@@ -662,8 +662,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mls z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.s,z0\.s\[0\]'
@@ -672,8 +672,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mls z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.d,z0\.d\[0\]'
@@ -682,8 +682,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mls z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mul z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.h,z0\.h\[0\]'
@@ -692,8 +692,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mul z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.s,z0\.s\[0\]'
@@ -702,8 +702,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mul z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.d,z0\.d\[0\]'
@@ -712,8 +712,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mul z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -722,8 +722,8 @@
[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: mul z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: mul z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.b,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `nmatch p0\.h,p0/z,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: nmatch p0\.b, p0/z, z0\.b, z0\.b
@@ -734,10 +734,10 @@
[^ :]+:[0-9]+: Info: nmatch p0\.b, p0/z, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: nmatch p0\.h, p0/z, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `nmatch p16\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `nmatch p16\.b,p0/z,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `nmatch p0\.b,p8/z,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `nmatch p0\.b,p0/z,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `nmatch p0\.b,p0/z,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `nmatch p0\.b,p0/z,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `nmatch p0\.b,p0/z,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `nbsl z0\.d,z1\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `nbsl z0\.d,z0\.d,z0\.h,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -748,30 +748,30 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `pmul z0\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: pmul z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmul z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmul z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmul z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.q,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.q,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.q,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `pmul z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmul z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmul z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullb z32\.q,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullb z0\.q,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullb z0\.q,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.q,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.q,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.q,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullt z32\.q,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullt z0\.q,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullt z0\.q,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d
@@ -781,26 +781,26 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: raddhnb z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: raddhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `raddhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `raddhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `raddhnb z0\.b,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `raddhnt z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: raddhnt z0\.b, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: raddhnt z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: raddhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnt z0\.b,z0\.h,z32\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `rax1 z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rax1 z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rax1 z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `raddhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `raddhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `raddhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `rax1 z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rax1 z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `rax1 z0\.d,z0\.d,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `rax1 z0\.d,z0\.d,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: rax1 z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rshrnb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `rshrnb z0\.h,z0\.h,#8'
@@ -814,8 +814,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `rshrnt z0\.b,z1\.h,#8'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rshrnt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `rshrnt z0\.h,z0\.h,#8'
@@ -834,18 +834,18 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: rsubhnb z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: rsubhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rsubhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rsubhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `rsubhnb z0\.b,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `rsubhnt z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: rsubhnt z0\.b, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: rsubhnt z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: rsubhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rsubhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rsubhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `rsubhnt z0\.b,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `saba z0\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: saba z0\.b, z0\.b, z0\.b
@@ -853,45 +853,45 @@
[^ :]+:[0-9]+: Info: saba z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: saba z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: saba z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saba z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saba z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saba z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `saba z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saba z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saba z0\.b,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sabalb z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sabalb z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sabalb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sabalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabalb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sabalt z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sabalt z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sabalt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sabalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabalt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sabdlb z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sabdlb z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sabdlb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sabdlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabdlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabdlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabdlb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sabdlt z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sabdlt z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sabdlt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sabdlt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabdlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabdlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabdlt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sadalp z0\.b,p0/m,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sadalp z0\.h, p0/m, z0\.b
@@ -905,74 +905,74 @@
[^ :]+:[0-9]+: Info: sadalp z0\.s, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sadalp z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sadalp z0\.h,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sadalp z32\.h,p0/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sadalp z0\.h,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sadalp z32\.h,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sadalp z0\.h,p0/m,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `saddlb z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: saddlb z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: saddlb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: saddlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddlb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `saddlbt z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: saddlbt z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: saddlbt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: saddlbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddlbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddlbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddlbt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `saddlt z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: saddlt z0\.h, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: saddlt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: saddlt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddlt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `saddwb z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: saddwb z0\.h, z0\.h, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: saddwb z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: saddwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddwb z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `saddwt z0\.b,z0\.h,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: saddwt z0\.h, z0\.h, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: saddwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: saddwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddwt z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sbclb z0\.d,z0\.s,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sbclb z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sbclb z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclb z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclb z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sbclb z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sbclb z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sbclb z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `sbclt z0\.d,z0\.s,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sbclt z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sbclt z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclt z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclt z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sbclt z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sbclt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sbclt z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shadd z0\.b,p0/m,z1\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `shadd z32\.b,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shadd z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `shadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `shadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `shadd z0\.h,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: shadd z0\.b, p0/m, z0\.b, z0\.b
@@ -987,8 +987,8 @@
[^ :]+:[0-9]+: Info: shadd z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: shadd z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: shadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `shrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `shrnb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `shrnb z0\.h,z0\.h,#8'
@@ -1002,8 +1002,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `shrnt z0\.b,z1\.h,#8'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `shrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `shrnt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `shrnt z0\.h,z0\.h,#8'
@@ -1017,10 +1017,10 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsub z0\.b,p0/m,z1\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `shsub z32\.b,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsub z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `shsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `shsub z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `shsub z0\.h,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: shsub z0\.b, p0/m, z0\.b, z0\.b
@@ -1036,10 +1036,10 @@
[^ :]+:[0-9]+: Info: shsub z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: shsub z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsubr z0\.b,p0/m,z1\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `shsubr z32\.b,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsubr z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `shsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `shsubr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `shsubr z0\.h,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: shsubr z0\.b, p0/m, z0\.b, z0\.b
@@ -1061,23 +1061,23 @@
[^ :]+:[0-9]+: Info: sli z0\.h, z0\.h, #0
[^ :]+:[0-9]+: Info: sli z0\.s, z0\.s, #0
[^ :]+:[0-9]+: Info: sli z0\.d, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sli z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sli z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sli z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sli z0\.b,z32\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sli z0\.b,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sli z0\.h,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sli z0\.s,z0\.s,#32'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 3 -- `sli z0\.d,z0\.d,#64'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sm4e z0\.s,z0\.s,z1\.s'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sm4e z1\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4e z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4e z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4e z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sm4e z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sm4e z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sm4e z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `sm4e z0\.s,z0\.s,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sm4e z0\.s, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4ekey z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4ekey z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4ekey z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sm4ekey z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sm4ekey z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sm4ekey z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `sm4ekey z0\.s,z0\.s,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sm4ekey z0\.s, z0\.s, z0\.s
@@ -1096,9 +1096,9 @@
[^ :]+:[0-9]+: Info: smaxp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: smaxp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `smaxp z1\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smaxp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smaxp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `smaxp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `smaxp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smaxp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `smaxp z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `smaxp z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sminp z0\.h,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1115,27 +1115,27 @@
[^ :]+:[0-9]+: Info: sminp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sminp z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sminp z1\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sminp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sminp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sminp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sminp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sminp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sminp z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sminp z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlalb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1143,23 +1143,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: smlalb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: smlalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlalt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1167,23 +1167,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: smlalt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: smlalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlslb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1191,23 +1191,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: smlslb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: smlslb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlslt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1222,26 +1222,26 @@
[^ :]+:[0-9]+: Info: smulh z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: smulh z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: smulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smulh z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `smulh z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smulh z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `smulh z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `smulh z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smulh z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smullb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1249,23 +1249,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: smullb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: smullb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: smullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smullt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1283,14 +1283,14 @@
[^ :]+:[0-9]+: Info: splice z0\.d, p0, {z0\.d, z1\.d}
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `splice z32\.b,p0,{z0\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `splice z32\.b,p0,{z0\.b,z1\.b}'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `splice z0\.b,p8,{z0\.b,z1\.b}'
[^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z31\.b,z1\.b}'
[^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z31\.b,z32\.b}'
-[^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z32\.b,z1\.b}'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqabs z32\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `splice z0\.b,p0,{z32\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqabs z32\.b,p0/m,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqabs z0\.b,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqabs z0\.b,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqabs z0\.b,p0/m,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/m,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqabs z0\.b, p0/m, z0\.b
@@ -1305,9 +1305,9 @@
[^ :]+:[0-9]+: Info: sqabs z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sqabs z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: sqabs z0\.d, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -1326,9 +1326,9 @@
[^ :]+:[0-9]+: Info: sqadd z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `sqcadd z0\.b,z0\.b,z0\.b,#180'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sqcadd z0\.b,z1\.b,z0\.b,#90'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqcadd z32\.b,z0\.b,z0\.b,#90'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqcadd z0\.b,z32\.b,z0\.b,#90'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqcadd z0\.b,z0\.b,z32\.b,#90'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcadd z32\.b,z0\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqcadd z0\.b,z32\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqcadd z0\.b,z0\.b,z32\.b,#90'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqcadd z0\.b,z0\.b,z0\.h,#90'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqcadd z0\.b, z0\.b, z0\.b, #90
@@ -1336,23 +1336,23 @@
[^ :]+:[0-9]+: Info: sqcadd z0\.h, z0\.h, z0\.h, #90
[^ :]+:[0-9]+: Info: sqcadd z0\.s, z0\.s, z0\.s, #90
[^ :]+:[0-9]+: Info: sqcadd z0\.d, z0\.d, z0\.d, #90
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlalb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1360,9 +1360,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmlalb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmlalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlalbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlalbt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalbt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalbt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1370,23 +1370,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmlalbt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmlalbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlalt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1394,23 +1394,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmlalt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmlalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlslb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1418,9 +1418,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmlslb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmlslb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlslbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlslbt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslbt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslbt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1428,23 +1428,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmlslbt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmlslbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlslt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1452,8 +1452,8 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmlslt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmlslt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmulh z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.h\[0\]'
@@ -1462,8 +1462,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmulh z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.s\[0\]'
@@ -1472,8 +1472,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmulh z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqdmulh z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.h,z0\.d\[0\]'
@@ -1482,9 +1482,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmulh z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmulh z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1493,23 +1493,23 @@
[^ :]+:[0-9]+: Info: sqdmulh z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: sqdmulh z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqdmulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmullb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1517,23 +1517,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmullb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmullb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqdmullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmullt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1541,9 +1541,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqdmullt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqdmullt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqneg z32\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqneg z32\.b,p0/m,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqneg z0\.b,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqneg z0\.b,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqneg z0\.b,p0/m,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/m,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqneg z0\.b, p0/m, z0\.b
@@ -1558,8 +1558,8 @@
[^ :]+:[0-9]+: Info: sqneg z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sqneg z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: sqneg z0\.d, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z8\.h\[0\],#0'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[4\],#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#1'
@@ -1570,8 +1570,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.s,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z16\.s\[0\],#0'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[2\],#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[0\],#1'
@@ -1582,9 +1582,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.s,z0\.h,z0\.s\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.b,z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.b,z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdcmlah z0\.b,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.b,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdcmlah z0\.b,z0\.b,z32\.b,#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#1'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#360'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.b,z0\.b,z0\.h,#0'
@@ -1594,8 +1594,8 @@
[^ :]+:[0-9]+: Info: sqrdcmlah z0\.h, z0\.h, z0\.h, #0
[^ :]+:[0-9]+: Info: sqrdcmlah z0\.s, z0\.s, z0\.s, #0
[^ :]+:[0-9]+: Info: sqrdcmlah z0\.d, z0\.d, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlah z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.h\[0\]'
@@ -1604,8 +1604,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlah z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.s\[0\]'
@@ -1614,8 +1614,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlah z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlah z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.h,z0\.d\[0\]'
@@ -1624,9 +1624,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlah z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmlah z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlah z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1635,8 +1635,8 @@
[^ :]+:[0-9]+: Info: sqrdmlah z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: sqrdmlah z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqrdmlah z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.h\[0\]'
@@ -1645,8 +1645,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.s\[0\]'
@@ -1655,8 +1655,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.h,z0\.d\[0\]'
@@ -1665,9 +1665,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlsh z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1676,8 +1676,8 @@
[^ :]+:[0-9]+: Info: sqrdmlsh z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: sqrdmlsh z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqrdmlsh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.h,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.h,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmulh z0\.h,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.h\[0\]'
@@ -1686,8 +1686,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmulh z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.s\[0\]'
@@ -1696,8 +1696,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmulh z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmulh z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.h,z0\.d\[0\]'
@@ -1706,9 +1706,9 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmulh z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmulh z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -1717,9 +1717,9 @@
[^ :]+:[0-9]+: Info: sqrdmulh z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: sqrdmulh z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqrdmulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqrshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqrshl z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshl z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshl z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -1736,9 +1736,9 @@
[^ :]+:[0-9]+: Info: sqrshl z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqrshl z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqrshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqrshlr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshlr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshlr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -1755,8 +1755,8 @@
[^ :]+:[0-9]+: Info: sqrshlr z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqrshlr z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqrshlr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrnb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnb z0\.h,z0\.h,#8'
@@ -1770,8 +1770,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrnt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnt z0\.h,z0\.h,#8'
@@ -1784,8 +1784,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnt z0\.h,z0\.s,#17'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrunb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrunb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunb z0\.h,z0\.h,#8'
@@ -1799,8 +1799,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrunt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrunt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrunt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunt z0\.h,z0\.h,#8'
@@ -1820,15 +1820,15 @@
[^ :]+:[0-9]+: Info: sqshl z0\.h, p0/m, z0\.h, #0
[^ :]+:[0-9]+: Info: sqshl z0\.s, p0/m, z0\.s, #0
[^ :]+:[0-9]+: Info: sqshl z0\.d, p0/m, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqshl z32\.b,p0/m,z32\.b,#0'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,#0'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshl z0\.h,p0/m,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshl z0\.s,p0/m,z0\.s,#32'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshl z0\.d,p0/m,z0\.d,#64'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqshl z0\.b,p0/m,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,z0\.b'
@@ -1846,9 +1846,9 @@
[^ :]+:[0-9]+: Info: sqshl z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqshl z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqshlr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -1872,15 +1872,15 @@
[^ :]+:[0-9]+: Info: sqshlu z0\.h, p0/m, z0\.h, #0
[^ :]+:[0-9]+: Info: sqshlu z0\.s, p0/m, z0\.s, #0
[^ :]+:[0-9]+: Info: sqshlu z0\.d, p0/m, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqshlu z32\.b,p0/m,z32\.b,#0'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlu z0\.b,p0/m,z1\.b,#0'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlu z0\.b,p8/m,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshlu z0\.b,p0/m,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshlu z0\.h,p0/m,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshlu z0\.s,p0/m,z0\.s,#32'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshlu z0\.d,p0/m,z0\.d,#64'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrnb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnb z0\.h,z0\.h,#8'
@@ -1894,8 +1894,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrnt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnt z0\.h,z0\.h,#8'
@@ -1908,8 +1908,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnt z0\.h,z0\.s,#17'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrunb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrunb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunb z0\.h,z0\.h,#8'
@@ -1923,8 +1923,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrunt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrunt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrunt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunt z0\.h,z0\.h,#8'
@@ -1937,9 +1937,9 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunt z0\.h,z0\.s,#17'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqsub z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqsub z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsub z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsub z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqsub z0\.h,p0/m,z0\.b,z0\.b'
@@ -1956,9 +1956,9 @@
[^ :]+:[0-9]+: Info: sqsub z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqsub z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqsub z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqsubr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqsubr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsubr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsubr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqsubr z0\.h,p0/m,z0\.b,z0\.b'
@@ -1975,41 +1975,41 @@
[^ :]+:[0-9]+: Info: sqsubr z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: sqsubr z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: sqsubr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnb z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtnb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtnb z0\.b,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnb z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqxtnb z0\.b, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqxtnb z0\.h, z0\.s
[^ :]+:[0-9]+: Info: sqxtnb z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnt z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtnt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtnt z0\.b,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnt z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqxtnt z0\.b, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqxtnt z0\.h, z0\.s
[^ :]+:[0-9]+: Info: sqxtnt z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunb z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtunb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtunb z0\.b,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunb z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqxtunb z0\.b, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqxtunb z0\.h, z0\.s
[^ :]+:[0-9]+: Info: sqxtunb z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunt z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtunt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtunt z0\.b,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunt z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqxtunt z0\.b, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqxtunt z0\.h, z0\.s
[^ :]+:[0-9]+: Info: sqxtunt z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srhadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srhadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `srhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `srhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `srhadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srhadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srhadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `srhadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2033,8 +2033,8 @@
[^ :]+:[0-9]+: Info: sri z0\.h, z0\.h, #1
[^ :]+:[0-9]+: Info: sri z0\.s, z0\.s, #1
[^ :]+:[0-9]+: Info: sri z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sri z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sri z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sri z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sri z0\.b,z32\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sri z0\.h,z0\.h,#0'
@@ -2042,9 +2042,9 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#33'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `sri z0\.d,z0\.d,#0'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `srshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `srshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `srshl z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshl z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshl z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `srshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -2061,9 +2061,9 @@
[^ :]+:[0-9]+: Info: srshl z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: srshl z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: srshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `srshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `srshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `srshlr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshlr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshlr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `srshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2087,7 +2087,7 @@
[^ :]+:[0-9]+: Info: srshr z0\.h, p0/m, z0\.h, #1
[^ :]+:[0-9]+: Info: srshr z0\.s, p0/m, z0\.s, #1
[^ :]+:[0-9]+: Info: srshr z0\.d, p0/m, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshr z32\.b,p0/m,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `srshr z32\.b,p0/m,z32\.b,#1'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshr z0\.b,p0/m,z1\.b,#1'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshr z0\.b,p8/m,z0\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `srshr z0\.b,p0/m,z0\.b,#0'
@@ -2105,8 +2105,8 @@
[^ :]+:[0-9]+: Info: srsra z0\.h, z0\.h, #1
[^ :]+:[0-9]+: Info: srsra z0\.s, z0\.s, #1
[^ :]+:[0-9]+: Info: srsra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srsra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `srsra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `srsra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `srsra z0\.b,z32\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `srsra z0\.h,z0\.h,#0'
@@ -2120,8 +2120,8 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sshllb z0\.s, z0\.h, #0
[^ :]+:[0-9]+: Info: sshllb z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllb z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllb z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sshllb z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sshllb z0\.h,z32\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllb z0\.h,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllb z0\.s,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllb z0\.d,z0\.s,#32'
@@ -2131,8 +2131,8 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sshllt z0\.s, z0\.h, #0
[^ :]+:[0-9]+: Info: sshllt z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllt z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllt z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sshllt z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sshllt z0\.h,z32\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllt z0\.h,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllt z0\.s,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllt z0\.d,z0\.s,#32'
@@ -2143,8 +2143,8 @@
[^ :]+:[0-9]+: Info: ssra z0\.h, z0\.h, #1
[^ :]+:[0-9]+: Info: ssra z0\.s, z0\.s, #1
[^ :]+:[0-9]+: Info: ssra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ssra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ssra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssra z0\.b,z32\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ssra z0\.h,z0\.h,#0'
@@ -2152,9 +2152,9 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#33'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `ssra z0\.d,z0\.d,#0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssublb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssublb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssublb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `ssublb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2162,9 +2162,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssublb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: ssublb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssublbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssublbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssublbt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublbt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `ssublbt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2172,9 +2172,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssublbt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: ssublbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssublt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssublt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssublt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `ssublt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2182,9 +2182,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssublt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: ssublt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubltb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubltb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubltb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssubltb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssubltb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssubltb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubltb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `ssubltb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2192,9 +2192,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssubltb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: ssubltb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssubwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssubwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssubwb z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwb z0\.s,z0\.s,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `ssubwb z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2202,9 +2202,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssubwb z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: ssubwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssubwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssubwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssubwt z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwt z0\.s,z0\.s,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `ssubwt z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2216,7 +2216,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
@@ -2227,7 +2227,7 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
@@ -2237,7 +2237,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1d {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
@@ -2251,7 +2251,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
@@ -2262,7 +2262,7 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
@@ -2272,7 +2272,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
@@ -2283,7 +2283,7 @@
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
@@ -2295,21 +2295,21 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: subhnb z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: subhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `subhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `subhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `subhnb z0\.b,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `subhnt z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: subhnt z0\.b, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: subhnt z0\.h, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: subhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnt z0\.b,z0\.h,z32\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `suqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `suqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `suqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `subhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `subhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `subhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `suqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `suqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `suqadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `suqadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `suqadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `suqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2326,10 +2326,10 @@
[^ :]+:[0-9]+: Info: suqadd z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: suqadd z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: suqadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `tbl z0\.b,{z31\.b,z32\.b},z0\.b'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.b,{z31\.b,z1\.b},z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b, z1\.b}, z0\.b
@@ -2340,9 +2340,9 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbx z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `tbx z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbx z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbx z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `tbx z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbx z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `tbx z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `tbx z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2351,9 +2351,9 @@
[^ :]+:[0-9]+: Info: tbx z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: tbx z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: tbx z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaba z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaba z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaba z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uaba z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaba z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaba z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaba z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uaba z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2362,9 +2362,9 @@
[^ :]+:[0-9]+: Info: uaba z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: uaba z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uaba z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabalb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uabalb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2372,9 +2372,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uabalb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uabalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabalt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uabalt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2382,9 +2382,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uabalt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uabalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabdlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabdlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabdlb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uabdlb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2392,9 +2392,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uabdlb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uabdlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabdlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabdlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabdlt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uabdlt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2415,11 +2415,11 @@
[^ :]+:[0-9]+: Info: uadalp z0\.s, p0/m, z0\.h
[^ :]+:[0-9]+: Info: uadalp z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uadalp z0\.h,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uadalp z32\.h,p0/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uadalp z0\.h,p0/m,z32\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uadalp z32\.h,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uadalp z0\.h,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddlb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uaddlb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2427,9 +2427,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uaddlb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uaddlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddlt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uaddlt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2437,9 +2437,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uaddlt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uaddlt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddwb z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwb z0\.s,z0\.s,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uaddwb z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2447,9 +2447,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uaddwb z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: uaddwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddwt z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwt z0\.s,z0\.s,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `uaddwt z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2457,9 +2457,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uaddwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: uaddwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uhadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uhadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2476,9 +2476,9 @@
[^ :]+:[0-9]+: Info: uhadd z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uhadd z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uhadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsub z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uhsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uhsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uhsub z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsub z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsub z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uhsub z0\.h,p0/m,z0\.b,z0\.b'
@@ -2495,9 +2495,9 @@
[^ :]+:[0-9]+: Info: uhsub z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uhsub z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uhsub z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsubr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uhsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uhsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uhsubr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsubr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsubr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uhsubr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2514,9 +2514,9 @@
[^ :]+:[0-9]+: Info: uhsubr z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uhsubr z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uhsubr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umaxp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umaxp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `umaxp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `umaxp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umaxp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `umaxp z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `umaxp z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `umaxp z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `umaxp z0\.h,p0/m,z0\.b,z0\.b'
@@ -2533,9 +2533,9 @@
[^ :]+:[0-9]+: Info: umaxp z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umaxp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: umaxp z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uminp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uminp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uminp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uminp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uminp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uminp z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uminp z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uminp z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uminp z0\.h,p0/m,z0\.b,z0\.b'
@@ -2552,23 +2552,23 @@
[^ :]+:[0-9]+: Info: uminp z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uminp z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uminp z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlalb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2576,23 +2576,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: umlalb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umlalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlalt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2600,23 +2600,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: umlalt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umlalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlslb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2624,23 +2624,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: umlslb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umlslb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlslt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2648,9 +2648,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: umlslt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umlslt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umulh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `umulh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `umulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `umulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umulh z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umulh z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umulh z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2659,23 +2659,23 @@
[^ :]+:[0-9]+: Info: umulh z0\.b, z0\.b, z0\.b
[^ :]+:[0-9]+: Info: umulh z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: umulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullb z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullb z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umullb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2683,23 +2683,23 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: umullb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umullb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.s,z32\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullt z0\.d,z0\.s,z16\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullt z0\.d,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: umullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umullt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2707,9 +2707,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: umullt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: umullt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2726,9 +2726,9 @@
[^ :]+:[0-9]+: Info: uqadd z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqadd z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqrshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqrshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqrshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqrshl z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshl z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshl z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -2745,9 +2745,9 @@
[^ :]+:[0-9]+: Info: uqrshl z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqrshl z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqrshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqrshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqrshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqrshlr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshlr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshlr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2764,8 +2764,8 @@
[^ :]+:[0-9]+: Info: uqrshlr z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqrshlr z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqrshlr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqrshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqrshrnb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnb z0\.h,z0\.h,#8'
@@ -2779,8 +2779,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqrshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqrshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqrshrnt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnt z0\.h,z0\.h,#8'
@@ -2800,15 +2800,15 @@
[^ :]+:[0-9]+: Info: uqshl z0\.h, p0/m, z0\.h, #0
[^ :]+:[0-9]+: Info: uqshl z0\.s, p0/m, z0\.s, #0
[^ :]+:[0-9]+: Info: uqshl z0\.d, p0/m, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqshl z32\.b,p0/m,z32\.b,#0'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,#0'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `uqshl z0\.h,p0/m,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `uqshl z0\.s,p0/m,z0\.s,#32'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `uqshl z0\.d,p0/m,z0\.d,#64'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqshl z0\.b,p0/m,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,z0\.b'
@@ -2826,9 +2826,9 @@
[^ :]+:[0-9]+: Info: uqshl z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqshl z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqshlr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshlr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshlr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2845,8 +2845,8 @@
[^ :]+:[0-9]+: Info: uqshlr z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqshlr z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqshlr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqshrnb z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnb z0\.h,z0\.h,#8'
@@ -2860,8 +2860,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#33'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqshrnt z0\.b,z32\.h,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnt z0\.h,z0\.h,#8'
@@ -2874,9 +2874,9 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnt z0\.h,z0\.s,#17'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqsub z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqsub z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsub z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsub z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqsub z0\.h,p0/m,z0\.b,z0\.b'
@@ -2893,9 +2893,9 @@
[^ :]+:[0-9]+: Info: uqsub z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqsub z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqsub z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqsubr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqsubr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsubr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsubr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqsubr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2912,31 +2912,31 @@
[^ :]+:[0-9]+: Info: uqsubr z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: uqsubr z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: uqsubr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnb z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqxtnb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqxtnb z0\.b,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnb z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: uqxtnb z0\.b, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uqxtnb z0\.h, z0\.s
[^ :]+:[0-9]+: Info: uqxtnb z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnt z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqxtnt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqxtnt z0\.b,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnt z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: uqxtnt z0\.b, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: uqxtnt z0\.h, z0\.s
[^ :]+:[0-9]+: Info: uqxtnt z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urecpe z32\.s,p0/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urecpe z0\.s,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `urecpe z32\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urecpe z0\.s,p0/m,z32\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urecpe z0\.s,p8/m,z0\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `urecpe z0\.d,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: urecpe z0\.s, p0/m, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urhadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urhadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `urhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `urhadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urhadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urhadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `urhadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2953,9 +2953,9 @@
[^ :]+:[0-9]+: Info: urhadd z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: urhadd z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: urhadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `urshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `urshl z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshl z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshl z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `urshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -2972,9 +2972,9 @@
[^ :]+:[0-9]+: Info: urshl z0\.h, p0/m, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: urshl z0\.s, p0/m, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: urshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `urshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `urshlr z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshlr z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshlr z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `urshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2998,7 +2998,7 @@
[^ :]+:[0-9]+: Info: urshr z0\.h, p0/m, z0\.h, #1
[^ :]+:[0-9]+: Info: urshr z0\.s, p0/m, z0\.s, #1
[^ :]+:[0-9]+: Info: urshr z0\.d, p0/m, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshr z32\.b,p0/m,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `urshr z32\.b,p0/m,z32\.b,#1'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshr z0\.b,p0/m,z1\.b,#1'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshr z0\.b,p8/m,z0\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `urshr z0\.b,p0/m,z0\.b,#0'
@@ -3009,8 +3009,8 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `urshr z0\.s,p0/m,z0\.s,#33'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#65'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ursqrte z32\.s,p0/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ursqrte z0\.s,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `ursqrte z32\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ursqrte z0\.s,p0/m,z32\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ursqrte z0\.s,p8/m,z0\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `ursqrte z0\.d,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -3022,8 +3022,8 @@
[^ :]+:[0-9]+: Info: ursra z0\.h, z0\.h, #1
[^ :]+:[0-9]+: Info: ursra z0\.s, z0\.s, #1
[^ :]+:[0-9]+: Info: ursra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ursra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ursra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ursra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ursra z0\.b,z32\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ursra z0\.h,z0\.h,#0'
@@ -3037,8 +3037,8 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ushllb z0\.s, z0\.h, #0
[^ :]+:[0-9]+: Info: ushllb z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllb z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllb z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ushllb z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ushllb z0\.h,z32\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllb z0\.h,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllb z0\.s,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllb z0\.d,z0\.s,#32'
@@ -3048,14 +3048,14 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ushllt z0\.s, z0\.h, #0
[^ :]+:[0-9]+: Info: ushllt z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllt z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllt z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ushllt z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ushllt z0\.h,z32\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllt z0\.h,z0\.b,#8'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllt z0\.s,z0\.h,#16'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllt z0\.d,z0\.s,#32'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `usqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `usqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `usqadd z0\.b,p0/m,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `usqadd z0\.b,p0/m,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `usqadd z0\.b,p8/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `usqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -3079,8 +3079,8 @@
[^ :]+:[0-9]+: Info: usra z0\.h, z0\.h, #1
[^ :]+:[0-9]+: Info: usra z0\.s, z0\.s, #1
[^ :]+:[0-9]+: Info: usra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `usra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usra z0\.b,z32\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `usra z0\.h,z0\.h,#0'
@@ -3088,9 +3088,9 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#33'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `usra z0\.d,z0\.d,#0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usublb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usublb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usublb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublb z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `usublb z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -3098,9 +3098,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: usublb z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: usublb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usublt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usublt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usublt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublt z0\.s,z0\.h,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `usublt z0\.h,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -3108,9 +3108,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: usublt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: usublt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usubwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usubwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usubwb z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwb z0\.s,z0\.s,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `usubwb z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -3118,9 +3118,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: usubwb z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: usubwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usubwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usubwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usubwt z0\.h,z0\.h,z32\.b'
[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwt z0\.s,z0\.s,z0\.x'
[^ :]+:[0-9]+: Error: operand mismatch -- `usubwt z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -3128,9 +3128,9 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: usubwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: usubwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilege p0\.b, x0, x0
@@ -3138,8 +3138,8 @@
[^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x31'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0\.b,x0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilege p0\.b, x0, x0
@@ -3154,9 +3154,9 @@
[^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilege p0\.b, x0, x0
@@ -3164,11 +3164,11 @@
[^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilegt p0\.b, x0, x0
@@ -3176,8 +3176,8 @@
[^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x31'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0\.b,x0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilegt p0\.b, x0, x0
@@ -3192,9 +3192,9 @@
[^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilegt p0\.b, x0, x0
@@ -3202,11 +3202,11 @@
[^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilehi p0\.b, x0, x0
@@ -3214,8 +3214,8 @@
[^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x31'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0\.b,x0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilehi p0\.b, x0, x0
@@ -3230,9 +3230,9 @@
[^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilehi p0\.b, x0, x0
@@ -3240,11 +3240,11 @@
[^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilehs p0\.b, x0, x0
@@ -3252,8 +3252,8 @@
[^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x31'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0\.b,x0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilehs p0\.b, x0, x0
@@ -3268,9 +3268,9 @@
[^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilehs p0\.b, x0, x0
@@ -3278,8 +3278,8 @@
[^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w31'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0\.b,w0,x0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilerw p0\.b, x0, x0
@@ -3294,8 +3294,8 @@
[^ :]+:[0-9]+: Info: whilerw p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilerw p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilerw p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilerw p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilerw p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilerw p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilerw p16\.b,x0,x0'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilewr p0\.b,w0,x0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: whilewr p0\.b, x0, x0
@@ -3310,8 +3310,8 @@
[^ :]+:[0-9]+: Info: whilewr p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilewr p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilewr p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilewr p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilewr p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilewr p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilewr p16\.b,x0,x0'
[^ :]+:[0-9]+: Error: operand mismatch -- `xar z0\.h,z0\.b,z0\.b,#1'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: xar z0\.b, z0\.b, z0\.b, #1
@@ -3320,8 +3320,8 @@
[^ :]+:[0-9]+: Info: xar z0\.s, z0\.s, z0\.s, #1
[^ :]+:[0-9]+: Info: xar z0\.d, z0\.d, z0\.d, #1
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `xar z0\.b,z1\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `xar z32\.b,z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `xar z0\.b,z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `xar z32\.b,z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `xar z0\.b,z0\.b,z32\.b,#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#9'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `xar z0\.h,z0\.h,z0\.h,#0'
diff --git a/gas/testsuite/gas/aarch64/legacy_reg_names.l b/gas/testsuite/gas/aarch64/legacy_reg_names.l
index 791bad33a69..f3dde54e418 100644
--- a/gas/testsuite/gas/aarch64/legacy_reg_names.l
+++ b/gas/testsuite/gas/aarch64/legacy_reg_names.l
@@ -1,4 +1,4 @@
[^:]*: Assembler messages:
[^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
-[^:]*:6: Error: operand 1 must be an integer register -- `mov r0.w,r1.w'
-[^:]*:7: Error: operand 2 must be a SIMD vector element -- `dup s0,s1\[3\]'
+[^:]*:6: Error: expected a register at operand 1 -- `mov r0.w,r1.w'
+[^:]*:7: Error: expected an Advanced SIMD vector register at operand 2 -- `dup s0,s1\[3\]'
diff --git a/gas/testsuite/gas/aarch64/mops_invalid.l b/gas/testsuite/gas/aarch64/mops_invalid.l
index 8f5e588482c..76a5c30fd1e 100644
--- a/gas/testsuite/gas/aarch64/mops_invalid.l
+++ b/gas/testsuite/gas/aarch64/mops_invalid.l
@@ -10,44 +10,44 @@
[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,#0\]!,x2!'
[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,xzr\]!,x2!'
[^:]+:[0-9]+: Error: operand 3 must be an integer register with writeback -- `cpyfp \[x0\]!,\[x1\]!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!'
[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x0\]!,\[x0\]!,x1!'
[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x10\]!,\[x1\]!,x10!'
[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x1\]!,\[x30\]!,x30!'
@@ -56,24 +56,24 @@
[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0\],x1!,x2'
[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,#0\]!,x1!,x2'
[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,xzr\]!,x1!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[x31\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[sp\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[zr\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w30\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w0\]!,x1!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wsp\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wzr\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[foo\]!,x1!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,x31!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,sp!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,zr!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,w30!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,w0!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wsp!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wzr!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,foo!,x2'
-[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,sp'
-[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,wsp'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[x31\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[sp\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[zr\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[w30\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[w0\]!,x1!,x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[wsp\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[wzr\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[foo\]!,x1!,x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,x31!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,sp!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,zr!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,w30!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x1\]!,w0!,x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,wsp!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,wzr!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x1\]!,foo!,x2'
+[^:]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `setp \[x30\]!,x0!,sp'
+[^:]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `setp \[x30\]!,x0!,wsp'
[^:]+:[0-9]+: Error: operand mismatch -- `setp \[x30\]!,x0!,wzr'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: setp \[x30\]!, x0!, xzr
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index b4ce9dc69fd..1df18ef2002 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -3,7 +3,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.h,p0/m,za2h\.h\[w12,#0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]'
-[^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 3 -- `mova z0\.q,p0/m,za16h.q\[w12\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l
index cb8fe4ef47a..717af3b54be 100644
--- a/gas/testsuite/gas/aarch64/sme-3-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l
@@ -3,7 +3,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index 57d7d65c08c..86e315476dd 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -22,11 +22,11 @@
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za_}'
+[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zaX}'
+[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}'
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zax}'
+[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
[^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}'
@@ -37,5 +37,5 @@
[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.q}'
[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za.2d}'
[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za0.2d}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0h\.b}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0v\.b}'
+[^:]*:[0-9]+: Error: expected an unsuffixed ZA tile at operand 1 -- `zero {za0h\.b}'
+[^:]*:[0-9]+: Error: expected an unsuffixed ZA tile at operand 1 -- `zero {za0v\.b}'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index 852f1547634..f892dcd2090 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -35,10 +35,10 @@
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
@@ -49,3 +49,10 @@
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]'
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
[^:]*:[0-9]+: Error: missing immediate offset at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]'
+[^:]*:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `ld1b {za0.b\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {za.b\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1b za0h.b\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1h za0h.h\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1w za0h.s\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1d za0h.d\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1q za0h.q\[w12,0\],p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.s b/gas/testsuite/gas/aarch64/sme-5-illegal.s
index bf65f6af5ce..29f86669043 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.s
@@ -50,3 +50,10 @@ ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3]
ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4]
ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1]
ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1]
+ld1b {za0.b[w12, 0]}, p0/z, [x0]
+ld1b {za.b[w12, 0]}, p0/z, [x0]
+ld1b za0h.b[w12, 0], p0/z, [x0]
+ld1h za0h.h[w12, 0], p0/z, [x0]
+ld1w za0h.s[w12, 0], p0/z, [x0]
+ld1d za0h.d[w12, 0], p0/z, [x0]
+ld1q za0h.q[w12, 0], p0/z, [x0]
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index 30aea0b75ea..c8141e086ab 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -35,10 +35,10 @@
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index cf4bca2cd20..0023a84da71 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -48,3 +48,9 @@
[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `ldr za/z\[w12,0\],\[x0\]'
[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `ldr za.2b\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0.b\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h.h\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v.s\[w12,0\],\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s
index 0669fe16dd4..75e2810e647 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s
@@ -45,3 +45,10 @@ ldr za.d[w12, 0], [x0]
ldr za.q[w12, 0], [x0]
ldr za/z[w12, 0], [x0]
ldr za.2b[w12, 0], [x0]
+
+ldr za0[w12, 0], [x0]
+ldr za0.b[w12, 0], [x0]
+ldr za0h[w12, 0], [x0]
+ldr za0h.h[w12, 0], [x0]
+ldr za0v[w12, 0], [x0]
+ldr za0v.s[w12, 0], [x0]
diff --git a/gas/testsuite/gas/aarch64/sme-illegal.l b/gas/testsuite/gas/aarch64/sme-illegal.l
index efc9b800656..f8d05478cc6 100644
--- a/gas/testsuite/gas/aarch64/sme-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-illegal.l
@@ -4,6 +4,7 @@
[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.s,p2/m,p3/m,z2.d'
[^:]*:[0-9]+: Info: did you mean this\?
[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d
+[^:]*:[0-9]+: Error: expected a ZA tile at operand 1 -- `addha z0.s,p0/m,p1/m,z1.s'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d'
[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.d,p2/m,p3/m,z2.s'
diff --git a/gas/testsuite/gas/aarch64/sme-illegal.s b/gas/testsuite/gas/aarch64/sme-illegal.s
index d543a64217a..512d4523a17 100644
--- a/gas/testsuite/gas/aarch64/sme-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-illegal.s
@@ -4,6 +4,7 @@
addha za4.s, p0/m, p1/m, z1.s
addha za15.s, p2/m, p3/m, z2.s
addha za0.s, p2/m, p3/m, z2.d
+addha z0.s, p0/m, p1/m, z1.s
/* ADDHA 64-bit variant. */
addha za8.d, p0/m, p1/m, z1.d
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index b0750933612..ca447307b9e 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1,5 +1,5 @@
[^:]*: Assembler messages:
-.*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2'
+.*: Error: expected an SVE predicate register at operand 2 -- `fmov z1,z2'
.*: Error: operand mismatch -- `fmov z1,#1\.0'
.*: Info: did you mean this\?
.*: Info: fmov z1\.h, #1\.000000000000000000e\+00
@@ -126,7 +126,7 @@
.*: Info: movprfx z0\.s, p1/m, z1\.s
.*: Info: movprfx z0\.d, p1/z, z1\.d
.*: Info: movprfx z0\.d, p1/m, z1\.d
-.*: Error: operand 1 must be an SVE vector register -- `movprfx p0,p1'
+.*: Error: expected an SVE vector register at operand 1 -- `movprfx p0,p1'
.*: Error: operand mismatch -- `ldr p0\.b,\[x1\]'
.*: Info: did you mean this\?
.*: Info: ldr p0, \[x1\]
@@ -184,7 +184,7 @@
.*: Info: add z0\.s, z0\.s, #1
.*: Info: add z0\.d, z0\.d, #1
.*: Error: constant expression required at operand 2 -- `mov z0\.b,z32\.b'
-.*: Error: operand 2 must be an SVE predicate register -- `mov p0\.b,p16\.b'
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p0\.b,p16\.b'
.*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p8/z,z1\.b,z2\.b'
.*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p15/z,z1\.b,z2\.b'
.*: Error: operand mismatch -- `ld1w z0\.s,p0,\[x0\]'
@@ -275,12 +275,12 @@
.*: Error: missing type suffix at operand 1 -- `stnt1h {z0},p1/z,\[x1\]'
.*: Error: missing type suffix at operand 1 -- `stnt1w {z0},p1/z,\[x1\]'
.*: Error: missing type suffix at operand 1 -- `stnt1d {z0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {x0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {b0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {h0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {s0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {d0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {v0\.2s},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {x0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {b0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {h0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {s0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {d0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {v0\.2s},p1/z,\[x1\]'
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1},p1/z,\[x1\]'
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.h},p1/z,\[x1\]'
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.s},p1/z,\[x1\]'
@@ -859,7 +859,7 @@
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#-1'
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#8'
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#9'
-.*: Error: operand 3 must be an SVE vector register -- `lsl z0\.b,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 3 -- `lsl z0\.b,z0\.b,x0'
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#-1'
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#16'
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#17'
@@ -872,7 +872,7 @@
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#-1'
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#8'
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#9'
-.*: Error: operand 4 must be an SVE vector register -- `lsl z0\.b,p1/m,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 4 -- `lsl z0\.b,p1/m,z0\.b,x0'
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#-1'
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#16'
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#17'
@@ -885,7 +885,7 @@
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#-1'
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#0'
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#9'
-.*: Error: operand 3 must be an SVE vector register -- `lsr z0\.b,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 3 -- `lsr z0\.b,z0\.b,x0'
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#-1'
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#0'
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#17'
@@ -898,7 +898,7 @@
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#-1'
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#0'
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#9'
-.*: Error: operand 4 must be an SVE vector register -- `lsr z0\.b,p1/m,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 4 -- `lsr z0\.b,p1/m,z0\.b,x0'
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#-1'
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#0'
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#17'
@@ -914,8 +914,8 @@
.*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#16'
.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl x0,sp,#-33'
.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl sp,x0,#32'
-.*: Error: operand 2 must be an integer register or SP -- `addpl x0,xzr,#1'
-.*: Error: operand 1 must be an integer or stack pointer register -- `addpl xzr,x0,#1'
+.*: Error: expected an integer or stack pointer register at operand 2 -- `addpl x0,xzr,#1'
+.*: Error: expected an integer or stack pointer register at operand 1 -- `addpl xzr,x0,#1'
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#-129'
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#128'
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#-129'
diff --git a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
index 34d6634714a..435d52a721f 100644
--- a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
+++ b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
@@ -1,6 +1,6 @@
.*: Assembler messages:
-.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,x0'
-.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0'
+.*: Error: expected an Advanced SIMD vector register at operand 3 -- `cmeq v0\.4s,v1\.4s,x0'
+.*: Error: expected an Advanced SIMD vector register at operand 3 -- `cmeq v0\.4s,v1\.4s,s0'
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b'
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b'
.*: Error: invalid base register at operand 2 -- `ldr x1,\[s0\]'
@@ -19,6 +19,6 @@
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#z0\.s'
.*: Error: immediate out of range at operand 3 -- `and x0,x0,p0'
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#p0'
-.*: Error: operand 3 must be an integer register -- `lsl x0,x0,s0'
+.*: Error: expected an integer or zero register at operand 3 -- `lsl x0,x0,s0'
.*: Error: immediate operand required at operand 1 -- `svc x0'
.*: Error: immediate operand required at operand 1 -- `svc s0'
diff --git a/gas/testsuite/gas/aarch64/tme-invalid.l b/gas/testsuite/gas/aarch64/tme-invalid.l
index 22f60c5b117..dd1a7d111ce 100644
--- a/gas/testsuite/gas/aarch64/tme-invalid.l
+++ b/gas/testsuite/gas/aarch64/tme-invalid.l
@@ -12,7 +12,7 @@
.*: Error: constant expression required at operand 1 -- `tcancel wsp'
.*: Error: constant expression required at operand 1 -- `tcancel xsp'
.*: Error: constant expression required at operand 1 -- `tcancel sp'
-.*: Error: operand 1 must be an integer register -- `tstart'
+.*: Error: expected an integer or zero register at operand 1 -- `tstart'
.*: Error: operand mismatch -- `tstart w1'
.*: Info: did you mean this\?
.*: Info: tstart x1
@@ -22,5 +22,5 @@
.*: Error: operand mismatch -- `tstart wzr'
.*: Info: did you mean this\?
.*: Info: tstart xzr
-.*: Error: operand 1 must be an integer register -- `tstart wsp'
-.*: Error: operand 1 must be an integer register -- `tstart xsp'
+.*: Error: expected an integer or zero register at operand 1 -- `tstart wsp'
+.*: Error: expected an integer or zero register at operand 1 -- `tstart xsp'
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 26/43] aarch64: Update operand_mismatch_kind_names
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (24 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
` (16 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
The contents of operand_mismatch_kind_names were out of sync
with the enum.
---
gas/config/tc-aarch64.c | 2 ++
include/opcode/aarch64.h | 5 ++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fac027ab7b8..8910872dbe4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5051,6 +5051,8 @@ const char* operand_mismatch_kind_names[] =
"AARCH64_OPDE_SYNTAX_ERROR",
"AARCH64_OPDE_FATAL_SYNTAX_ERROR",
"AARCH64_OPDE_INVALID_VARIANT",
+ "AARCH64_OPDE_UNTIED_IMMS",
+ "AARCH64_OPDE_UNTIED_OPERAND",
"AARCH64_OPDE_OUT_OF_RANGE",
"AARCH64_OPDE_UNALIGNED",
"AARCH64_OPDE_REG_LIST",
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index cc0ddf08989..60c77cab2a8 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1316,7 +1316,10 @@ struct aarch64_inst
The enumerators have an increasing severity. This is helpful when there are
multiple instruction templates available for a given mnemonic name (e.g.
FMOV); this mechanism will help choose the most suitable template from which
- the generated diagnostics can most closely describe the issues, if any. */
+ the generated diagnostics can most closely describe the issues, if any.
+
+ This enum needs to be kept up-to-date with operand_mismatch_kind_names
+ in tc-aarch64.c. */
enum aarch64_operand_error_kind
{
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (25 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
` (15 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
SME2 has many instructions that take a list of SVE registers.
There are often multiple forms, with different forms taking
different numbers of registers.
This means that if, after a successful parse and qualifier match,
we find that the number of registers does not match the opcode entry,
the associated error should have a lower priority/severity than other
errors reported at the same stage. For example, if there are 2-register
and 4-register forms of an instruction, and if the assembly code uses
the 2-register form with an out-of-range value, the out-of-range value
error against the 2-register instruction should have a higher priority
than the "wrong number of registers" error against the 4-register
instruction.
This is tested by the main SME2 patches, but seemed worth splitting out.
---
gas/config/tc-aarch64.c | 6 +++---
include/opcode/aarch64.h | 14 +++++++++-----
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8910872dbe4..86d5ba992ff 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5051,11 +5051,11 @@ const char* operand_mismatch_kind_names[] =
"AARCH64_OPDE_SYNTAX_ERROR",
"AARCH64_OPDE_FATAL_SYNTAX_ERROR",
"AARCH64_OPDE_INVALID_VARIANT",
+ "AARCH64_OPDE_REG_LIST",
"AARCH64_OPDE_UNTIED_IMMS",
"AARCH64_OPDE_UNTIED_OPERAND",
"AARCH64_OPDE_OUT_OF_RANGE",
"AARCH64_OPDE_UNALIGNED",
- "AARCH64_OPDE_REG_LIST",
"AARCH64_OPDE_OTHER_ERROR",
};
#endif /* DEBUG_AARCH64 */
@@ -5077,9 +5077,9 @@ operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_EXPECTED_A_AFTER_B);
gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
- gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
+ gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_INVALID_VARIANT);
+ gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST);
gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
- gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
return lhs > rhs;
}
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 60c77cab2a8..10c7983aa2d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1284,6 +1284,14 @@ struct aarch64_inst
No syntax error, but the operands are not a valid combination, e.g.
FMOV D0,S0
+ The following errors are only reported against an asm string that is
+ syntactically valid and that has valid operand qualifiers.
+
+ AARCH64_OPDE_REG_LIST
+ Error about the register list operand having an unexpected number of
+ registers. This error is low severity because there might be another
+ opcode entry that supports the given number of registers.
+
AARCH64_OPDE_UNTIED_IMMS
The asm failed to use the same immediate for a destination operand
and a tied source operand.
@@ -1299,10 +1307,6 @@ struct aarch64_inst
Error about some immediate value not properly aligned (i.e. not being a
multiple times of a certain value).
- AARCH64_OPDE_REG_LIST
- Error about the register list operand having unexpected number of
- registers.
-
AARCH64_OPDE_OTHER_ERROR
Error of the highest severity and used for any severe issue that does not
fall into any of the above categories.
@@ -1330,11 +1334,11 @@ enum aarch64_operand_error_kind
AARCH64_OPDE_SYNTAX_ERROR,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
AARCH64_OPDE_INVALID_VARIANT,
+ AARCH64_OPDE_REG_LIST,
AARCH64_OPDE_UNTIED_IMMS,
AARCH64_OPDE_UNTIED_OPERAND,
AARCH64_OPDE_OUT_OF_RANGE,
AARCH64_OPDE_UNALIGNED,
- AARCH64_OPDE_REG_LIST,
AARCH64_OPDE_OTHER_ERROR
};
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 28/43] aarch64: Add an error code for out-of-range registers
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (26 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
` (14 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
libopcodes currently reports out-of-range registers as a general
AARCH64_OPDE_OTHER_ERROR. However, this means that each register
range needs its own hard-coded string, which is a bit cumbersome
if the range is determined programmatically. This patch therefore
adds a dedicated error type for out-of-range errors.
---
gas/config/tc-aarch64.c | 8 ++++++++
include/opcode/aarch64.h | 10 +++++++++-
opcodes/aarch64-opc.c | 20 ++++++++++++++------
3 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 86d5ba992ff..145e241b13b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5057,6 +5057,7 @@ const char* operand_mismatch_kind_names[] =
"AARCH64_OPDE_OUT_OF_RANGE",
"AARCH64_OPDE_UNALIGNED",
"AARCH64_OPDE_OTHER_ERROR",
+ "AARCH64_OPDE_INVALID_REGNO",
};
#endif /* DEBUG_AARCH64 */
@@ -5081,6 +5082,7 @@ operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST);
gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
+ gas_assert (AARCH64_OPDE_INVALID_REGNO > AARCH64_OPDE_OTHER_ERROR);
return lhs > rhs;
}
@@ -5712,6 +5714,12 @@ output_operand_error_record (const operand_error_record *record, char *str)
detail->index + 1, str);
break;
+ case AARCH64_OPDE_INVALID_REGNO:
+ handler (_("%s%d-%s%d expected at operand %d -- `%s'"),
+ detail->data[0].s, detail->data[1].i,
+ detail->data[0].s, detail->data[2].i, idx + 1, str);
+ break;
+
case AARCH64_OPDE_OUT_OF_RANGE:
if (detail->data[0].i != detail->data[1].i)
handler (_("%s out of range %d to %d at operand %d -- `%s'"),
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 10c7983aa2d..6615dec41a7 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1311,6 +1311,13 @@ struct aarch64_inst
Error of the highest severity and used for any severe issue that does not
fall into any of the above categories.
+ AARCH64_OPDE_INVALID_REGNO
+ A register was syntactically valid and had the right type, but it was
+ outside the range supported by the associated operand field. This is
+ a high severity error because there are currently no instructions that
+ would accept the operands that precede the erroneous one (if any) and
+ yet still accept a wider range of registers.
+
AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and
AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the
AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
@@ -1339,7 +1346,8 @@ enum aarch64_operand_error_kind
AARCH64_OPDE_UNTIED_OPERAND,
AARCH64_OPDE_OUT_OF_RANGE,
AARCH64_OPDE_UNALIGNED,
- AARCH64_OPDE_OTHER_ERROR
+ AARCH64_OPDE_OTHER_ERROR,
+ AARCH64_OPDE_INVALID_REGNO
};
/* N.B. GAS assumes that this structure work well with shallow copy. */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 24cca9e8193..c36e4cc67f6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1335,6 +1335,18 @@ set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
}
+static inline void
+set_invalid_regno_error (aarch64_operand_error *mismatch_detail, int idx,
+ const char *prefix, int lower_bound, int upper_bound)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_error (mismatch_detail, AARCH64_OPDE_INVALID_REGNO, idx, NULL);
+ mismatch_detail->data[0].s = prefix;
+ mismatch_detail->data[1].i = lower_bound;
+ mismatch_detail->data[2].i = upper_bound;
+}
+
static inline void
set_out_of_range_error (aarch64_operand_error *mismatch_detail,
int idx, int lower_bound, int upper_bound,
@@ -1569,11 +1581,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
mask = (1 << shift) - 1;
if (opnd->reg.regno > mask)
{
- assert (mask == 7 || mask == 15);
- set_other_error (mismatch_detail, idx,
- mask == 15
- ? _("z0-z15 expected")
- : _("z0-z7 expected"));
+ set_invalid_regno_error (mismatch_detail, idx, "z", 0, mask);
return 0;
}
mask = (1u << (size - shift)) - 1;
@@ -1642,7 +1650,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
if (opnd->reg.regno >= 8
&& get_operand_fields_width (get_operand_from_code (type)) == 3)
{
- set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
+ set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7);
return 0;
}
break;
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 29/43] aarch64: Commonise checks for index operands
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (27 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
` (13 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch splits out the constraint checking for index operands,
so that it can be reused by new SME2 operands.
---
opcodes/aarch64-opc.c | 50 +++++++++++++++++++++++++++----------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index c36e4cc67f6..6b9b19ffc57 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1450,6 +1450,31 @@ set_other_error (aarch64_operand_error *mismatch_detail, int idx,
set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
}
+/* Check that indexed register operand OPND has a register in the range
+ [MIN_REGNO, MAX_REGNO] and an index in the range [MIN_INDEX, MAX_INDEX].
+ PREFIX is the register prefix, such as "z" for SVE vector registers. */
+
+static bool
+check_reglane (const aarch64_opnd_info *opnd,
+ aarch64_operand_error *mismatch_detail, int idx,
+ const char *prefix, int min_regno, int max_regno,
+ int min_index, int max_index)
+{
+ if (!value_in_range_p (opnd->reglane.regno, min_regno, max_regno))
+ {
+ set_invalid_regno_error (mismatch_detail, idx, prefix, min_regno,
+ max_regno);
+ return false;
+ }
+ if (!value_in_range_p (opnd->reglane.index, min_index, max_index))
+ {
+ set_elem_idx_out_of_range_error (mismatch_detail, idx, min_index,
+ max_index);
+ return false;
+ }
+ return true;
+}
+
/* Check that indexed ZA operand OPND has:
- a selection register in the range [MIN_WREG, MIN_WREG + 3]
@@ -1578,28 +1603,17 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SVE_Zm4_INDEX:
size = get_operand_fields_width (get_operand_from_code (type));
shift = get_operand_specific_data (&aarch64_operands[type]);
- mask = (1 << shift) - 1;
- if (opnd->reg.regno > mask)
- {
- set_invalid_regno_error (mismatch_detail, idx, "z", 0, mask);
- return 0;
- }
- mask = (1u << (size - shift)) - 1;
- if (!value_in_range_p (opnd->reglane.index, 0, mask))
- {
- set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
- return 0;
- }
+ if (!check_reglane (opnd, mismatch_detail, idx,
+ "z", 0, (1 << shift) - 1,
+ 0, (1u << (size - shift)) - 1))
+ return 0;
break;
case AARCH64_OPND_SVE_Zn_INDEX:
size = aarch64_get_qualifier_esize (opnd->qualifier);
- if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
- {
- set_elem_idx_out_of_range_error (mismatch_detail, idx,
- 0, 64 / size - 1);
- return 0;
- }
+ if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
+ 0, 64 / size - 1))
+ return 0;
break;
case AARCH64_OPND_SVE_ZnxN:
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 30/43] aarch64: Add an operand class for SVE register lists
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (28 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
` (12 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
SVE register lists were classified as SVE_REG, since there had been
no particular reason to separate them out. However, some SME2
instructions have tied register list operands, and so we need to
distinguish registers and register lists when checking whether two
operands match.
Also, the register list operands used a general error message,
even though we already have a dedicated error code for register
lists that are the wrong length.
---
gas/testsuite/gas/aarch64/illegal-sve2.l | 26 ++++++++++++------------
include/opcode/aarch64.h | 1 +
opcodes/aarch64-opc-2.c | 4 ++--
opcodes/aarch64-opc.c | 19 ++++++++---------
opcodes/aarch64-tbl.h | 4 ++--
5 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index d41f6f23ba5..995440627d1 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -248,8 +248,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
-[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
-[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b},#0'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; 2 registers are expected at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; 2 registers are expected at operand 2 -- `ext z0\.b,{z0\.b},#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
@@ -488,7 +488,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: histseg z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -515,7 +515,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -535,7 +535,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -556,7 +556,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -569,7 +569,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -582,7 +582,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -595,7 +595,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -2212,7 +2212,7 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssubwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: ssubwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
@@ -2233,7 +2233,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
@@ -2247,7 +2247,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
@@ -2268,7 +2268,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6615dec41a7..d09897f48d4 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -224,6 +224,7 @@ enum aarch64_operand_class
AARCH64_OPND_CLASS_SISD_REG,
AARCH64_OPND_CLASS_SIMD_REGLIST,
AARCH64_OPND_CLASS_SVE_REG,
+ AARCH64_OPND_CLASS_SVE_REGLIST,
AARCH64_OPND_CLASS_PRED_REG,
AARCH64_OPND_CLASS_ZA_ACCESS,
AARCH64_OPND_CLASS_ADDRESS,
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 3603f2c8c9b..2fa09b29d26 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -231,9 +231,9 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 6b9b19ffc57..dfffbf6f6e5 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1616,16 +1616,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
break;
- case AARCH64_OPND_SVE_ZnxN:
- case AARCH64_OPND_SVE_ZtxN:
- if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
- {
- set_other_error (mismatch_detail, idx,
- _("invalid register list"));
- return 0;
- }
- break;
-
case AARCH64_OPND_SME_PnT_Wm_imm:
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
@@ -1638,6 +1628,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_CLASS_SVE_REGLIST:
+ num = get_opcode_dependent_value (opcode);
+ if (opnd->reglist.num_regs != num)
+ {
+ set_reg_list_error (mismatch_detail, idx, num);
+ return 0;
+ }
+ break;
+
case AARCH64_OPND_CLASS_ZA_ACCESS:
switch (type)
{
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 98b2b01b2a2..77890fd0f14 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5902,11 +5902,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an SVE vector register") \
Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \
"an indexed SVE vector register") \
- Y(SVE_REG, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \
+ Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \
"a list of SVE vector registers") \
Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \
"an SVE vector register") \
- Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
+ Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
"a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
"an SME ZA tile ZA0-ZA3") \
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (29 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
` (11 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
AARCH64_OPDE_REG_LIST took a single operand that specified the
expected number of registers. However, there are quite a few
SME2 instructions that have both 2-register forms and (separate)
4-register forms. If the user tries to use a 3-register list,
it isn't obvious which opcode entry they meant. Saying that we
expect 2 registers and saying that we expect 4 registers would
both be wrong.
This patch therefore switches the operand to a bitfield. If a
AARCH64_OPDE_REG_LIST is reported against multiple opcode entries,
the patch ORs up the expected lengths.
This has no user-visible effect yet. A later patch adds more error
strings, alongside tests that use them.
---
gas/config/tc-aarch64.c | 54 ++++++++++++++++++++++++++---------------
opcodes/aarch64-opc.c | 2 +-
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 145e241b13b..a57cc2bc080 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4914,6 +4914,20 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
goto failure; \
} while (0)
\f
+/* A primitive log calculator. */
+
+static inline unsigned int
+get_log2 (unsigned int n)
+{
+ unsigned int count = 0;
+ while (n > 1)
+ {
+ n >>= 1;
+ count += 1;
+ }
+ return count;
+}
+
/* encode the 12-bit imm field of Add/sub immediate */
static inline uint32_t
encode_addsub_imm (uint32_t imm)
@@ -5732,14 +5746,17 @@ output_operand_error_record (const operand_error_record *record, char *str)
break;
case AARCH64_OPDE_REG_LIST:
- if (detail->data[0].i == 1)
+ if (detail->data[0].i == (1 << 1))
handler (_("invalid number of registers in the list; "
"only 1 register is expected at operand %d -- `%s'"),
idx + 1, str);
- else
+ else if ((detail->data[0].i & -detail->data[0].i) == detail->data[0].i)
handler (_("invalid number of registers in the list; "
"%d registers are expected at operand %d -- `%s'"),
- detail->data[0].i, idx + 1, str);
+ get_log2 (detail->data[0].i), idx + 1, str);
+ else
+ handler (_("invalid number of registers in the list"
+ " at operand %d -- `%s'"), idx + 1, str);
break;
case AARCH64_OPDE_UNALIGNED:
@@ -5807,6 +5824,12 @@ output_operand_error_report (char *str, bool non_fatal_only)
curr->detail.data[0].i, curr->detail.data[1].i,
curr->detail.data[2].i);
}
+ else if (curr->detail.kind == AARCH64_OPDE_REG_LIST)
+ {
+ DEBUG_TRACE ("\t%s [%x]",
+ operand_mismatch_kind_names[curr->detail.kind],
+ curr->detail.data[0].i);
+ }
else
{
DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
@@ -5847,6 +5870,13 @@ output_operand_error_report (char *str, bool non_fatal_only)
curr->detail.data[0].i, curr->detail.data[1].i,
curr->detail.data[2].i);
}
+ else if (kind == AARCH64_OPDE_REG_LIST)
+ {
+ record->detail.data[0].i |= curr->detail.data[0].i;
+ DEBUG_TRACE ("\t--> %s [%x]",
+ operand_mismatch_kind_names[kind],
+ curr->detail.data[0].i);
+ }
}
}
@@ -6191,22 +6221,6 @@ process_movw_reloc_info (void)
return true;
}
-/* A primitive log calculator. */
-
-static inline unsigned int
-get_logsz (unsigned int size)
-{
- const unsigned char ls[16] =
- {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
- if (size > 16)
- {
- gas_assert (0);
- return -1;
- }
- gas_assert (ls[size - 1] != (unsigned char)-1);
- return ls[size - 1];
-}
-
/* Determine and return the real reloc type code for an instruction
with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
@@ -6271,7 +6285,7 @@ ldst_lo12_determine_real_reloc_type (void)
1, opd0_qlf, 0);
gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
- logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
+ logsz = get_log2 (aarch64_get_qualifier_esize (opd1_qlf));
if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
|| inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index dfffbf6f6e5..590d227fde3 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1438,7 +1438,7 @@ set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
if (mismatch_detail == NULL)
return;
set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
- mismatch_detail->data[0].i = expected_num;
+ mismatch_detail->data[0].i = 1 << expected_num;
}
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 32/43] aarch64: Tweak register list errors
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (30 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
` (10 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
The error for invalid register lists had the form:
invalid number of registers in the list; N registers are expected at operand M -- `insn'
This seems a bit verbose. Also, the "bracketing" is really:
(invalid number of registers in the list; N registers are expected) at operand M
but the semicolon works against that.
This patch goes for slightly shorter messages, setting a template
that later patches can use for more complex cases.
---
gas/config/tc-aarch64.c | 6 ++----
gas/testsuite/gas/aarch64/diagnostic.l | 4 ++--
gas/testsuite/gas/aarch64/illegal-sve2.l | 26 +++++++++++------------
gas/testsuite/gas/aarch64/verbose-error.l | 2 +-
4 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index a57cc2bc080..0d2a04ddb16 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5747,12 +5747,10 @@ output_operand_error_record (const operand_error_record *record, char *str)
case AARCH64_OPDE_REG_LIST:
if (detail->data[0].i == (1 << 1))
- handler (_("invalid number of registers in the list; "
- "only 1 register is expected at operand %d -- `%s'"),
+ handler (_("expected a single-register list at operand %d -- `%s'"),
idx + 1, str);
else if ((detail->data[0].i & -detail->data[0].i) == detail->data[0].i)
- handler (_("invalid number of registers in the list; "
- "%d registers are expected at operand %d -- `%s'"),
+ handler (_("expected a list of %d registers at operand %d -- `%s'"),
get_log2 (detail->data[0].i), idx + 1, str);
else
handler (_("invalid number of registers in the list"
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 52365319283..6d59564a543 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -27,7 +27,7 @@
[^:]*:29: Error: shift amount out of range 0 to 31 at operand 3 -- `add w0,wzr,w7,asr#32'
[^:]*:30: Error: invalid post-increment amount at operand 2 -- `st2 \{v0.4s,v1.4s\},\[sp\],#24'
[^:]*:31: Error: invalid shift amount at operand 2 -- `ldr q0,\[x0,w0,uxtw#5\]'
-[^:]*:32: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
+[^:]*:32: Error: expected a list of 2 registers at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
[^:]*:33: Error: shift amount must be 0 or 12 at operand 3 -- `adds x1,sp,2134,lsl#4'
[^:]*:34: Error: shift amount must be a multiple of 16 at operand 2 -- `movz w0,2134,lsl#8'
[^:]*:35: Error: shift amount out of range 0 to 16 at operand 2 -- `movz w0,2134,lsl#32'
@@ -77,7 +77,7 @@
[^:]*:79: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm 0x2f,LABEL1'
[^:]*:80: Error: immediate value out of range 0 to 15 at operand 1 -- `dmb #16'
[^:]*:81: Error: immediate value out of range 0 to 31 at operand 2 -- `tbz w0,#40,0x17c'
-[^:]*:82: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
+[^:]*:82: Error: expected a list of 2 registers at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
[^:]*:83: Error: invalid register list at operand 1 -- `ld2 \{v1.4h,v0.4h\},\[x1\]'
[^:]*:84: Error: the specified option is not accepted in ISB at operand 1 -- `isb osh'
[^:]*:85: Error: invalid address at operand 2 -- `st2 \{v4.2d,v5.2d,v6.2d\},\\\[x3\\\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 995440627d1..551440f3741 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -248,8 +248,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; 2 registers are expected at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; 2 registers are expected at operand 2 -- `ext z0\.b,{z0\.b},#0'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b},#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
@@ -488,7 +488,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: histseg z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -515,7 +515,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -535,7 +535,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -556,7 +556,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -569,7 +569,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -582,7 +582,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -595,7 +595,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -2212,7 +2212,7 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssubwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: ssubwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
@@ -2233,7 +2233,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
@@ -2247,7 +2247,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
@@ -2268,7 +2268,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
diff --git a/gas/testsuite/gas/aarch64/verbose-error.l b/gas/testsuite/gas/aarch64/verbose-error.l
index 5696a5c4671..188dadfe87d 100644
--- a/gas/testsuite/gas/aarch64/verbose-error.l
+++ b/gas/testsuite/gas/aarch64/verbose-error.l
@@ -9,7 +9,7 @@
[^:]*:7: Error: invalid shift amount at operand 2 -- `strb w7,\[x30,x0,lsl#1\]'
[^:]*:8: Error: invalid addressing mode at operand 2 -- `st2 {v4.2d,v5.2d},\[x3,#3\]'
[^:]*:9: Error: the top half of a 128-bit FP/SIMD register is expected at operand 1 -- `fmov v1.D\[0\],x0'
-[^:]*:10: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ld1r \{v1.4s,v2.4s,v3.4s\},\[x3\],x4'
+[^:]*:10: Error: expected a single-register list at operand 1 -- `ld1r \{v1.4s,v2.4s,v3.4s\},\[x3\],x4'
[^:]*:11: Error: missing immediate expression at operand 1 -- `svc'
[^:]*:12: Error: operand mismatch -- `add v0.4s,v1.4s,v2.2s'
[^:]*:12: Info: did you mean this\?
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 33/43] aarch64: Try to report invalid variants against the closest match
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (31 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
` (9 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
If an instruction has invalid qualifiers, GAS would report the
error against the final opcode entry that got to the qualifier-
checking stage. It seems better to report the error against
the opcode entry that had the closest match, just like we
pick the closest match within an opcode entry for the
"did you mean this?" message.
This patch adds the number of invalid operands as an
argument to AARCH64_OPDE_INVALID_VARIANT and then picks the
AARCH64_OPDE_INVALID_VARIANT with the lowest argument.
---
gas/config/tc-aarch64.c | 4 +
gas/testsuite/gas/aarch64/illegal-sve2.l | 158 ++++++++++++-----------
gas/testsuite/gas/aarch64/sme-illegal.l | 24 ++--
gas/testsuite/gas/aarch64/sve-invalid.l | 8 +-
opcodes/aarch64-dis.c | 3 +-
opcodes/aarch64-opc.c | 44 ++++---
opcodes/aarch64-opc.h | 2 +-
7 files changed, 131 insertions(+), 112 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0d2a04ddb16..1851f83ad05 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5875,6 +5875,10 @@ output_operand_error_report (char *str, bool non_fatal_only)
operand_mismatch_kind_names[kind],
curr->detail.data[0].i);
}
+ /* Pick the variant with the cloest match. */
+ else if (kind == AARCH64_OPDE_INVALID_VARIANT
+ && record->detail.data[0].i > curr->detail.data[0].i)
+ record = curr;
}
}
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 551440f3741..369c0e6983a 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -159,7 +159,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cdot z0\.s,z0\.b,z0\.b\[4\],#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.d,z0\.b\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: cdot z0\.d, z0\.h, z0\.h\[0\], #0
+[^ :]+:[0-9]+: Info: cdot z0\.s, z0\.b, z0\.b\[0\], #0
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cdot z0\.s,z0\.b,z8\.b\[0\],#0'
@@ -197,7 +197,7 @@
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cmla z0\.s,z0\.s,z16\.s\[0\],#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.s,z0\.s,z0\.d\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: cmla z0\.h, z0\.h, z0\.h\[0\], #0
+[^ :]+:[0-9]+: Info: cmla z0\.s, z0\.s, z0\.s\[0\], #0
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `cmla z0\.s,z0\.s,z0\.s\[2\],#0'
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.s,z0\.s,z0\.s\[0\],#1'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.b,z0\.b,z0\.b,#0'
@@ -282,7 +282,7 @@
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/z,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Info: fcvtlt z0\.s, p0/m, z0\.h
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtlt z32\.d,p0/m,z0\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.d,p8/m,z0\.s'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtlt z0\.d,p0/m,z32\.s'
@@ -298,10 +298,10 @@
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.h,p0/m,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/m,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Info: fcvtnt z0\.h, p0/m, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/z,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Info: fcvtnt z0\.h, p0/m, z0\.s
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.s,p8/m,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.s,p0/m,z32\.d'
@@ -491,7 +491,7 @@
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Info: ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
@@ -538,7 +538,7 @@
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Info: ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
@@ -598,7 +598,7 @@
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Info: ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
@@ -638,20 +638,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mla z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mla z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mla z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mla z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mla z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mla z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mla z0\.d,z0\.d,z16\.d\[0\]'
@@ -668,20 +668,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mls z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mls z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mls z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mls z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mls z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mls z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mls z0\.d,z0\.d,z16\.d\[0\]'
@@ -698,20 +698,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mul z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mul z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mul z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.s,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.s,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.s,z0\.s,z8\.s\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mul z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mul z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: mul z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mul z0\.d,z0\.d,z16\.d\[0\]'
@@ -762,7 +762,9 @@
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullb z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d
+[^ :]+:[0-9]+: Info: pmullb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: pmullb z0\.d, z0\.s, z0\.s
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullt z32\.q,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullt z0\.q,z32\.d,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullt z0\.q,z0\.d,z32\.d'
@@ -774,7 +776,9 @@
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullt z0\.h,z0\.b,z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d
+[^ :]+:[0-9]+: Info: pmullt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: pmullt z0\.d, z0\.s, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `raddhnb z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: raddhnb z0\.b, z0\.h, z0\.h
@@ -1125,7 +1129,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: smlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: smlalb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalb z0\.d,z0\.s,z16\.s\[0\]'
@@ -1149,7 +1153,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: smlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: smlalt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalt z0\.d,z0\.s,z16\.s\[0\]'
@@ -1173,7 +1177,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: smlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: smlslb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslb z0\.d,z0\.s,z16\.s\[0\]'
@@ -1197,7 +1201,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: smlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: smlslt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslt z0\.d,z0\.s,z16\.s\[0\]'
@@ -1231,7 +1235,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: smullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: smullb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullb z0\.d,z0\.s,z16\.s\[0\]'
@@ -1255,7 +1259,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: smullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: smullt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullt z0\.d,z0\.s,z16\.s\[0\]'
@@ -1342,7 +1346,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: sqdmlalb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalb z0\.d,z0\.s,z16\.s\[0\]'
@@ -1376,7 +1380,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: sqdmlalt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalt z0\.d,z0\.s,z16\.s\[0\]'
@@ -1400,7 +1404,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: sqdmlslb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslb z0\.d,z0\.s,z16\.s\[0\]'
@@ -1434,7 +1438,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: sqdmlslt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslt z0\.d,z0\.s,z16\.s\[0\]'
@@ -1468,20 +1472,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmulh z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqdmulh z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqdmulh z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmulh z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqdmulh z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.h,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqdmulh z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqdmulh z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.h,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmulh z0\.h,z0\.b,z32\.b'
@@ -1499,7 +1503,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: sqdmullb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullb z0\.d,z0\.s,z16\.s\[0\]'
@@ -1523,7 +1527,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqdmullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: sqdmullt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullt z0\.d,z0\.s,z16\.s\[0\]'
@@ -1566,10 +1570,10 @@
[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#360'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.h,z0\.s\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
+[^ :]+:[0-9]+: Info: sqrdcmlah z0\.h, z0\.h, z0\.h\[0\], #0
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.s,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
+[^ :]+:[0-9]+: Info: sqrdcmlah z0\.h, z0\.h, z0\.h\[0\], #0
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z16\.s\[0\],#0'
@@ -1610,20 +1614,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlah z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlah z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlah z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlah z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlah z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.h,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlah z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlah z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.h,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmlah z0\.h,z0\.b,z32\.b'
@@ -1651,20 +1655,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlsh z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlsh z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.h,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlsh z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmlsh z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
@@ -1692,20 +1696,20 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmulh z0\.s,z0\.s,z0\.s\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.s\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmulh z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.s,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmulh z0\.s, z0\.s, z0\.s\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmulh z0\.d,z0\.d,z16\.d\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmulh z0\.d,z0\.d,z0\.d\[2\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.h,z0\.d\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmulh z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.d,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: sqrdmulh z0\.d, z0\.d, z0\.d\[0\]
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.h,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmulh z0\.h,z0\.b,z32\.b'
@@ -2215,7 +2219,7 @@
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Info: stnt1b {z0\.d}, p0, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
@@ -2250,7 +2254,7 @@
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Info: stnt1h {z0\.d}, p0, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
@@ -2271,7 +2275,7 @@
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Info: stnt1w {z0\.d}, p0, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
@@ -2558,7 +2562,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: umlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: umlalb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalb z0\.d,z0\.s,z16\.s\[0\]'
@@ -2582,7 +2586,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: umlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: umlalt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalt z0\.d,z0\.s,z16\.s\[0\]'
@@ -2606,7 +2610,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: umlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: umlslb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslb z0\.d,z0\.s,z16\.s\[0\]'
@@ -2630,7 +2634,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: umlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: umlslt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslt z0\.d,z0\.s,z16\.s\[0\]'
@@ -2665,7 +2669,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: umullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: umullb z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullb z0\.d,z0\.s,z16\.s\[0\]'
@@ -2689,7 +2693,7 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: umullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Info: umullt z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullt z0\.d,z0\.s,z16\.s\[0\]'
@@ -3159,11 +3163,11 @@
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: whilege p0\.b, x0, x0
+[^ :]+:[0-9]+: Info: whilege p0\.b, w0, w0
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0
-[^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0
-[^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0
+[^ :]+:[0-9]+: Info: whilege p0\.h, w0, w0
+[^ :]+:[0-9]+: Info: whilege p0\.s, w0, w0
+[^ :]+:[0-9]+: Info: whilege p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w31'
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,x0,x0'
@@ -3197,11 +3201,11 @@
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: whilegt p0\.b, x0, x0
+[^ :]+:[0-9]+: Info: whilegt p0\.b, w0, w0
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0
-[^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0
-[^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0
+[^ :]+:[0-9]+: Info: whilegt p0\.h, w0, w0
+[^ :]+:[0-9]+: Info: whilegt p0\.s, w0, w0
+[^ :]+:[0-9]+: Info: whilegt p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w31'
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,x0,x0'
@@ -3235,11 +3239,11 @@
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: whilehi p0\.b, x0, x0
+[^ :]+:[0-9]+: Info: whilehi p0\.b, w0, w0
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0
-[^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0
-[^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0
+[^ :]+:[0-9]+: Info: whilehi p0\.h, w0, w0
+[^ :]+:[0-9]+: Info: whilehi p0\.s, w0, w0
+[^ :]+:[0-9]+: Info: whilehi p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w31'
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,x0,x0'
@@ -3273,11 +3277,11 @@
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: whilehs p0\.b, x0, x0
+[^ :]+:[0-9]+: Info: whilehs p0\.b, w0, w0
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0
-[^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0
-[^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0
+[^ :]+:[0-9]+: Info: whilehs p0\.h, w0, w0
+[^ :]+:[0-9]+: Info: whilehs p0\.s, w0, w0
+[^ :]+:[0-9]+: Info: whilehs p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w31'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0\.b,w0,x0'
diff --git a/gas/testsuite/gas/aarch64/sme-illegal.l b/gas/testsuite/gas/aarch64/sme-illegal.l
index f8d05478cc6..69177ca8105 100644
--- a/gas/testsuite/gas/aarch64/sme-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-illegal.l
@@ -35,27 +35,27 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmopa za8.d,p0/m,p1/m,z1.d,z8.d'
[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.d,p2/m,p3/m,z2.s,z7.s'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: fmopa za0.d, p2/m, p3/m, z2.d, z7.d
+[^:]*:[0-9]+: Info: fmopa za0.s, p2/m, p3/m, z2.s, z7.s
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.h,z4.h'
[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za1.s,p2/m,p3/m,z2.q,z3.q'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: fmopa za1.d, p2/m, p3/m, z2.d, z3.d
+[^:]*:[0-9]+: Info: fmopa za1.s, p2/m, p3/m, z2.h, z3.h
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmops za4.s,p0/m,p1/m,z1.s,z4.s'
[^:]*:[0-9]+: Error: operand mismatch -- `fmops za1.s,p2/m,p3/m,z2.q,z3.q'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: fmops za1.d, p2/m, p3/m, z2.d, z3.d
+[^:]*:[0-9]+: Info: fmops za1.s, p2/m, p3/m, z2.h, z3.h
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmops za8.d,p0/m,p1/m,z1.d,z8.d'
[^:]*:[0-9]+: Error: operand mismatch -- `fmops za0.d,p2/m,p3/m,z2.s,z7.s'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: fmops za0.d, p2/m, p3/m, z2.d, z7.d
+[^:]*:[0-9]+: Info: fmops za0.s, p2/m, p3/m, z2.s, z7.s
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `fmops za8.s,p0/m,p1/m,z1.h,z4.h'
[^:]*:[0-9]+: Error: operand mismatch -- `fmops za1.q,p2/m,p3/m,z2.h,z3.h'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: fmops za1.d, p2/m, p3/m, z2.d, z3.d
+[^:]*:[0-9]+: Info: fmops za1.s, p2/m, p3/m, z2.h, z3.h
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smopa za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `smopa za1.q,p2/m,p3/m,z2.b,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: smopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: smopa za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smopa za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `smopa za1.d,p2/m,p3/m,z2.h,z7.q'
[^:]*:[0-9]+: Info: did you mean this\?
@@ -63,7 +63,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smops za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `smops za1.q,p2/m,p3/m,z2.b,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: smops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: smops za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `smops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `smops za1.d,p2/m,p3/m,z2.h,z7.q'
[^:]*:[0-9]+: Info: did you mean this\?
@@ -79,7 +79,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `sumops za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `sumops za1.q,p2/m,p3/m,z2.b,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: sumops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: sumops za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `sumops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `sumops za1.q,p2/m,p3/m,z2.h,z7.h'
[^:]*:[0-9]+: Info: did you mean this\?
@@ -87,7 +87,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umopa za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `umopa za1.q,p2/m,p3/m,z2.b,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: umopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: umopa za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umopa za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `umopa za1.q,p2/m,p3/m,z2.h,z7.h'
[^:]*:[0-9]+: Info: did you mean this\?
@@ -95,7 +95,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umops za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `umops za1.q,p2/m,p3/m,z2.b,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: umops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: umops za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `umops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `umops za1.d,p2/m,p3/m,z2.d,z7.d'
[^:]*:[0-9]+: Info: did you mean this\?
@@ -103,7 +103,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmopa za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `usmopa za1.q,p2/m,p3/m,z2.b,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: usmopa za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: usmopa za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmopa za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `usmopa za1.q,p2/m,p3/m,z2.h,z7.h'
[^:]*:[0-9]+: Info: did you mean this\?
@@ -111,7 +111,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmops za4.s,p0/m,p1/m,z1.b,z4.b'
[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.s,p2/m,p3/m,z2.s,z3.b'
[^:]*:[0-9]+: Info: did you mean this\?
-[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z3.h
+[^:]*:[0-9]+: Info: usmops za1.s, p2/m, p3/m, z2.b, z3.b
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `usmops za8.d,p0/m,p1/m,z1.h,z8.h'
[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.d,p2/m,p3/m,z2.d,z7.d'
[^:]*:[0-9]+: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index ca447307b9e..00352f88f52 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1165,13 +1165,13 @@
.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h\[0\]'
.*: Info: did you mean this\?
-.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
+.*: Info: sdot z0\.d, z1\.h, z2\.h\[0\]
.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s\[0\]'
.*: Info: did you mean this\?
.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d\[0\]'
.*: Info: did you mean this\?
-.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
+.*: Info: sdot z0\.d, z1\.h, z2\.h\[0\]
.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b'
.*: Info: did you mean this\?
.*: Info: udot z0\.s, z1\.b, z2\.b
@@ -1197,13 +1197,13 @@
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h\[0\]'
.*: Info: did you mean this\?
-.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Info: udot z0\.d, z1\.h, z2\.h\[0\]
.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s\[0\]'
.*: Info: did you mean this\?
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d\[0\]'
.*: Info: did you mean this\?
-.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Info: udot z0\.d, z1\.h, z2\.h\[0\]
.*: Error: syntax error in register list at operand 1 -- `ld2b {},p0/z,\[x0\]'
.*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]'
.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]'
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index eabcc9ee586..ddbeefa9d91 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -253,8 +253,9 @@ get_expected_qualifier (const aarch64_inst *inst, int i)
aarch64_opnd_qualifier_seq_t qualifiers;
/* Should not be called if the qualifier is known. */
assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
+ int invalid_count;
if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
- i, qualifiers))
+ i, qualifiers, &invalid_count))
return qualifiers[i];
else
return AARCH64_OPND_QLF_NIL;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 590d227fde3..b9029010c47 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -906,6 +906,9 @@ aarch64_num_of_operands (const aarch64_opcode *opcode)
/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
+ Store the smallest number of non-matching qualifiers in *INVALID_COUNT.
+ This is always 0 if the function succeeds.
+
N.B. on the entry, it is very likely that only some operands in *INST
have had their qualifiers been established.
@@ -928,16 +931,17 @@ aarch64_num_of_operands (const aarch64_opcode *opcode)
int
aarch64_find_best_match (const aarch64_inst *inst,
const aarch64_opnd_qualifier_seq_t *qualifiers_list,
- int stop_at, aarch64_opnd_qualifier_t *ret)
+ int stop_at, aarch64_opnd_qualifier_t *ret,
+ int *invalid_count)
{
- int found = 0;
- int i, num_opnds;
+ int i, num_opnds, invalid, min_invalid;
const aarch64_opnd_qualifier_t *qualifiers;
num_opnds = aarch64_num_of_operands (inst->opcode);
if (num_opnds == 0)
{
DEBUG_TRACE ("SUCCEED: no operand");
+ *invalid_count = 0;
return 1;
}
@@ -945,13 +949,14 @@ aarch64_find_best_match (const aarch64_inst *inst,
stop_at = num_opnds - 1;
/* For each pattern. */
+ min_invalid = num_opnds;
for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
{
int j;
qualifiers = *qualifiers_list;
/* Start as positive. */
- found = 1;
+ invalid = 0;
DEBUG_TRACE ("%d", i);
#ifdef DEBUG_AARCH64
@@ -963,10 +968,7 @@ aarch64_find_best_match (const aarch64_inst *inst,
qualifier sequence. (This matters for strict testing.) In other
positions an empty sequence acts as a terminator. */
if (i > 0 && empty_qualifier_sequence_p (qualifiers))
- {
- found = 0;
- break;
- }
+ break;
for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
{
@@ -989,21 +991,22 @@ aarch64_find_best_match (const aarch64_inst *inst,
if (operand_also_qualified_p (inst->operands + j, *qualifiers))
continue;
else
- {
- found = 0;
- break;
- }
+ invalid += 1;
}
else
continue; /* Equal qualifiers are certainly matched. */
}
+ if (min_invalid > invalid)
+ min_invalid = invalid;
+
/* Qualifiers established. */
- if (found == 1)
+ if (min_invalid == 0)
break;
}
- if (found == 1)
+ *invalid_count = min_invalid;
+ if (min_invalid == 0)
{
/* Fill the result in *RET. */
int j;
@@ -1033,17 +1036,21 @@ aarch64_find_best_match (const aarch64_inst *inst,
Return 1 if the operand qualifier(s) in *INST match one of the qualifier
sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
+ Store the smallest number of non-matching qualifiers in *INVALID_COUNT.
+ This is always 0 if the function succeeds.
+
if UPDATE_P, update the qualifier(s) in *INST after the matching
succeeds. */
static int
-match_operands_qualifier (aarch64_inst *inst, bool update_p)
+match_operands_qualifier (aarch64_inst *inst, bool update_p,
+ int *invalid_count)
{
int i;
aarch64_opnd_qualifier_seq_t qualifiers;
if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
- qualifiers))
+ qualifiers, invalid_count))
{
DEBUG_TRACE ("matching FAIL");
return 0;
@@ -2893,7 +2900,9 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
constraint checking will carried out by operand_general_constraint_met_p,
which has be to called after this in order to get all of the operands'
qualifiers established. */
- if (match_operands_qualifier (inst, true /* update_p */) == 0)
+ int invalid_count;
+ if (match_operands_qualifier (inst, true /* update_p */,
+ &invalid_count) == 0)
{
DEBUG_TRACE ("FAIL on operand qualifier matching");
if (mismatch_detail)
@@ -2904,6 +2913,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
mismatch_detail->index = -1;
mismatch_detail->error = NULL;
+ mismatch_detail->data[0].i = invalid_count;
}
return 0;
}
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 377b4720188..2bbc81e66bb 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -366,7 +366,7 @@ unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
int aarch64_find_best_match (const aarch64_inst *,
const aarch64_opnd_qualifier_seq_t *,
- int, aarch64_opnd_qualifier_t *);
+ int, aarch64_opnd_qualifier_t *, int *);
static inline void
reset_operand_qualifier (aarch64_inst *inst, int idx)
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (32 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
` (8 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
There are three main kinds of error reported during parsing,
in increasing order of priority:
- AARCH64_OPDE_RECOVERABLE (register seen instead of immediate)
- AARCH64_OPDE_SYNTAX_ERROR
- AARCH64_OPDE_FATAL_SYNTAX_ERROR
This priority makes sense when comparing errors reported against the
same operand. But if we get to operand 3 (say) and see a register
instead of an immediate, that's likely to be a better match than
something that fails with a syntax error at operand 1.
The idea of this patch is to prioritise parsing-related errors
based on operand index first, then by error code. Post-parsing
errors still win over parsing errors, and their relative priorities
don't change.
---
gas/config/tc-aarch64.c | 50 ++++++++++++++++++++---
gas/testsuite/gas/aarch64/sme-8-illegal.l | 12 +++---
2 files changed, 51 insertions(+), 11 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 1851f83ad05..c8e37623d9e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5769,6 +5769,44 @@ output_operand_error_record (const operand_error_record *record, char *str)
}
}
+/* Return true if the presence of error A against an instruction means
+ that error B should not be reported. This is only used as a first pass,
+ to pick the kind of error that we should report. */
+
+static bool
+better_error_p (operand_error_record *a, operand_error_record *b)
+{
+ /* For errors reported during parsing, prefer errors that relate to
+ later operands, since that implies that the earlier operands were
+ syntactically valid.
+
+ For example, if we see a register R instead of an immediate in
+ operand N, we'll report that as a recoverable "immediate operand
+ required" error. This is because there is often another opcode
+ entry that accepts a register operand N, and any errors about R
+ should be reported against the register forms of the instruction.
+ But if no such register form exists, the recoverable error should
+ still win over a syntax error against operand N-1.
+
+ For these purposes, count an error reported at the end of the
+ assembly string as equivalent to an error reported against the
+ final operand. This means that opcode entries that expect more
+ operands win over "unexpected characters following instruction". */
+ if (a->detail.kind <= AARCH64_OPDE_FATAL_SYNTAX_ERROR
+ && b->detail.kind <= AARCH64_OPDE_FATAL_SYNTAX_ERROR)
+ {
+ int a_index = (a->detail.index < 0
+ ? aarch64_num_of_operands (a->opcode) - 1
+ : a->detail.index);
+ int b_index = (b->detail.index < 0
+ ? aarch64_num_of_operands (b->opcode) - 1
+ : b->detail.index);
+ if (a_index != b_index)
+ return a_index > b_index;
+ }
+ return operand_error_higher_severity_p (a->detail.kind, b->detail.kind);
+}
+
/* Process and output the error message about the operand mismatching.
When this function is called, the operand error information had
@@ -5787,7 +5825,7 @@ output_operand_error_report (char *str, bool non_fatal_only)
enum aarch64_operand_error_kind kind;
operand_error_record *curr;
operand_error_record *head = operand_error_report.head;
- operand_error_record *record = NULL;
+ operand_error_record *record;
/* No error to report. */
if (head == NULL)
@@ -5811,7 +5849,7 @@ output_operand_error_report (char *str, bool non_fatal_only)
/* Find the error kind of the highest severity. */
DEBUG_TRACE ("multiple opcode entries with error kind");
- kind = AARCH64_OPDE_NIL;
+ record = NULL;
for (curr = head; curr != NULL; curr = curr->next)
{
gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
@@ -5832,14 +5870,16 @@ output_operand_error_report (char *str, bool non_fatal_only)
{
DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
}
- if (operand_error_higher_severity_p (curr->detail.kind, kind)
- && (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
- kind = curr->detail.kind;
+ if ((!non_fatal_only || curr->detail.non_fatal)
+ && (!record || better_error_p (curr, record)))
+ record = curr;
}
+ kind = (record ? record->detail.kind : AARCH64_OPDE_NIL);
gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
/* Pick up one of errors of KIND to report. */
+ record = NULL;
for (curr = head; curr != NULL; curr = curr->next)
{
/* If we don't want to print non-fatal errors then don't consider them
diff --git a/gas/testsuite/gas/aarch64/sme-8-illegal.l b/gas/testsuite/gas/aarch64/sme-8-illegal.l
index ee9f76f3b9c..7123e8d9eac 100644
--- a/gas/testsuite/gas/aarch64/sme-8-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-8-illegal.l
@@ -1,7 +1,7 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart x0'
-[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart sa'
-[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart zm'
-[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop x0'
-[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop sa'
-[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop zm'
+[^:]*:[0-9]+: Error: unknown or missing PSTATE field name at operand 1 -- `smstart x0'
+[^:]*:[0-9]+: Error: unknown or missing PSTATE field name at operand 1 -- `smstart sa'
+[^:]*:[0-9]+: Error: unknown or missing PSTATE field name at operand 1 -- `smstart zm'
+[^:]*:[0-9]+: Error: unknown or missing PSTATE field name at operand 1 -- `smstop x0'
+[^:]*:[0-9]+: Error: unknown or missing PSTATE field name at operand 1 -- `smstop sa'
+[^:]*:[0-9]+: Error: unknown or missing PSTATE field name at operand 1 -- `smstop zm'
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (33 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
` (7 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch renames the OP_SME_* macros in aarch64-tbl.h so that
they follow the same scheme as the OP_SVE_* ones. It also uses
OP_SVE_ as the prefix, since there is no real distinction between
the SVE and SME uses of qualifiers: a macro defined for one can
be useful for the other too.
---
opcodes/aarch64-tbl.h | 158 ++++++++++++++++++++----------------------
1 file changed, 77 insertions(+), 81 deletions(-)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 77890fd0f14..7fcc347c3b9 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1438,10 +1438,12 @@
- U: the operand is unqualified (NIL).
- - [BHSD]: the operand has a S_[BHSD] qualifier and the choice of
- qualifier is the same for all variants. This is used for both
- .[BHSD] suffixes on an SVE predicate or vector register and
- scalar FPRs of the form [BHSD]<number>.
+ - [BHSDQ]: the operand has a S_[BHSDQ] qualifier and the choice of
+ qualifier is the same for all variants. This is used for:
+
+ - .[BHSDQ] suffixes on an SVE vector or predicate
+ - .[BHSDQ] suffixes on an SME ZA operand
+ - vector registers and scalar FPRs of the form [BHSDQ]<number>
- [WX]: the operand has a [WX] qualifier and the choice of qualifier
is the same for all variants.
@@ -1450,7 +1452,8 @@
is the same for all variants.
- V: the operand has a S_[BHSD] qualifier and the choice of qualifier
- is not the same for all variants.
+ is not the same for all variants. This is used for the same kinds
+ of operand as [BHSDQ] above.
- R: the operand has a [WX] qualifier and the choice of qualifier is
not the same for all variants.
@@ -1532,6 +1535,18 @@
{ \
QLF3(S_D,S_D,S_D), \
}
+#define OP_SVE_DMMD \
+{ \
+ QLF4(S_D,P_M,P_M,S_D), \
+}
+#define OP_SVE_DMMDD \
+{ \
+ QLF5(S_D,P_M,P_M,S_D,S_D) \
+}
+#define OP_SVE_DMMHH \
+{ \
+ QLF5(S_D,P_M,P_M,S_H,S_H) \
+}
#define OP_SVE_QQQ \
{ \
QLF3(S_Q,S_Q,S_Q), \
@@ -1656,6 +1671,22 @@
{ \
QLF3(S_S,P_M,S_D), \
}
+#define OP_SVE_SMMBB \
+{ \
+ QLF5(S_S,P_M,P_M,S_B,S_B) \
+}
+#define OP_SVE_SMMHH \
+{ \
+ QLF5(S_S,P_M,P_M,S_H,S_H), \
+}
+#define OP_SVE_SMMS \
+{ \
+ QLF4(S_S,P_M,P_M,S_S), \
+}
+#define OP_SVE_SMMSS \
+{ \
+ QLF5(S_S,P_M,P_M,S_S,S_S) \
+}
#define OP_SVE_SSS \
{ \
QLF3(S_S,S_S,S_S), \
@@ -1787,6 +1818,14 @@
QLF3(S_S,P_M,S_S), \
QLF3(S_D,P_M,S_D), \
}
+#define OP_SVE_VMV_BHSDQ \
+{ \
+ QLF3(S_B,P_M,S_B), \
+ QLF3(S_H,P_M,S_H), \
+ QLF3(S_S,P_M,S_S), \
+ QLF3(S_D,P_M,S_D), \
+ QLF3(S_Q,P_M,S_Q) \
+}
#define OP_SVE_VMV_HSD \
{ \
QLF3(S_H,P_M,S_H), \
@@ -2196,49 +2235,6 @@
{ \
QLF3(X,X,NIL), \
}
-/* e.g. ADDVA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S */
-#define OP_SME_ZADA_PN_PM_ZN_S \
-{ \
- QLF4(S_S,P_M,P_M,S_S), \
-}
-/* e.g. ADDVA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D */
-#define OP_SME_ZADA_PN_PM_ZN_D \
-{ \
- QLF4(S_D,P_M,P_M,S_D), \
-}
-/* e.g. BFMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H */
-#define OP_SME_ZADA_PN_PM_ZN_ZM \
-{ \
- QLF5(S_S,P_M,P_M,S_H,S_H), \
-}
-#define OP_SME_ZADA_S_PM_PM_S_S \
-{ \
- QLF5(S_S,P_M,P_M,S_S,S_S) \
-}
-#define OP_SME_ZADA_D_PM_PM_D_D \
-{ \
- QLF5(S_D,P_M,P_M,S_D,S_D) \
-}
-#define OP_SME_ZADA_S_PM_PM_H_H \
-{ \
- QLF5(S_S,P_M,P_M,S_H,S_H) \
-}
-#define OP_SME_ZADA_S_PM_PM_B_B \
-{ \
- QLF5(S_S,P_M,P_M,S_B,S_B) \
-}
-#define OP_SME_ZADA_D_PM_PM_H_H \
-{ \
- QLF5(S_D,P_M,P_M,S_H,S_H) \
-}
-#define OP_SME_BHSDQ_PM_BHSDQ \
-{ \
- QLF3(S_B,P_M,S_B), \
- QLF3(S_H,P_M,S_H), \
- QLF3(S_S,P_M,S_S), \
- QLF3(S_D,P_M,S_D), \
- QLF3(S_Q,P_M,S_Q) \
-}
/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */
#define QL_V3DOT \
@@ -5206,42 +5202,42 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
/* SME instructions. */
- SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0),
- SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0),
+ SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0),
+ SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0),
SME_INSN ("addspl", 0x04605800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
SME_INSN ("addsvl", 0x04205800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
- SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0),
- SME_I16I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0),
- SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0),
- SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0),
- SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0),
- SME_F64F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0),
- SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0),
- SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0),
- SME_F64F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0),
- SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0),
+ SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0),
+ SME_I16I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0),
+ SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
+ SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
+ SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0),
+ SME_F64F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMDD, 0, 0),
+ SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
+ SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0),
+ SME_F64F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMDD, 0, 0),
+ SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
SME_INSN ("rdsvl", 0x04bf5800, 0xfffff800, sme_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0),
- SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
- SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
- SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
-
- SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+ SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
+
+ SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0),
SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (34 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
` (6 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch just moves some out-of-order-looking OP_SVE_* macros.
---
opcodes/aarch64-tbl.h | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7fcc347c3b9..8deeded05e5 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1547,10 +1547,6 @@
{ \
QLF5(S_D,P_M,P_M,S_H,S_H) \
}
-#define OP_SVE_QQQ \
-{ \
- QLF3(S_Q,S_Q,S_Q), \
-}
#define OP_SVE_DDDD \
{ \
QLF4(S_D,S_D,S_D,S_D), \
@@ -1559,10 +1555,6 @@
{ \
QLF3(S_D,P_M,S_D), \
}
-#define OP_SVE_QMQ \
-{ \
- QLF3(S_Q,P_M,S_Q), \
-}
#define OP_SVE_DMH \
{ \
QLF3(S_D,P_M,S_H), \
@@ -1583,10 +1575,6 @@
{ \
QLF3(S_D,NIL,NIL), \
}
-#define OP_SVE_QUU \
-{ \
- QLF3(S_Q,NIL,NIL), \
-}
#define OP_SVE_DUV_BHS \
{ \
QLF3(S_D,NIL,S_B), \
@@ -1608,10 +1596,6 @@
{ \
QLF3(S_D,P_Z,NIL), \
}
-#define OP_SVE_QZU \
-{ \
- QLF3(S_Q,P_Z,NIL), \
-}
#define OP_SVE_HB \
{ \
QLF2(S_H,S_B), \
@@ -1648,6 +1632,22 @@
{ \
QLF3(S_H,P_Z,NIL), \
}
+#define OP_SVE_QMQ \
+{ \
+ QLF3(S_Q,P_M,S_Q), \
+}
+#define OP_SVE_QQQ \
+{ \
+ QLF3(S_Q,S_Q,S_Q), \
+}
+#define OP_SVE_QUU \
+{ \
+ QLF3(S_Q,NIL,NIL), \
+}
+#define OP_SVE_QZU \
+{ \
+ QLF3(S_Q,P_Z,NIL), \
+}
#define OP_SVE_RR \
{ \
QLF2(W,W), \
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (35 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
` (5 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Quite a lot of SME2 instructions have an opcode bit that selects
between 32-bit and 64-bit forms of an instruction, with the 32-bit
forms being part of base SME2 and with the 64-bit forms being part
of an optional extension. It's nevertheless useful to have a single
opcode entry for both forms since (a) that matches the ISA definition
and (b) it tends to improve error reporting.
This patch therefore adds a libopcodes function called
aarch64_cpu_supports_inst_p that tests whether the target
supports a particular instruction. In future it will depend
on internal libopcodes routines.
---
gas/config/tc-aarch64.c | 3 +--
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-opc.c | 13 +++++++++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c8e37623d9e..71b63d3f7b3 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8116,8 +8116,7 @@ md_assemble (char *str)
&& do_encode (inst_base->opcode, &inst.base, &inst_base->value))
{
/* Check that this instruction is supported for this CPU. */
- if (!opcode->avariant
- || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
+ if (!aarch64_cpu_supports_inst_p (cpu_variant, inst_base))
{
as_bad (_("selected processor does not support `%s'"), str);
return;
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d09897f48d4..61afe561a12 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1471,6 +1471,9 @@ aarch64_get_operand_desc (enum aarch64_opnd);
extern bool
aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
+extern bool
+aarch64_cpu_supports_inst_p (uint64_t, aarch64_inst *);
+
#ifdef DEBUG_AARCH64
extern int debug_dump;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index b9029010c47..7a88c19633d 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -6158,6 +6158,19 @@ aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
return svalue < -128 || svalue >= 128;
}
+/* Return true if a CPU with the AARCH64_FEATURE_* bits in CPU_VARIANT
+ supports the instruction described by INST. */
+
+bool
+aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst)
+{
+ if (!inst->opcode->avariant
+ || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avariant))
+ return false;
+
+ return true;
+}
+
/* Include the opcode description table as well as the operand description
table. */
#define VERIFIER(x) verify_##x
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (36 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
` (4 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
In GAS, the vector and predicate registers are identified by
REG_TYPE_VN, REG_TYPE_ZN and REG_TYPE_PN. This "N" is obviously
a placeholder for the register number. However, we don't use that
convention for integer and FP registers, and (more importantly)
SME2 adds "predicate-as-counter" registers that are denoted PN.
This patch therefore drops the "N" suffix from the existing
registers. The main hitch is that Z was also used for the
zero register in things like R_Z, but using ZR seems more
consistent with the SP-based names.
---
gas/config/tc-aarch64.c | 142 ++++++++++++++++++++--------------------
1 file changed, 71 insertions(+), 71 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 71b63d3f7b3..c6cc654095e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -297,16 +297,16 @@ struct reloc_entry
BASIC_REG_TYPE(R_64) /* x[0-30] */ \
BASIC_REG_TYPE(SP_32) /* wsp */ \
BASIC_REG_TYPE(SP_64) /* sp */ \
- BASIC_REG_TYPE(Z_32) /* wzr */ \
- BASIC_REG_TYPE(Z_64) /* xzr */ \
+ BASIC_REG_TYPE(ZR_32) /* wzr */ \
+ BASIC_REG_TYPE(ZR_64) /* xzr */ \
BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
- BASIC_REG_TYPE(VN) /* v[0-31] */ \
- BASIC_REG_TYPE(ZN) /* z[0-31] */ \
- BASIC_REG_TYPE(PN) /* p[0-15] */ \
+ BASIC_REG_TYPE(V) /* v[0-31] */ \
+ BASIC_REG_TYPE(Z) /* z[0-31] */ \
+ BASIC_REG_TYPE(P) /* p[0-15] */ \
BASIC_REG_TYPE(ZA) /* za */ \
BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
@@ -315,48 +315,48 @@ struct reloc_entry
MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
/* Typecheck: same, plus SVE registers. */ \
MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
- | REG_TYPE(ZN)) \
+ | REG_TYPE(Z)) \
/* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
- MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
- | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ MULTI_REG_TYPE(R_ZR, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
/* Typecheck: same, plus SVE registers. */ \
MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
- | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
- | REG_TYPE(ZN)) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) \
+ | REG_TYPE(Z)) \
/* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
/* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
- MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ MULTI_REG_TYPE(R_ZR_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
- | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
/* Typecheck: any [BHSDQ]P FP. */ \
MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
/* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
- MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
- | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
+ MULTI_REG_TYPE(R_ZR_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
/* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
be used for SVE instructions, since Zn and Pn are valid symbols \
in other contexts. */ \
- MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
- | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
- | REG_TYPE(ZN) | REG_TYPE(PN)) \
+ | REG_TYPE(Z) | REG_TYPE(P)) \
/* Any integer register; used for error messages only. */ \
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
- | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
/* Any vector register. */ \
- MULTI_REG_TYPE(VZ, REG_TYPE(VN) | REG_TYPE(ZN)) \
+ MULTI_REG_TYPE(VZ, REG_TYPE(V) | REG_TYPE(Z)) \
/* An SVE vector or predicate register. */ \
- MULTI_REG_TYPE(ZP, REG_TYPE(ZN) | REG_TYPE(PN)) \
+ MULTI_REG_TYPE(ZP, REG_TYPE(Z) | REG_TYPE(P)) \
/* Any vector or predicate register. */ \
- MULTI_REG_TYPE(VZP, REG_TYPE(VN) | REG_TYPE(ZN) | REG_TYPE(PN)) \
+ MULTI_REG_TYPE(VZP, REG_TYPE(V) | REG_TYPE(Z) | REG_TYPE(P)) \
/* The whole of ZA or a single tile. */ \
MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
/* A horizontal or vertical slice of a ZA tile. */ \
@@ -443,7 +443,7 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
/* Integer, zero and stack registers. */
if (mask == reg_type_masks[REG_TYPE_R_64])
return N_("expected a 64-bit integer register at operand %d");
- if (mask == reg_type_masks[REG_TYPE_R_Z])
+ if (mask == reg_type_masks[REG_TYPE_R_ZR])
return N_("expected an integer or zero register at operand %d");
if (mask == reg_type_masks[REG_TYPE_R_SP])
return N_("expected an integer or stack pointer register at operand %d");
@@ -452,11 +452,11 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
if (mask == reg_type_masks[REG_TYPE_BHSDQ])
return N_("expected a scalar SIMD or floating-point register"
" at operand %d");
- if (mask == reg_type_masks[REG_TYPE_VN])
+ if (mask == reg_type_masks[REG_TYPE_V])
return N_("expected an Advanced SIMD vector register at operand %d");
- if (mask == reg_type_masks[REG_TYPE_ZN])
+ if (mask == reg_type_masks[REG_TYPE_Z])
return N_("expected an SVE vector register at operand %d");
- if (mask == reg_type_masks[REG_TYPE_PN])
+ if (mask == reg_type_masks[REG_TYPE_P])
return N_("expected an SVE predicate register at operand %d");
if (mask == reg_type_masks[REG_TYPE_VZ])
return N_("expected a vector register at operand %d");
@@ -476,22 +476,22 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
return N_("expected a ZA tile slice at operand %d");
/* Integer and vector combos. */
- if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VN]))
+ if (mask == (reg_type_masks[REG_TYPE_R_ZR] | reg_type_masks[REG_TYPE_V]))
return N_("expected an integer register or Advanced SIMD vector register"
" at operand %d");
- if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_ZN]))
+ if (mask == (reg_type_masks[REG_TYPE_R_ZR] | reg_type_masks[REG_TYPE_Z]))
return N_("expected an integer register or SVE vector register"
" at operand %d");
- if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZ]))
+ if (mask == (reg_type_masks[REG_TYPE_R_ZR] | reg_type_masks[REG_TYPE_VZ]))
return N_("expected an integer or vector register at operand %d");
- if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_PN]))
+ if (mask == (reg_type_masks[REG_TYPE_R_ZR] | reg_type_masks[REG_TYPE_P]))
return N_("expected an integer or predicate register at operand %d");
- if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZP]))
+ if (mask == (reg_type_masks[REG_TYPE_R_ZR] | reg_type_masks[REG_TYPE_VZP]))
return N_("expected an integer, vector or predicate register"
" at operand %d");
/* SVE and SME combos. */
- if (mask == (reg_type_masks[REG_TYPE_ZN] | reg_type_masks[REG_TYPE_ZATHV]))
+ if (mask == (reg_type_masks[REG_TYPE_Z] | reg_type_masks[REG_TYPE_ZATHV]))
return N_("expected an SVE vector register or ZA tile slice"
" at operand %d");
@@ -902,12 +902,12 @@ inherent_reg_qualifier (const reg_entry *reg)
{
case REG_TYPE_R_32:
case REG_TYPE_SP_32:
- case REG_TYPE_Z_32:
+ case REG_TYPE_ZR_32:
return AARCH64_OPND_QLF_W;
case REG_TYPE_R_64:
case REG_TYPE_SP_64:
- case REG_TYPE_Z_64:
+ case REG_TYPE_ZR_64:
return AARCH64_OPND_QLF_X;
case REG_TYPE_FP_B:
@@ -949,8 +949,8 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
switch (reg->type)
{
- case REG_TYPE_ZN:
- if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) == 0
+ case REG_TYPE_Z:
+ if ((reg_type_masks[reg_type] & (1 << REG_TYPE_Z)) == 0
|| str[0] != '.')
return NULL;
switch (TOLOWER (str[1]))
@@ -968,7 +968,7 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
break;
default:
- if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
+ if (!aarch64_check_reg_type (reg, REG_TYPE_R_ZR_SP))
return NULL;
*qualifier = inherent_reg_qualifier (reg);
break;
@@ -988,7 +988,7 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
static const reg_entry *
aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
{
- return aarch64_addr_reg_parse (ccp, REG_TYPE_R_Z_SP, qualifier);
+ return aarch64_addr_reg_parse (ccp, REG_TYPE_R_ZR_SP, qualifier);
}
/* Parse the qualifier of a vector register or vector element of type
@@ -1011,7 +1011,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
gas_assert (*ptr == '.');
ptr++;
- if (reg_type != REG_TYPE_VN || !ISDIGIT (*ptr))
+ if (reg_type != REG_TYPE_V || !ISDIGIT (*ptr))
{
width = 0;
goto elt_size;
@@ -1043,7 +1043,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
element_size = 64;
break;
case 'q':
- if (reg_type != REG_TYPE_VN || width == 1)
+ if (reg_type != REG_TYPE_V || width == 1)
{
type = NT_q;
element_size = 128;
@@ -1118,15 +1118,15 @@ aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
{
switch (type)
{
- case REG_TYPE_VN:
- case REG_TYPE_ZN:
+ case REG_TYPE_V:
+ case REG_TYPE_Z:
case REG_TYPE_ZA:
case REG_TYPE_ZAT:
case REG_TYPE_ZATH:
case REG_TYPE_ZATV:
return ch == '.';
- case REG_TYPE_PN:
+ case REG_TYPE_P:
return ch == '.' || ch == '/';
default:
@@ -1237,7 +1237,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
/* Register if of the form Vn.[bhsdq]. */
is_typed_vecreg = true;
- if (type != REG_TYPE_VN)
+ if (type != REG_TYPE_V)
{
/* The width is always variable; we don't allow an integer width
to be specified. */
@@ -1288,7 +1288,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
}
/* A vector reg Vn should be typed or indexed. */
- if (type == REG_TYPE_VN && atype.defined == 0)
+ if (type == REG_TYPE_V && atype.defined == 0)
{
first_error (_("invalid use of vector register"));
}
@@ -1397,7 +1397,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
}
val = reg->number;
/* reject [bhsd]n */
- if (type == REG_TYPE_VN && typeinfo.defined == 0)
+ if (type == REG_TYPE_V && typeinfo.defined == 0)
{
set_first_syntax_error (_("invalid scalar register in list"));
error = true;
@@ -3700,9 +3700,9 @@ parse_shifter_operand (char **str, aarch64_opnd_info *operand,
return false;
}
- if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
+ if (!aarch64_check_reg_type (reg, REG_TYPE_R_ZR))
{
- set_expected_reg_error (REG_TYPE_R_Z, reg, 0);
+ set_expected_reg_error (REG_TYPE_R_ZR, reg, 0);
return false;
}
@@ -4176,7 +4176,7 @@ parse_address (char **str, aarch64_opnd_info *operand)
{
aarch64_opnd_qualifier_t base_qualifier, offset_qualifier;
return parse_address_main (str, operand, &base_qualifier, &offset_qualifier,
- REG_TYPE_R64_SP, REG_TYPE_R_Z, SHIFTED_NONE);
+ REG_TYPE_R64_SP, REG_TYPE_R_ZR, SHIFTED_NONE);
}
/* Parse an address in which SVE vector registers and MUL VL are allowed.
@@ -6401,9 +6401,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
AARCH64_FEATURE_SVE
| AARCH64_FEATURE_SVE2))
- imm_reg_type = REG_TYPE_R_Z_SP_BHSDQ_VZP;
+ imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP;
else
- imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
+ imm_reg_type = REG_TYPE_R_ZR_BHSDQ_V;
for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
{
@@ -6450,7 +6450,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
case AARCH64_OPND_SVE_Rm:
- po_int_fp_reg_or_fail (REG_TYPE_R_Z);
+ po_int_fp_reg_or_fail (REG_TYPE_R_ZR);
/* In LS64 load/store instructions Rt register number must be even
and <=22. */
@@ -6520,7 +6520,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Pn:
case AARCH64_OPND_SVE_Pt:
case AARCH64_OPND_SME_Pm:
- reg_type = REG_TYPE_PN;
+ reg_type = REG_TYPE_P;
goto vector_reg;
case AARCH64_OPND_SVE_Za_5:
@@ -6530,14 +6530,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm_16:
case AARCH64_OPND_SVE_Zn:
case AARCH64_OPND_SVE_Zt:
- reg_type = REG_TYPE_ZN;
+ reg_type = REG_TYPE_Z;
goto vector_reg;
case AARCH64_OPND_Va:
case AARCH64_OPND_Vd:
case AARCH64_OPND_Vn:
case AARCH64_OPND_Vm:
- reg_type = REG_TYPE_VN;
+ reg_type = REG_TYPE_V;
vector_reg:
reg = aarch64_reg_parse (&str, reg_type, &vectype);
if (!reg)
@@ -6546,9 +6546,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
info->reg.regno = reg->number;
- if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN)
+ if ((reg_type == REG_TYPE_P || reg_type == REG_TYPE_Z)
&& vectype.type == NT_invtype)
- /* Unqualified Pn and Zn registers are allowed in certain
+ /* Unqualified P and Z registers are allowed in certain
contexts. Rely on F_STRICT qualifier checking to catch
invalid uses. */
info->qualifier = AARCH64_OPND_QLF_NIL;
@@ -6562,7 +6562,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_VdD1:
case AARCH64_OPND_VnD1:
- reg = aarch64_reg_parse (&str, REG_TYPE_VN, &vectype);
+ reg = aarch64_reg_parse (&str, REG_TYPE_V, &vectype);
if (!reg)
goto failure;
if (vectype.type != NT_d || vectype.index != 1)
@@ -6585,7 +6585,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
- reg_type = REG_TYPE_ZN;
+ reg_type = REG_TYPE_Z;
goto vector_reg_index;
case AARCH64_OPND_Ed:
@@ -6593,7 +6593,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_SM3_IMM2:
- reg_type = REG_TYPE_VN;
+ reg_type = REG_TYPE_V;
vector_reg_index:
reg = aarch64_reg_parse (&str, reg_type, &vectype);
if (!reg)
@@ -6610,16 +6610,16 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
- reg_type = REG_TYPE_ZN;
+ reg_type = REG_TYPE_Z;
goto vector_reg_list;
case AARCH64_OPND_LVn:
case AARCH64_OPND_LVt:
case AARCH64_OPND_LVt_AL:
case AARCH64_OPND_LEt:
- reg_type = REG_TYPE_VN;
+ reg_type = REG_TYPE_V;
vector_reg_list:
- if (reg_type == REG_TYPE_ZN
+ if (reg_type == REG_TYPE_Z
&& get_opcode_dependent_value (opcode) == 1
&& *str != '{')
{
@@ -6664,7 +6664,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
if (!(vectype.defined & NTA_HASTYPE))
{
- if (reg_type == REG_TYPE_ZN)
+ if (reg_type == REG_TYPE_Z)
set_fatal_syntax_error (_("missing type suffix"));
goto failure;
}
@@ -6824,8 +6824,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_IMM_MOV:
{
char *saved = str;
- if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
- reg_name_p (str, REG_TYPE_VN))
+ if (reg_name_p (str, REG_TYPE_R_ZR_SP)
+ || reg_name_p (str, REG_TYPE_V))
goto failure;
str = saved;
po_misc_or_fail (aarch64_get_expression (&inst.reloc.exp, &str,
@@ -7279,7 +7279,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_PnT_Wm_imm:
- if (!parse_dual_indexed_reg (&str, REG_TYPE_PN,
+ if (!parse_dual_indexed_reg (&str, REG_TYPE_P,
&info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
@@ -8245,8 +8245,8 @@ static const reg_entry reg_names[] = {
REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
- REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
- REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
+ REGDEF (wzr, 31, ZR_32), REGDEF (WZR, 31, ZR_32),
+ REGDEF (xzr, 31, ZR_64), REGDEF (XZR, 31, ZR_64),
/* Floating-point single precision registers. */
REGSET (s, FP_S), REGSET (S, FP_S),
@@ -8264,13 +8264,13 @@ static const reg_entry reg_names[] = {
REGSET (q, FP_Q), REGSET (Q, FP_Q),
/* FP/SIMD registers. */
- REGSET (v, VN), REGSET (V, VN),
+ REGSET (v, V), REGSET (V, V),
/* SVE vector registers. */
- REGSET (z, ZN), REGSET (Z, ZN),
+ REGSET (z, Z), REGSET (Z, Z),
/* SVE predicate registers. */
- REGSET16 (p, PN), REGSET16 (P, PN),
+ REGSET16 (p, P), REGSET16 (P, P),
/* SME ZA. We model this as a register because it acts syntactically
like ZA0H, supporting qualifier suffixes and indexing. */
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 39/43] aarch64: Regularise FLD_* suffixes
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (37 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
` (3 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Some FLD_imm* suffixes used a counting scheme such as FLD_immN,
FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the
suffix. The latter seems more mnemonic, and was a big help
in doing the SME2 work.
Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious.
Presumably it indicated a 2-bit field, but it actually starts
in bit 22.
---
opcodes/aarch64-asm.c | 4 ++--
opcodes/aarch64-dis.c | 10 +++++-----
opcodes/aarch64-opc-2.c | 32 ++++++++++++++++----------------
opcodes/aarch64-opc.c | 16 ++++++++--------
opcodes/aarch64-opc.h | 16 ++++++++--------
opcodes/aarch64-tbl.h | 32 ++++++++++++++++----------------
6 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 73ee15a0257..7351c2417b2 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -120,7 +120,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
/* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
assert (info->idx == 1); /* Vn */
aarch64_insn value = info->reglane.index << pos;
- insert_field (FLD_imm4, code, value, 0);
+ insert_field (FLD_imm4_11, code, value, 0);
}
else
{
@@ -962,7 +962,7 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
insert_field (FLD_shift, code,
aarch64_get_operand_modifier_value (info->shifter.kind), 0);
/* imm6 */
- insert_field (FLD_imm6, code, info->shifter.amount, 0);
+ insert_field (FLD_imm6_10, code, info->shifter.amount, 0);
return true;
}
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index ddbeefa9d91..05e285fac99 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -335,7 +335,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
unsigned shift;
/* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
assert (info->idx == 1); /* Vn */
- aarch64_insn value = extract_field (FLD_imm4, code, 0);
+ aarch64_insn value = extract_field (FLD_imm4_11, code, 0);
/* Depend on AARCH64_OPND_Ed to determine the qualifier. */
info->qualifier = get_expected_qualifier (inst, info->idx);
shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
@@ -1430,7 +1430,7 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
instructions. */
return false;
/* imm6 */
- info->shifter.amount = extract_field (FLD_imm6, code, 0);
+ info->shifter.amount = extract_field (FLD_imm6_10, code, 0);
/* This makes the constraint checking happy. */
info->shifter.operator_present = 1;
@@ -1838,7 +1838,7 @@ aarch64_ext_sme_za_list (const aarch64_operand *self,
}
/* Decode ZA array vector select register (Rv field), optional vector and
- memory offset (imm4 field).
+ memory offset (imm4_11 field).
*/
bool
aarch64_ext_sme_za_array (const aarch64_operand *self,
@@ -2669,7 +2669,7 @@ convert_csinc_to_cset (aarch64_inst *inst)
/* MOV <Wd>, #<imm>
is equivalent to:
- MOVZ <Wd>, #<imm16>, LSL #<shift>.
+ MOVZ <Wd>, #<imm16_5>, LSL #<shift>.
A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
@@ -2956,7 +2956,7 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
switch (inst->opcode->iclass)
{
case sme_mov:
- variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10);
+ variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_22);
if (variant >= 4 && variant < 7)
return false;
if (variant == 7)
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 2fa09b29d26..1d59a8bd332 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -66,8 +66,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_11}, "an immediate as the index of the least significant byte"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_0}, "an immediate as the index of the least significant byte"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
@@ -78,25 +78,25 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"},
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the leftmost bit number to be moved from the source"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the width of the bit-field"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_3}, "a 4-bit unsigned Logical Address Tag modifier"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_10}, "a 4-bit unsigned Logical Address Tag modifier"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"},
{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_2}, "a 16-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_0}, "a 16-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
{AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit immediate with optional left shift"},
{AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"},
@@ -236,16 +236,16 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
- {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
- {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 7a88c19633d..46c49dd95f8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -239,11 +239,11 @@ const aarch64_field fields[] =
{ 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
{ 22, 2 }, /* type: floating point type field in fp data inst. */
{ 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
- { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
- { 15, 6 }, /* imm6_2: in rmif instructions. */
- { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
- { 0, 4 }, /* imm4_2: in rmif instructions. */
- { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
+ { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
+ { 15, 6 }, /* imm6_15: in rmif instructions. */
+ { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
+ { 0, 4 }, /* imm4_0: in rmif instructions. */
+ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */
{ 5, 4 }, /* imm4_5: in SME instructions. */
{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
{ 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
@@ -251,8 +251,8 @@ const aarch64_field fields[] =
{ 12, 9 }, /* imm9: in load/store pre/post index instructions. */
{ 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
{ 5, 14 }, /* imm14: in test bit and branch instructions. */
- { 5, 16 }, /* imm16: in exception instructions. */
- { 0, 16 }, /* imm16_2: in udf instruction. */
+ { 5, 16 }, /* imm16_5: in exception instructions. */
+ { 0, 16 }, /* imm16_0: in udf instruction. */
{ 0, 26 }, /* imm26: in unconditional branch instructions. */
{ 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
{ 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
@@ -326,7 +326,7 @@ const aarch64_field fields[] =
{ 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
{ 0, 2 }, /* SME ZAda tile ZA0-ZA3. */
{ 0, 3 }, /* SME ZAda tile ZA0-ZA7. */
- { 22, 2 }, /* SME_size_10: size<1>, size<0> class field, [23:22]. */
+ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
{ 16, 1 }, /* SME_Q: Q class bit, bit 16. */
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 2bbc81e66bb..fc1f8087261 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -66,11 +66,11 @@ enum aarch64_field_kind
FLD_shift,
FLD_type,
FLD_ldst_size,
- FLD_imm6,
- FLD_imm6_2,
- FLD_imm4,
- FLD_imm4_2,
- FLD_imm4_3,
+ FLD_imm6_10,
+ FLD_imm6_15,
+ FLD_imm4_11,
+ FLD_imm4_0,
+ FLD_imm4_10,
FLD_imm4_5,
FLD_imm5,
FLD_imm7,
@@ -78,8 +78,8 @@ enum aarch64_field_kind
FLD_imm9,
FLD_imm12,
FLD_imm14,
- FLD_imm16,
- FLD_imm16_2,
+ FLD_imm16_5,
+ FLD_imm16_0,
FLD_imm26,
FLD_imms,
FLD_immr,
@@ -153,7 +153,7 @@ enum aarch64_field_kind
FLD_SVE_xs_22,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
- FLD_SME_size_10,
+ FLD_SME_size_22,
FLD_SME_Q,
FLD_SME_V,
FLD_SME_Rv,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8deeded05e5..82f4af2839f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5535,9 +5535,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a 4-bit opcode field named for historical reasons C0 - C15") \
Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm), \
"a 4-bit opcode field named for historical reasons C0 - C15") \
- Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \
+ Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4_11), \
"an immediate as the index of the least significant byte") \
- Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_2), \
+ Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_0), \
"an immediate as the index of the least significant byte") \
Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \
"a left shift amount for an AdvSIMD register") \
@@ -5557,19 +5557,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an 8-bit floating-point constant") \
Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \
"the right rotate amount") \
- Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \
+ Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6_10), \
"the leftmost bit number to be moved from the source") \
- Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \
+ Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6_10), \
"the width of the bit-field") \
- Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
- Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_2), "an immediate") \
+ Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6_10), "an immediate") \
+ Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_15), "an immediate") \
Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \
"a 3-bit unsigned immediate") \
Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \
"a 3-bit unsigned immediate") \
Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
"a 4-bit unsigned immediate") \
- Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_3), \
+ Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_10), \
"a 4-bit unsigned Logical Address Tag modifier") \
Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
"a 7-bit unsigned immediate") \
@@ -5577,9 +5577,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a 10-bit unsigned multiple of 16") \
Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
"the bit number to be tested") \
- Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
+ Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16_5), \
"a 16-bit unsigned immediate") \
- Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_2), \
+ Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_0), \
"a 16-bit unsigned immediate") \
Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
"a 5-bit unsigned immediate") \
@@ -5591,7 +5591,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"Logical immediate") \
Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \
"a 12-bit unsigned immediate with optional left shift of 12 bits")\
- Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \
+ Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16_5), \
"a 16-bit immediate with optional left shift") \
Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
"the number of bits after the binary point in the fixed-point value")\
@@ -5909,28 +5909,28 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
"an SME ZA tile ZA0-ZA7") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \
- F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \
+ F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \
"an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \
- F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \
+ F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \
"an SME horizontal or vertical vector access register") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
- F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \
+ F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \
"an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_array, "SME_ZA_array", 0, \
- F(FLD_SME_Rv,FLD_imm4_2), "ZA array") \
+ F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \
Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \
- F(FLD_Rn,FLD_imm4_2), "memory offset") \
+ F(FLD_Rn,FLD_imm4_0), "memory offset") \
Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \
F(FLD_CRm), "streaming mode") \
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
"Source scalable predicate register with index ") \
- Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
+ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \
"a 16-bit unsigned immediate for TME tcancel") \
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
"an indexed SM3 vector immediate") \
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 40/43] aarch64: Resync field names
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (38 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
` (2 subsequent siblings)
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch just makes the comments in aarch64-opc.c:fields match
the names of the associated FLD_* enum.
---
opcodes/aarch64-opc.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 46c49dd95f8..dc4df2ff20c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -258,12 +258,12 @@ const aarch64_field fields[] =
{ 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
{ 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
{ 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
- { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
+ { 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
{ 22, 1 }, /* N: in logical (immediate) instructions. */
{ 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
{ 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
{ 31, 1 }, /* sf: in integer data processing instructions. */
- { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
+ { 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
@@ -324,22 +324,22 @@ const aarch64_field fields[] =
{ 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
{ 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
{ 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
- { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */
- { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */
+ { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
+ { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
{ 16, 1 }, /* SME_Q: Q class bit, bit 16. */
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
- { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */
+ { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
{ 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
{ 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
- { 18, 3 }, /* SME_tshl: immediate and qualifier field, bits [20:18]. */
+ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
- { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
+ { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
{ 22, 1 }, /* sz: 1-bit element size select. */
{ 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
{ 10, 8 }, /* CSSC_imm8. */
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 41/43] aarch64: Sort fields alphanumerically
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (39 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
This patch just sorts the field enum alphanumerically, which makes
it easier to see if a particular field has already been defined.
---
opcodes/aarch64-opc.c | 162 ++++++++++++++++++++---------------------
opcodes/aarch64-opc.h | 165 +++++++++++++++++++++---------------------
2 files changed, 164 insertions(+), 163 deletions(-)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index dc4df2ff20c..8a9e51faebd 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -202,74 +202,36 @@ aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
const aarch64_field fields[] =
{
{ 0, 0 }, /* NIL. */
- { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
- { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
- { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
- { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
- { 5, 19 }, /* imm19: e.g. in CBZ. */
- { 5, 19 }, /* immhi: e.g. in ADRP. */
- { 29, 2 }, /* immlo: e.g. in ADRP. */
- { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
- { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
- { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
- { 30, 1 }, /* Q: in most AdvSIMD instructions. */
- { 0, 5 }, /* Rt: in load/store instructions. */
- { 0, 5 }, /* Rd: in many integer instructions. */
- { 5, 5 }, /* Rn: in many integer instructions. */
- { 10, 5 }, /* Rt2: in load/store pair instructions. */
- { 10, 5 }, /* Ra: in fp instructions. */
- { 5, 3 }, /* op2: in the system instructions. */
{ 8, 4 }, /* CRm: in the system instructions. */
+ { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
{ 12, 4 }, /* CRn: in the system instructions. */
- { 16, 3 }, /* op1: in the system instructions. */
- { 19, 2 }, /* op0: in the system instructions. */
- { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
- { 12, 4 }, /* cond: condition flags as a source operand. */
- { 12, 4 }, /* opcode: in advsimd load/store instructions. */
- { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
- { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
- { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
- { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
- { 16, 5 }, /* Rs: in load/store exclusive instructions. */
- { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
- { 12, 1 }, /* S: in load/store reg offset instructions. */
- { 21, 2 }, /* hw: in move wide constant instructions. */
- { 22, 2 }, /* opc: in load/store reg offset instructions. */
- { 23, 1 }, /* opc1: in load/store reg offset instructions. */
- { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
- { 22, 2 }, /* type: floating point type field in fp data inst. */
- { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
- { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
- { 15, 6 }, /* imm6_15: in rmif instructions. */
- { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
- { 0, 4 }, /* imm4_0: in rmif instructions. */
- { 10, 4 }, /* imm4_10: in adddg/subg instructions. */
- { 5, 4 }, /* imm4_5: in SME instructions. */
- { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
- { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
- { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
- { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
- { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
- { 5, 14 }, /* imm14: in test bit and branch instructions. */
- { 5, 16 }, /* imm16_5: in exception instructions. */
- { 0, 16 }, /* imm16_0: in udf instruction. */
- { 0, 26 }, /* imm26: in unconditional branch instructions. */
- { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
- { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
- { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
- { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
- { 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
- { 22, 1 }, /* N: in logical (immediate) instructions. */
- { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
- { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
- { 31, 1 }, /* sf: in integer data processing instructions. */
- { 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
+ { 10, 8 }, /* CSSC_imm8. */
{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
- { 31, 1 }, /* b5: in the test bit and branch instructions. */
- { 19, 5 }, /* b40: in the test bit and branch instructions. */
- { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
+ { 22, 1 }, /* N: in logical (immediate) instructions. */
+ { 30, 1 }, /* Q: in most AdvSIMD instructions. */
+ { 10, 5 }, /* Ra: in fp instructions. */
+ { 0, 5 }, /* Rd: in many integer instructions. */
+ { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
+ { 5, 5 }, /* Rn: in many integer instructions. */
+ { 16, 5 }, /* Rs: in load/store exclusive instructions. */
+ { 0, 5 }, /* Rt: in load/store instructions. */
+ { 10, 5 }, /* Rt2: in load/store pair instructions. */
+ { 12, 1 }, /* S: in load/store reg offset instructions. */
+ { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
+ { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
+ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */
+ { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
+ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
+ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
+ { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
+ { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
+ { 23, 1 }, /* SME_i1: immediate field, bit 23. */
+ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
+ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
+ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
+ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
{ 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
{ 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
{ 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
@@ -295,10 +257,10 @@ const aarch64_field fields[] =
{ 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
+ { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
- { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
- { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
+ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
@@ -315,8 +277,8 @@ const aarch64_field fields[] =
{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
{ 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
- { 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
+ { 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 30, 1 }, /* SVE_sz2: 1-bit element size select. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
@@ -324,25 +286,63 @@ const aarch64_field fields[] =
{ 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
{ 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
{ 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
- { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
- { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
- { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
- { 16, 1 }, /* SME_Q: Q class bit, bit 16. */
- { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
- { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
- { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
- { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
- { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
- { 23, 1 }, /* SME_i1: immediate field, bit 23. */
- { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
- { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
+ { 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
+ { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
+ { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
+ { 19, 5 }, /* b40: in the test bit and branch instructions. */
+ { 31, 1 }, /* b5: in the test bit and branch instructions. */
+ { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
+ { 12, 4 }, /* cond: condition flags as a source operand. */
+ { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
+ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
+ { 21, 2 }, /* hw: in move wide constant instructions. */
+ { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
+ { 0, 4 }, /* imm4_0: in rmif instructions. */
+ { 5, 4 }, /* imm4_5: in SME instructions. */
+ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */
+ { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
+ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
+ { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
+ { 15, 6 }, /* imm6_15: in rmif instructions. */
+ { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
+ { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
+ { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
+ { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
+ { 5, 14 }, /* imm14: in test bit and branch instructions. */
+ { 0, 16 }, /* imm16_0: in udf instruction. */
+ { 5, 16 }, /* imm16_5: in exception instructions. */
+ { 5, 19 }, /* imm19: e.g. in CBZ. */
+ { 0, 26 }, /* imm26: in unconditional branch instructions. */
+ { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
+ { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
+ { 5, 19 }, /* immhi: e.g. in ADRP. */
+ { 29, 2 }, /* immlo: e.g. in ADRP. */
+ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
+ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
+ { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
+ { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
+ { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
+ { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
+ { 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
+ { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
+ { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
+ { 19, 2 }, /* op0: in the system instructions. */
+ { 16, 3 }, /* op1: in the system instructions. */
+ { 5, 3 }, /* op2: in the system instructions. */
+ { 22, 2 }, /* opc: in load/store reg offset instructions. */
+ { 23, 1 }, /* opc1: in load/store reg offset instructions. */
+ { 12, 4 }, /* opcode: in advsimd load/store instructions. */
+ { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
- { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
+ { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
+ { 31, 1 }, /* sf: in integer data processing instructions. */
+ { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
+ { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
{ 22, 1 }, /* sz: 1-bit element size select. */
- { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
- { 10, 8 }, /* CSSC_imm8. */
+ { 22, 2 }, /* type: floating point type field in fp data inst. */
+ { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
};
enum aarch64_operand_class
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index fc1f8087261..3ded6ab7958 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -25,78 +25,41 @@
#include "opcode/aarch64.h"
/* Instruction fields.
- Keep synced with fields. */
+ Keep this sorted alphanumerically and synced with the fields array
+ in aarch64-opc.c. */
enum aarch64_field_kind
{
FLD_NIL,
- FLD_cond2,
- FLD_nzcv,
- FLD_defgh,
- FLD_abc,
- FLD_imm19,
- FLD_immhi,
- FLD_immlo,
- FLD_size,
- FLD_vldst_size,
- FLD_op,
- FLD_Q,
- FLD_Rt,
- FLD_Rd,
- FLD_Rn,
- FLD_Rt2,
- FLD_Ra,
- FLD_op2,
FLD_CRm,
+ FLD_CRm_dsb_nxs,
FLD_CRn,
- FLD_op1,
- FLD_op0,
- FLD_imm3,
- FLD_cond,
- FLD_opcode,
- FLD_cmode,
- FLD_asisdlso_opcode,
- FLD_len,
- FLD_Rm,
- FLD_Rs,
- FLD_option,
- FLD_S,
- FLD_hw,
- FLD_opc,
- FLD_opc1,
- FLD_shift,
- FLD_type,
- FLD_ldst_size,
- FLD_imm6_10,
- FLD_imm6_15,
- FLD_imm4_11,
- FLD_imm4_0,
- FLD_imm4_10,
- FLD_imm4_5,
- FLD_imm5,
- FLD_imm7,
- FLD_imm8,
- FLD_imm9,
- FLD_imm12,
- FLD_imm14,
- FLD_imm16_5,
- FLD_imm16_0,
- FLD_imm26,
- FLD_imms,
- FLD_immr,
- FLD_immb,
- FLD_immh,
- FLD_S_imm10,
- FLD_N,
- FLD_index,
- FLD_index2,
- FLD_sf,
- FLD_lse_sz,
+ FLD_CSSC_imm8,
FLD_H,
FLD_L,
FLD_M,
- FLD_b5,
- FLD_b40,
- FLD_scale,
+ FLD_N,
+ FLD_Q,
+ FLD_Ra,
+ FLD_Rd,
+ FLD_Rm,
+ FLD_Rn,
+ FLD_Rs,
+ FLD_Rt,
+ FLD_Rt2,
+ FLD_S,
+ FLD_SM3_imm2,
+ FLD_SME_Pm,
+ FLD_SME_Q,
+ FLD_SME_Rm,
+ FLD_SME_Rv,
+ FLD_SME_V,
+ FLD_SME_ZAda_2b,
+ FLD_SME_ZAda_3b,
+ FLD_SME_i1,
+ FLD_SME_size_22,
+ FLD_SME_tszh,
+ FLD_SME_tszl,
+ FLD_SME_zero_mask,
FLD_SVE_M_4,
FLD_SVE_M_14,
FLD_SVE_M_16,
@@ -122,10 +85,10 @@ enum aarch64_field_kind
FLD_SVE_Zn,
FLD_SVE_Zt,
FLD_SVE_i1,
+ FLD_SVE_i2h,
FLD_SVE_i3h,
- FLD_SVE_i3l,
FLD_SVE_i3h2,
- FLD_SVE_i2h,
+ FLD_SVE_i3l,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
@@ -142,8 +105,8 @@ enum aarch64_field_kind
FLD_SVE_rot1,
FLD_SVE_rot2,
FLD_SVE_rot3,
- FLD_SVE_sz,
FLD_SVE_size,
+ FLD_SVE_sz,
FLD_SVE_sz2,
FLD_SVE_tsz,
FLD_SVE_tszh,
@@ -151,25 +114,63 @@ enum aarch64_field_kind
FLD_SVE_tszl_19,
FLD_SVE_xs_14,
FLD_SVE_xs_22,
- FLD_SME_ZAda_2b,
- FLD_SME_ZAda_3b,
- FLD_SME_size_22,
- FLD_SME_Q,
- FLD_SME_V,
- FLD_SME_Rv,
- FLD_SME_Pm,
- FLD_SME_zero_mask,
- FLD_SME_Rm,
- FLD_SME_i1,
- FLD_SME_tszh,
- FLD_SME_tszl,
+ FLD_S_imm10,
+ FLD_abc,
+ FLD_asisdlso_opcode,
+ FLD_b40,
+ FLD_b5,
+ FLD_cmode,
+ FLD_cond,
+ FLD_cond2,
+ FLD_defgh,
+ FLD_hw,
+ FLD_imm3,
+ FLD_imm4_0,
+ FLD_imm4_5,
+ FLD_imm4_10,
+ FLD_imm4_11,
+ FLD_imm5,
+ FLD_imm6_10,
+ FLD_imm6_15,
+ FLD_imm7,
+ FLD_imm8,
+ FLD_imm9,
+ FLD_imm12,
+ FLD_imm14,
+ FLD_imm16_0,
+ FLD_imm16_5,
+ FLD_imm19,
+ FLD_imm26,
+ FLD_immb,
+ FLD_immh,
+ FLD_immhi,
+ FLD_immlo,
+ FLD_immr,
+ FLD_imms,
+ FLD_index,
+ FLD_index2,
+ FLD_ldst_size,
+ FLD_len,
+ FLD_lse_sz,
+ FLD_nzcv,
+ FLD_op,
+ FLD_op0,
+ FLD_op1,
+ FLD_op2,
+ FLD_opc,
+ FLD_opc1,
+ FLD_opcode,
+ FLD_option,
FLD_rotate1,
FLD_rotate2,
FLD_rotate3,
- FLD_SM3_imm2,
+ FLD_scale,
+ FLD_sf,
+ FLD_shift,
+ FLD_size,
FLD_sz,
- FLD_CRm_dsb_nxs,
- FLD_CSSC_imm8
+ FLD_type,
+ FLD_vldst_size,
};
/* Field description. */
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 42/43] aarch64: Add support for strided register lists
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (40 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
42 siblings, 1 reply; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
SME2 has instructions that accept strided register lists,
such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this
patch is to extend binutils to support such lists.
The parsing code already had (unused) support for strides of 2.
The idea here is instead to accept all strides during parsing
and reject invalid strides during constraint checking.
The SME2 instructions that accept strided operands also have
non-strided forms. The errors about invalid strides therefore
take a bitmask of acceptable strides, which allows multiple
possibilities to be summed up in a single message.
I've tried to update all code that handles register lists.
---
gas/config/tc-aarch64.c | 58 ++++++++++++-------
gas/testsuite/gas/aarch64/diagnostic.l | 2 +-
gas/testsuite/gas/aarch64/illegal-sve2.l | 19 ++++--
gas/testsuite/gas/aarch64/illegal-sve2.s | 1 +
include/opcode/aarch64.h | 38 ++++++++----
opcodes/aarch64-dis.c | 5 ++
opcodes/aarch64-opc.c | 74 ++++++++++++++++--------
7 files changed, 135 insertions(+), 62 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c6cc654095e..0acb3643843 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5065,7 +5065,8 @@ const char* operand_mismatch_kind_names[] =
"AARCH64_OPDE_SYNTAX_ERROR",
"AARCH64_OPDE_FATAL_SYNTAX_ERROR",
"AARCH64_OPDE_INVALID_VARIANT",
- "AARCH64_OPDE_REG_LIST",
+ "AARCH64_OPDE_REG_LIST_LENGTH",
+ "AARCH64_OPDE_REG_LIST_STRIDE",
"AARCH64_OPDE_UNTIED_IMMS",
"AARCH64_OPDE_UNTIED_OPERAND",
"AARCH64_OPDE_OUT_OF_RANGE",
@@ -5092,10 +5093,11 @@ operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_EXPECTED_A_AFTER_B);
gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
- gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_INVALID_VARIANT);
- gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST);
+ gas_assert (AARCH64_OPDE_REG_LIST_LENGTH > AARCH64_OPDE_INVALID_VARIANT);
+ gas_assert (AARCH64_OPDE_REG_LIST_STRIDE > AARCH64_OPDE_REG_LIST_LENGTH);
+ gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST_STRIDE);
gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
- gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
+ gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST_STRIDE);
gas_assert (AARCH64_OPDE_INVALID_REGNO > AARCH64_OPDE_OTHER_ERROR);
return lhs > rhs;
}
@@ -5745,7 +5747,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
detail->data[0].i, idx + 1, str);
break;
- case AARCH64_OPDE_REG_LIST:
+ case AARCH64_OPDE_REG_LIST_LENGTH:
if (detail->data[0].i == (1 << 1))
handler (_("expected a single-register list at operand %d -- `%s'"),
idx + 1, str);
@@ -5757,6 +5759,15 @@ output_operand_error_record (const operand_error_record *record, char *str)
" at operand %d -- `%s'"), idx + 1, str);
break;
+ case AARCH64_OPDE_REG_LIST_STRIDE:
+ if (detail->data[0].i == (1 << 1))
+ handler (_("the register list must have a stride of %d"
+ " at operand %d -- `%s'"), 1, idx + 1, str);
+ else
+ handler (_("invalid register stride at operand %d -- `%s'"),
+ idx + 1, str);
+ break;
+
case AARCH64_OPDE_UNALIGNED:
handler (_("immediate value must be a multiple of "
"%d at operand %d -- `%s'"),
@@ -5860,7 +5871,8 @@ output_operand_error_report (char *str, bool non_fatal_only)
curr->detail.data[0].i, curr->detail.data[1].i,
curr->detail.data[2].i);
}
- else if (curr->detail.kind == AARCH64_OPDE_REG_LIST)
+ else if (curr->detail.kind == AARCH64_OPDE_REG_LIST_LENGTH
+ || curr->detail.kind == AARCH64_OPDE_REG_LIST_STRIDE)
{
DEBUG_TRACE ("\t%s [%x]",
operand_mismatch_kind_names[curr->detail.kind],
@@ -5908,7 +5920,8 @@ output_operand_error_report (char *str, bool non_fatal_only)
curr->detail.data[0].i, curr->detail.data[1].i,
curr->detail.data[2].i);
}
- else if (kind == AARCH64_OPDE_REG_LIST)
+ else if (kind == AARCH64_OPDE_REG_LIST_LENGTH
+ || kind == AARCH64_OPDE_REG_LIST_STRIDE)
{
record->detail.data[0].i |= curr->detail.data[0].i;
DEBUG_TRACE ("\t--> %s [%x]",
@@ -6352,33 +6365,40 @@ ldst_lo12_determine_real_reloc_type (void)
}
/* Check whether a register list REGINFO is valid. The registers must be
- numbered in increasing order (modulo 32), in increments of one or two.
+ numbered in increasing order (modulo 32). They must also have a
+ consistent stride.
- If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
- increments of two.
-
- Return FALSE if such a register list is invalid, otherwise return TRUE. */
+ Return true if the list is valid, describing it in LIST if so. */
static bool
-reg_list_valid_p (uint32_t reginfo, int accept_alternate)
+reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list)
{
uint32_t i, nb_regs, prev_regno, incr;
nb_regs = 1 + (reginfo & 0x3);
reginfo >>= 2;
prev_regno = reginfo & 0x1f;
- incr = accept_alternate ? 2 : 1;
+ incr = 1;
+
+ list->first_regno = prev_regno;
+ list->num_regs = nb_regs;
for (i = 1; i < nb_regs; ++i)
{
- uint32_t curr_regno;
+ uint32_t curr_regno, curr_incr;
reginfo >>= 5;
curr_regno = reginfo & 0x1f;
- if (curr_regno != ((prev_regno + incr) & 0x1f))
+ curr_incr = (curr_regno - prev_regno) & 0x1f;
+ if (curr_incr == 0)
+ return false;
+ else if (i == 1)
+ incr = curr_incr;
+ else if (curr_incr != incr)
return false;
prev_regno = curr_regno;
}
+ list->stride = incr;
return true;
}
@@ -6628,6 +6648,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
info->reglist.first_regno = reg->number;
info->reglist.num_regs = 1;
+ info->reglist.stride = 1;
}
else
{
@@ -6635,7 +6656,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (val == PARSE_FAIL)
goto failure;
- if (! reg_list_valid_p (val, /* accept_alternate */ 0))
+ if (! reg_list_valid_p (val, &info->reglist))
{
set_fatal_syntax_error (_("invalid register list"));
goto failure;
@@ -6647,9 +6668,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
(_("expected element type rather than vector type"));
goto failure;
}
-
- info->reglist.first_regno = (val >> 2) & 0x1f;
- info->reglist.num_regs = (val & 0x3) + 1;
}
if (operands[i] == AARCH64_OPND_LEt)
{
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 6d59564a543..85ec9fe6900 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -78,7 +78,7 @@
[^:]*:80: Error: immediate value out of range 0 to 15 at operand 1 -- `dmb #16'
[^:]*:81: Error: immediate value out of range 0 to 31 at operand 2 -- `tbz w0,#40,0x17c'
[^:]*:82: Error: expected a list of 2 registers at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
-[^:]*:83: Error: invalid register list at operand 1 -- `ld2 \{v1.4h,v0.4h\},\[x1\]'
+[^:]*:83: Error: the register list must have a stride of 1 at operand 1 -- `ld2 \{v1.4h,v0.4h\},\[x1\]'
[^:]*:84: Error: the specified option is not accepted in ISB at operand 1 -- `isb osh'
[^:]*:85: Error: invalid address at operand 2 -- `st2 \{v4.2d,v5.2d,v6.2d\},\\\[x3\\\]'
[^:]*:86: Error: immediate value must be a multiple of 4 at operand 3 -- `ldnp w7,w15,\[x3,#3\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 369c0e6983a..48281fcc4cd 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -239,7 +239,7 @@
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `eortb z0\.s,z32\.s,z0\.s'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `eortb z0\.s,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `ext z0\.b,{,},#0'
-[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
@@ -251,8 +251,8 @@
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b},#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
-[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `ext z32\.b,{z0\.b,z1\.b},#0'
[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0'
@@ -1277,7 +1277,7 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: smullt z0\.s, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: smullt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
[^ :]+:[0-9]+: Error: operand mismatch -- `splice z0\.h,p0,{z0\.b,z1\.b}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: splice z0\.b, p0, {z0\.b, z1\.b}
@@ -1289,7 +1289,7 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `splice z32\.b,p0,{z0\.b,z1\.b}'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `splice z0\.b,p8,{z0\.b,z1\.b}'
-[^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z31\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 3 -- `splice z0\.b,p0,{z31\.b,z1\.b}'
[^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z31\.b,z32\.b}'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `splice z0\.b,p0,{z32\.b,z1\.b}'
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqabs z32\.b,p0/m,z0\.b'
@@ -2332,7 +2332,7 @@
[^ :]+:[0-9]+: Info: suqadd z0\.d, p0/m, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `tbl z0\.b,{z31\.b,z32\.b},z0\.b'
-[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.b,{z31\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `tbl z0\.b,{z31\.b,z1\.b},z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
@@ -2344,6 +2344,13 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.h,{z0\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b, z1\.b}, z0\.b
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h, z1\.h}, z0\.h
+[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s, z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d, z1\.d}, z0\.d
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbx z32\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `tbx z0\.h,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbx z0\.h,z0\.b,z32\.b'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s
index 4b6285c185e..172d0f4b16b 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.s
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.s
@@ -1526,6 +1526,7 @@ tbl z0.b, { z0.b, z1.b }, z0.h
tbl z0.b, { z0.b, z1.h }, z0.b
tbl z0.b, { z0.h, z0.b }, z0.b
tbl z0.h, { z0.b, z0.b }, z0.b
+tbl z0.h, { z0.b, z1.b }, z0.b
tbx z32.h, z0.b, z0.b
tbx z0.h, z32.b, z0.b
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 61afe561a12..ef59d531d17 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1122,6 +1122,19 @@ struct aarch64_indexed_za
unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
};
+/* Information about a list of registers. */
+struct aarch64_reglist
+{
+ unsigned first_regno : 8;
+ unsigned num_regs : 8;
+ /* The difference between the nth and the n+1th register. */
+ unsigned stride : 8;
+ /* 1 if it is a list of reg element. */
+ unsigned has_index : 1;
+ /* Lane index; valid only when has_index is 1. */
+ int64_t index;
+} reglist;
+
/* Structure representing an operand. */
struct aarch64_opnd_info
@@ -1142,15 +1155,7 @@ struct aarch64_opnd_info
int64_t index;
} reglane;
/* e.g. LVn. */
- struct
- {
- unsigned first_regno : 5;
- unsigned num_regs : 3;
- /* 1 if it is a list of reg element. */
- unsigned has_index : 1;
- /* Lane index; valid only when has_index is 1. */
- int64_t index;
- } reglist;
+ struct aarch64_reglist reglist;
/* e.g. immediate or pc relative address offset. */
struct
{
@@ -1288,11 +1293,19 @@ struct aarch64_inst
The following errors are only reported against an asm string that is
syntactically valid and that has valid operand qualifiers.
- AARCH64_OPDE_REG_LIST
- Error about the register list operand having an unexpected number of
+ AARCH64_OPDE_REG_LIST_LENGTH
+ Error about a register list operand having an unexpected number of
registers. This error is low severity because there might be another
opcode entry that supports the given number of registers.
+ AARCH64_OPDE_REG_LIST_STRIDE
+ Error about a register list operand having the correct number
+ (and type) of registers, but an unexpected stride. This error is
+ more severe than AARCH64_OPDE_REG_LIST_LENGTH because it implies
+ that the length is known to be correct. However, it is lower than
+ many other errors, since some instructions have forms that share
+ the same number of registers but have different strides.
+
AARCH64_OPDE_UNTIED_IMMS
The asm failed to use the same immediate for a destination operand
and a tied source operand.
@@ -1342,7 +1355,8 @@ enum aarch64_operand_error_kind
AARCH64_OPDE_SYNTAX_ERROR,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
AARCH64_OPDE_INVALID_VARIANT,
- AARCH64_OPDE_REG_LIST,
+ AARCH64_OPDE_REG_LIST_LENGTH,
+ AARCH64_OPDE_REG_LIST_STRIDE,
AARCH64_OPDE_UNTIED_IMMS,
AARCH64_OPDE_UNTIED_OPERAND,
AARCH64_OPDE_OUT_OF_RANGE,
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 05e285fac99..e722514053e 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -439,6 +439,7 @@ aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
info->reglist.first_regno = extract_field (self->fields[0], code, 0);
/* len */
info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
+ info->reglist.stride = 1;
return true;
}
@@ -482,6 +483,7 @@ aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
if (expected_num != data[value].num_elements || data[value].is_reserved)
return false;
info->reglist.num_regs = data[value].num_regs;
+ info->reglist.stride = 1;
return true;
}
@@ -510,6 +512,7 @@ aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
info->reglist.num_regs = 2;
+ info->reglist.stride = 1;
return true;
}
@@ -573,6 +576,7 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
info->reglist.has_index = 1;
info->reglist.num_regs = 0;
+ info->reglist.stride = 1;
/* Number of registers is equal to the number of elements in
each structure to be loaded/stored. */
info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
@@ -1982,6 +1986,7 @@ aarch64_ext_sve_reglist (const aarch64_operand *self,
{
info->reglist.first_regno = extract_field (self->fields[0], code, 0);
info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
+ info->reglist.stride = 1;
return true;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 8a9e51faebd..4e950cf70f8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1439,12 +1439,22 @@ set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
}
static inline void
-set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
- int expected_num)
+set_reg_list_length_error (aarch64_operand_error *mismatch_detail, int idx,
+ int expected_num)
{
if (mismatch_detail == NULL)
return;
- set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
+ set_error (mismatch_detail, AARCH64_OPDE_REG_LIST_LENGTH, idx, NULL);
+ mismatch_detail->data[0].i = 1 << expected_num;
+}
+
+static inline void
+set_reg_list_stride_error (aarch64_operand_error *mismatch_detail, int idx,
+ int expected_num)
+{
+ if (mismatch_detail == NULL)
+ return;
+ set_error (mismatch_detail, AARCH64_OPDE_REG_LIST_STRIDE, idx, NULL);
mismatch_detail->data[0].i = 1 << expected_num;
}
@@ -1482,6 +1492,27 @@ check_reglane (const aarch64_opnd_info *opnd,
return true;
}
+/* Check that register list operand OPND has NUM_REGS registers and a
+ register stride of STRIDE. */
+
+static bool
+check_reglist (const aarch64_opnd_info *opnd,
+ aarch64_operand_error *mismatch_detail, int idx,
+ int num_regs, int stride)
+{
+ if (opnd->reglist.num_regs != num_regs)
+ {
+ set_reg_list_length_error (mismatch_detail, idx, num_regs);
+ return false;
+ }
+ if (opnd->reglist.stride != stride)
+ {
+ set_reg_list_stride_error (mismatch_detail, idx, stride);
+ return false;
+ }
+ return true;
+}
+
/* Check that indexed ZA operand OPND has:
- a selection register in the range [MIN_WREG, MIN_WREG + 3]
@@ -1637,11 +1668,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_CLASS_SVE_REGLIST:
num = get_opcode_dependent_value (opcode);
- if (opnd->reglist.num_regs != num)
- {
- set_reg_list_error (mismatch_detail, idx, num);
- return 0;
- }
+ if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
+ return 0;
break;
case AARCH64_OPND_CLASS_ZA_ACCESS:
@@ -2123,26 +2151,25 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
assert (num >= 1 && num <= 4);
/* Unless LD1/ST1, the number of registers should be equal to that
of the structure elements. */
- if (num != 1 && opnd->reglist.num_regs != num)
- {
- set_reg_list_error (mismatch_detail, idx, num);
- return 0;
- }
+ if (num != 1 && !check_reglist (opnd, mismatch_detail, idx, num, 1))
+ return 0;
break;
case AARCH64_OPND_LVt_AL:
case AARCH64_OPND_LEt:
assert (num >= 1 && num <= 4);
/* The number of registers should be equal to that of the structure
elements. */
- if (opnd->reglist.num_regs != num)
- {
- set_reg_list_error (mismatch_detail, idx, num);
- return 0;
- }
+ if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
+ return 0;
break;
default:
break;
}
+ if (opnd->reglist.stride != 1)
+ {
+ set_reg_list_stride_error (mismatch_detail, idx, 1);
+ return 0;
+ }
break;
case AARCH64_OPND_CLASS_IMMEDIATE:
@@ -3199,8 +3226,9 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
const char *prefix, struct aarch64_styler *styler)
{
const int num_regs = opnd->reglist.num_regs;
+ const int stride = opnd->reglist.stride;
const int first_reg = opnd->reglist.first_regno;
- const int last_reg = (first_reg + num_regs - 1) & 0x1f;
+ const int last_reg = (first_reg + (num_regs - 1) * stride) & 0x1f;
const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
char tb[16]; /* Temporary buffer. */
@@ -3218,16 +3246,16 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
/* The hyphenated form is preferred for disassembly if there are
more than two registers in the list, and the register numbers
are monotonically increasing in increments of one. */
- if (num_regs > 2 && last_reg > first_reg)
+ if (stride == 1 && num_regs > 2 && last_reg > first_reg)
snprintf (buf, size, "{%s-%s}%s",
style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
else
{
const int reg0 = first_reg;
- const int reg1 = (first_reg + 1) & 0x1f;
- const int reg2 = (first_reg + 2) & 0x1f;
- const int reg3 = (first_reg + 3) & 0x1f;
+ const int reg1 = (first_reg + stride) & 0x1f;
+ const int reg2 = (first_reg + stride * 2) & 0x1f;
+ const int reg3 = (first_reg + stride * 3) & 0x1f;
switch (num_regs)
{
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 43/43] aarch64: Prefer register ranges & support wrapping
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
` (41 preceding siblings ...)
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
@ 2023-03-30 10:23 ` Richard Sandiford
42 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 10:23 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Until now, binutils has supported register ranges such
as { v0.4s - v3.4s } as an unofficial shorthand for
{ v0.4s, v1.4s, v2.4s, v3.4s }. The SME2 ISA embraces this form
and makes it the preferred disassembly. It also embraces wrapped
lists such as { z31.s - z2.s }, which is something that binutils
didn't previously allow.
The range form was already binutils's preferred disassembly for 3- and
4-register lists. This patch prefers it for 2-register lists too.
The patch also adds support for wrap-around.
---
gas/config/tc-aarch64.c | 12 +-
gas/testsuite/gas/aarch64/illegal-sve2.l | 28 +-
.../gas/aarch64/neon-vfp-reglist-post.d | 184 +-
gas/testsuite/gas/aarch64/neon-vfp-reglist.d | 100 +-
gas/testsuite/gas/aarch64/reglist-1.d | 21 +
gas/testsuite/gas/aarch64/reglist-1.s | 15 +
gas/testsuite/gas/aarch64/reglist-2.d | 3 +
gas/testsuite/gas/aarch64/reglist-2.l | 8 +
gas/testsuite/gas/aarch64/reglist-2.s | 7 +
gas/testsuite/gas/aarch64/sve.d | 1612 ++++++++---------
gas/testsuite/gas/aarch64/sve2.d | 30 +-
opcodes/aarch64-opc.c | 2 +-
12 files changed, 1039 insertions(+), 983 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/reglist-1.d
create mode 100644 gas/testsuite/gas/aarch64/reglist-1.s
create mode 100644 gas/testsuite/gas/aarch64/reglist-2.d
create mode 100644 gas/testsuite/gas/aarch64/reglist-2.l
create mode 100644 gas/testsuite/gas/aarch64/reglist-2.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0acb3643843..2d4c6106506 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1358,7 +1358,6 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
int val, val_range;
int in_range;
int ret_val;
- int i;
bool error = false;
bool expect_index = false;
unsigned int ptr_flags = PTR_IN_REGLIST;
@@ -1409,13 +1408,13 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
if (in_range)
{
- if (val < val_range)
+ if (val == val_range)
{
set_first_syntax_error
(_("invalid range in vector register list"));
error = true;
}
- val_range++;
+ val_range = (val_range + 1) & 0x1f;
}
else
{
@@ -1430,10 +1429,13 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
}
}
if (! error)
- for (i = val_range; i <= val; i++)
+ for (;;)
{
- ret_val |= i << (5 * nb_regs);
+ ret_val |= val_range << (5 * nb_regs);
nb_regs++;
+ if (val_range == val)
+ break;
+ val_range = (val_range + 1) & 0x1f;
}
in_range = 0;
ptr_flags |= PTR_GOOD_MATCH;
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 48281fcc4cd..f07ef384f94 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -242,12 +242,12 @@
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
+[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b-z1\.b}, #0
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.h,z1\.b},#0'
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.h},#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
+[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b-z1\.b}, #0
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b},#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
@@ -1280,11 +1280,11 @@
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
[^ :]+:[0-9]+: Error: operand mismatch -- `splice z0\.h,p0,{z0\.b,z1\.b}'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: splice z0\.b, p0, {z0\.b, z1\.b}
+[^ :]+:[0-9]+: Info: splice z0\.b, p0, {z0\.b-z1\.b}
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: splice z0\.h, p0, {z0\.h, z1\.h}
-[^ :]+:[0-9]+: Info: splice z0\.s, p0, {z0\.s, z1\.s}
-[^ :]+:[0-9]+: Info: splice z0\.d, p0, {z0\.d, z1\.d}
+[^ :]+:[0-9]+: Info: splice z0\.h, p0, {z0\.h-z1\.h}
+[^ :]+:[0-9]+: Info: splice z0\.s, p0, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: splice z0\.d, p0, {z0\.d-z1\.d}
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `splice z32\.b,p0,{z0\.b,z1\.b}'
@@ -2336,21 +2336,21 @@
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b, z1\.b}, z0\.b
+[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b-z1\.b}, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h, z1\.h}, z0\.h
-[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s, z1\.s}, z0\.s
-[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d, z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h-z1\.h}, z0\.h
+[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d-z1\.d}, z0\.d
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.h,{z0\.b,z1\.b},z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b, z1\.b}, z0\.b
+[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b-z1\.b}, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h, z1\.h}, z0\.h
-[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s, z1\.s}, z0\.s
-[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d, z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h-z1\.h}, z0\.h
+[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d-z1\.d}, z0\.d
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbx z32\.h,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `tbx z0\.h,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbx z0\.h,z0\.b,z32\.b'
diff --git a/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d b/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
index 8e710562efc..5e41631b5ab 100644
--- a/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
+++ b/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
@@ -6,161 +6,161 @@ Disassembly of section \.text:
0+ <.*>:
0: 0cdf7000 ld1 {v0.8b}, \[x0\], #8
- 4: 0cdfa000 ld1 {v0.8b, v1.8b}, \[x0\], #16
+ 4: 0cdfa000 ld1 {v0.8b-v1.8b}, \[x0\], #16
8: 0cdf6000 ld1 {v0.8b-v2.8b}, \[x0\], #24
c: 0cdf2000 ld1 {v0.8b-v3.8b}, \[x0\], #32
10: 0cdf7400 ld1 {v0.4h}, \[x0\], #8
- 14: 0cdfa400 ld1 {v0.4h, v1.4h}, \[x0\], #16
+ 14: 0cdfa400 ld1 {v0.4h-v1.4h}, \[x0\], #16
18: 0cdf6400 ld1 {v0.4h-v2.4h}, \[x0\], #24
1c: 0cdf2400 ld1 {v0.4h-v3.4h}, \[x0\], #32
20: 0cdf7800 ld1 {v0.2s}, \[x0\], #8
- 24: 0cdfa800 ld1 {v0.2s, v1.2s}, \[x0\], #16
+ 24: 0cdfa800 ld1 {v0.2s-v1.2s}, \[x0\], #16
28: 0cdf6800 ld1 {v0.2s-v2.2s}, \[x0\], #24
2c: 0cdf2800 ld1 {v0.2s-v3.2s}, \[x0\], #32
30: 0cdf7c00 ld1 {v0.1d}, \[x0\], #8
- 34: 0cdfac00 ld1 {v0.1d, v1.1d}, \[x0\], #16
+ 34: 0cdfac00 ld1 {v0.1d-v1.1d}, \[x0\], #16
38: 0cdf6c00 ld1 {v0.1d-v2.1d}, \[x0\], #24
3c: 0cdf2c00 ld1 {v0.1d-v3.1d}, \[x0\], #32
40: 0c9f7000 st1 {v0.8b}, \[x0\], #8
- 44: 0c9fa000 st1 {v0.8b, v1.8b}, \[x0\], #16
+ 44: 0c9fa000 st1 {v0.8b-v1.8b}, \[x0\], #16
48: 0c9f6000 st1 {v0.8b-v2.8b}, \[x0\], #24
4c: 0c9f2000 st1 {v0.8b-v3.8b}, \[x0\], #32
50: 0c9f7400 st1 {v0.4h}, \[x0\], #8
- 54: 0c9fa400 st1 {v0.4h, v1.4h}, \[x0\], #16
+ 54: 0c9fa400 st1 {v0.4h-v1.4h}, \[x0\], #16
58: 0c9f6400 st1 {v0.4h-v2.4h}, \[x0\], #24
5c: 0c9f2400 st1 {v0.4h-v3.4h}, \[x0\], #32
60: 0c9f7800 st1 {v0.2s}, \[x0\], #8
- 64: 0c9fa800 st1 {v0.2s, v1.2s}, \[x0\], #16
+ 64: 0c9fa800 st1 {v0.2s-v1.2s}, \[x0\], #16
68: 0c9f6800 st1 {v0.2s-v2.2s}, \[x0\], #24
6c: 0c9f2800 st1 {v0.2s-v3.2s}, \[x0\], #32
70: 0c9f7c00 st1 {v0.1d}, \[x0\], #8
- 74: 0c9fac00 st1 {v0.1d, v1.1d}, \[x0\], #16
+ 74: 0c9fac00 st1 {v0.1d-v1.1d}, \[x0\], #16
78: 0c9f6c00 st1 {v0.1d-v2.1d}, \[x0\], #24
7c: 0c9f2c00 st1 {v0.1d-v3.1d}, \[x0\], #32
80: 4cdf7000 ld1 {v0.16b}, \[x0\], #16
- 84: 4cdfa000 ld1 {v0.16b, v1.16b}, \[x0\], #32
+ 84: 4cdfa000 ld1 {v0.16b-v1.16b}, \[x0\], #32
88: 4cdf6000 ld1 {v0.16b-v2.16b}, \[x0\], #48
8c: 4cdf2000 ld1 {v0.16b-v3.16b}, \[x0\], #64
90: 4cdf7400 ld1 {v0.8h}, \[x0\], #16
- 94: 4cdfa400 ld1 {v0.8h, v1.8h}, \[x0\], #32
+ 94: 4cdfa400 ld1 {v0.8h-v1.8h}, \[x0\], #32
98: 4cdf6400 ld1 {v0.8h-v2.8h}, \[x0\], #48
9c: 4cdf2400 ld1 {v0.8h-v3.8h}, \[x0\], #64
a0: 4cdf7800 ld1 {v0.4s}, \[x0\], #16
- a4: 4cdfa800 ld1 {v0.4s, v1.4s}, \[x0\], #32
+ a4: 4cdfa800 ld1 {v0.4s-v1.4s}, \[x0\], #32
a8: 4cdf6800 ld1 {v0.4s-v2.4s}, \[x0\], #48
ac: 4cdf2800 ld1 {v0.4s-v3.4s}, \[x0\], #64
b0: 4cdf7c00 ld1 {v0.2d}, \[x0\], #16
- b4: 4cdfac00 ld1 {v0.2d, v1.2d}, \[x0\], #32
+ b4: 4cdfac00 ld1 {v0.2d-v1.2d}, \[x0\], #32
b8: 4cdf6c00 ld1 {v0.2d-v2.2d}, \[x0\], #48
bc: 4cdf2c00 ld1 {v0.2d-v3.2d}, \[x0\], #64
c0: 4c9f7000 st1 {v0.16b}, \[x0\], #16
- c4: 4c9fa000 st1 {v0.16b, v1.16b}, \[x0\], #32
+ c4: 4c9fa000 st1 {v0.16b-v1.16b}, \[x0\], #32
c8: 4c9f6000 st1 {v0.16b-v2.16b}, \[x0\], #48
cc: 4c9f2000 st1 {v0.16b-v3.16b}, \[x0\], #64
d0: 4c9f7400 st1 {v0.8h}, \[x0\], #16
- d4: 4c9fa400 st1 {v0.8h, v1.8h}, \[x0\], #32
+ d4: 4c9fa400 st1 {v0.8h-v1.8h}, \[x0\], #32
d8: 4c9f6400 st1 {v0.8h-v2.8h}, \[x0\], #48
dc: 4c9f2400 st1 {v0.8h-v3.8h}, \[x0\], #64
e0: 4c9f7800 st1 {v0.4s}, \[x0\], #16
- e4: 4c9fa800 st1 {v0.4s, v1.4s}, \[x0\], #32
+ e4: 4c9fa800 st1 {v0.4s-v1.4s}, \[x0\], #32
e8: 4c9f6800 st1 {v0.4s-v2.4s}, \[x0\], #48
ec: 4c9f2800 st1 {v0.4s-v3.4s}, \[x0\], #64
f0: 4c9f7c00 st1 {v0.2d}, \[x0\], #16
- f4: 4c9fac00 st1 {v0.2d, v1.2d}, \[x0\], #32
+ f4: 4c9fac00 st1 {v0.2d-v1.2d}, \[x0\], #32
f8: 4c9f6c00 st1 {v0.2d-v2.2d}, \[x0\], #48
fc: 4c9f2c00 st1 {v0.2d-v3.2d}, \[x0\], #64
100: 0cc77000 ld1 {v0.8b}, \[x0\], x7
- 104: 0cc7a000 ld1 {v0.8b, v1.8b}, \[x0\], x7
+ 104: 0cc7a000 ld1 {v0.8b-v1.8b}, \[x0\], x7
108: 0cc76000 ld1 {v0.8b-v2.8b}, \[x0\], x7
10c: 0cc72000 ld1 {v0.8b-v3.8b}, \[x0\], x7
110: 0cc77400 ld1 {v0.4h}, \[x0\], x7
- 114: 0cc7a400 ld1 {v0.4h, v1.4h}, \[x0\], x7
+ 114: 0cc7a400 ld1 {v0.4h-v1.4h}, \[x0\], x7
118: 0cc76400 ld1 {v0.4h-v2.4h}, \[x0\], x7
11c: 0cc72400 ld1 {v0.4h-v3.4h}, \[x0\], x7
120: 0cc77800 ld1 {v0.2s}, \[x0\], x7
- 124: 0cc7a800 ld1 {v0.2s, v1.2s}, \[x0\], x7
+ 124: 0cc7a800 ld1 {v0.2s-v1.2s}, \[x0\], x7
128: 0cc76800 ld1 {v0.2s-v2.2s}, \[x0\], x7
12c: 0cc72800 ld1 {v0.2s-v3.2s}, \[x0\], x7
130: 0cc77c00 ld1 {v0.1d}, \[x0\], x7
- 134: 0cc7ac00 ld1 {v0.1d, v1.1d}, \[x0\], x7
+ 134: 0cc7ac00 ld1 {v0.1d-v1.1d}, \[x0\], x7
138: 0cc76c00 ld1 {v0.1d-v2.1d}, \[x0\], x7
13c: 0cc72c00 ld1 {v0.1d-v3.1d}, \[x0\], x7
140: 4cc77000 ld1 {v0.16b}, \[x0\], x7
- 144: 4cc7a000 ld1 {v0.16b, v1.16b}, \[x0\], x7
+ 144: 4cc7a000 ld1 {v0.16b-v1.16b}, \[x0\], x7
148: 4cc76000 ld1 {v0.16b-v2.16b}, \[x0\], x7
14c: 4cc72000 ld1 {v0.16b-v3.16b}, \[x0\], x7
150: 4cc77400 ld1 {v0.8h}, \[x0\], x7
- 154: 4cc7a400 ld1 {v0.8h, v1.8h}, \[x0\], x7
+ 154: 4cc7a400 ld1 {v0.8h-v1.8h}, \[x0\], x7
158: 4cc76400 ld1 {v0.8h-v2.8h}, \[x0\], x7
15c: 4cc72400 ld1 {v0.8h-v3.8h}, \[x0\], x7
160: 4cc77800 ld1 {v0.4s}, \[x0\], x7
- 164: 4cc7a800 ld1 {v0.4s, v1.4s}, \[x0\], x7
+ 164: 4cc7a800 ld1 {v0.4s-v1.4s}, \[x0\], x7
168: 4cc76800 ld1 {v0.4s-v2.4s}, \[x0\], x7
16c: 4cc72800 ld1 {v0.4s-v3.4s}, \[x0\], x7
170: 4cc77c00 ld1 {v0.2d}, \[x0\], x7
- 174: 4cc7ac00 ld1 {v0.2d, v1.2d}, \[x0\], x7
+ 174: 4cc7ac00 ld1 {v0.2d-v1.2d}, \[x0\], x7
178: 4cc76c00 ld1 {v0.2d-v2.2d}, \[x0\], x7
17c: 4cc72c00 ld1 {v0.2d-v3.2d}, \[x0\], x7
180: 0c877000 st1 {v0.8b}, \[x0\], x7
- 184: 0c87a000 st1 {v0.8b, v1.8b}, \[x0\], x7
+ 184: 0c87a000 st1 {v0.8b-v1.8b}, \[x0\], x7
188: 0c876000 st1 {v0.8b-v2.8b}, \[x0\], x7
18c: 0c872000 st1 {v0.8b-v3.8b}, \[x0\], x7
190: 0c877400 st1 {v0.4h}, \[x0\], x7
- 194: 0c87a400 st1 {v0.4h, v1.4h}, \[x0\], x7
+ 194: 0c87a400 st1 {v0.4h-v1.4h}, \[x0\], x7
198: 0c876400 st1 {v0.4h-v2.4h}, \[x0\], x7
19c: 0c872400 st1 {v0.4h-v3.4h}, \[x0\], x7
1a0: 0c877800 st1 {v0.2s}, \[x0\], x7
- 1a4: 0c87a800 st1 {v0.2s, v1.2s}, \[x0\], x7
+ 1a4: 0c87a800 st1 {v0.2s-v1.2s}, \[x0\], x7
1a8: 0c876800 st1 {v0.2s-v2.2s}, \[x0\], x7
1ac: 0c872800 st1 {v0.2s-v3.2s}, \[x0\], x7
1b0: 0c877c00 st1 {v0.1d}, \[x0\], x7
- 1b4: 0c87ac00 st1 {v0.1d, v1.1d}, \[x0\], x7
+ 1b4: 0c87ac00 st1 {v0.1d-v1.1d}, \[x0\], x7
1b8: 0c876c00 st1 {v0.1d-v2.1d}, \[x0\], x7
1bc: 0c872c00 st1 {v0.1d-v3.1d}, \[x0\], x7
1c0: 4c877000 st1 {v0.16b}, \[x0\], x7
- 1c4: 4c87a000 st1 {v0.16b, v1.16b}, \[x0\], x7
+ 1c4: 4c87a000 st1 {v0.16b-v1.16b}, \[x0\], x7
1c8: 4c876000 st1 {v0.16b-v2.16b}, \[x0\], x7
1cc: 4c872000 st1 {v0.16b-v3.16b}, \[x0\], x7
1d0: 4c877400 st1 {v0.8h}, \[x0\], x7
- 1d4: 4c87a400 st1 {v0.8h, v1.8h}, \[x0\], x7
+ 1d4: 4c87a400 st1 {v0.8h-v1.8h}, \[x0\], x7
1d8: 4c876400 st1 {v0.8h-v2.8h}, \[x0\], x7
1dc: 4c872400 st1 {v0.8h-v3.8h}, \[x0\], x7
1e0: 4c877800 st1 {v0.4s}, \[x0\], x7
- 1e4: 4c87a800 st1 {v0.4s, v1.4s}, \[x0\], x7
+ 1e4: 4c87a800 st1 {v0.4s-v1.4s}, \[x0\], x7
1e8: 4c876800 st1 {v0.4s-v2.4s}, \[x0\], x7
1ec: 4c872800 st1 {v0.4s-v3.4s}, \[x0\], x7
1f0: 4c877c00 st1 {v0.2d}, \[x0\], x7
- 1f4: 4c87ac00 st1 {v0.2d, v1.2d}, \[x0\], x7
+ 1f4: 4c87ac00 st1 {v0.2d-v1.2d}, \[x0\], x7
1f8: 4c876c00 st1 {v0.2d-v2.2d}, \[x0\], x7
1fc: 4c872c00 st1 {v0.2d-v3.2d}, \[x0\], x7
- 200: 0cdf8000 ld2 {v0.8b, v1.8b}, \[x0\], #16
- 204: 0cc78000 ld2 {v0.8b, v1.8b}, \[x0\], x7
- 208: 0cdf8400 ld2 {v0.4h, v1.4h}, \[x0\], #16
- 20c: 0cc78400 ld2 {v0.4h, v1.4h}, \[x0\], x7
- 210: 0cdf8800 ld2 {v0.2s, v1.2s}, \[x0\], #16
- 214: 0cc78800 ld2 {v0.2s, v1.2s}, \[x0\], x7
- 218: 0c9f8000 st2 {v0.8b, v1.8b}, \[x0\], #16
- 21c: 0c878000 st2 {v0.8b, v1.8b}, \[x0\], x7
- 220: 0c9f8400 st2 {v0.4h, v1.4h}, \[x0\], #16
- 224: 0c878400 st2 {v0.4h, v1.4h}, \[x0\], x7
- 228: 0c9f8800 st2 {v0.2s, v1.2s}, \[x0\], #16
- 22c: 0c878800 st2 {v0.2s, v1.2s}, \[x0\], x7
- 230: 4cdf8000 ld2 {v0.16b, v1.16b}, \[x0\], #32
- 234: 4cc78000 ld2 {v0.16b, v1.16b}, \[x0\], x7
- 238: 4cdf8400 ld2 {v0.8h, v1.8h}, \[x0\], #32
- 23c: 4cc78400 ld2 {v0.8h, v1.8h}, \[x0\], x7
- 240: 4cdf8800 ld2 {v0.4s, v1.4s}, \[x0\], #32
- 244: 4cc78800 ld2 {v0.4s, v1.4s}, \[x0\], x7
- 248: 4cdf8c00 ld2 {v0.2d, v1.2d}, \[x0\], #32
- 24c: 4cc78c00 ld2 {v0.2d, v1.2d}, \[x0\], x7
- 250: 4c9f8000 st2 {v0.16b, v1.16b}, \[x0\], #32
- 254: 4c878000 st2 {v0.16b, v1.16b}, \[x0\], x7
- 258: 4c9f8400 st2 {v0.8h, v1.8h}, \[x0\], #32
- 25c: 4c878400 st2 {v0.8h, v1.8h}, \[x0\], x7
- 260: 4c9f8800 st2 {v0.4s, v1.4s}, \[x0\], #32
- 264: 4c878800 st2 {v0.4s, v1.4s}, \[x0\], x7
- 268: 4c9f8c00 st2 {v0.2d, v1.2d}, \[x0\], #32
- 26c: 4c878c00 st2 {v0.2d, v1.2d}, \[x0\], x7
+ 200: 0cdf8000 ld2 {v0.8b-v1.8b}, \[x0\], #16
+ 204: 0cc78000 ld2 {v0.8b-v1.8b}, \[x0\], x7
+ 208: 0cdf8400 ld2 {v0.4h-v1.4h}, \[x0\], #16
+ 20c: 0cc78400 ld2 {v0.4h-v1.4h}, \[x0\], x7
+ 210: 0cdf8800 ld2 {v0.2s-v1.2s}, \[x0\], #16
+ 214: 0cc78800 ld2 {v0.2s-v1.2s}, \[x0\], x7
+ 218: 0c9f8000 st2 {v0.8b-v1.8b}, \[x0\], #16
+ 21c: 0c878000 st2 {v0.8b-v1.8b}, \[x0\], x7
+ 220: 0c9f8400 st2 {v0.4h-v1.4h}, \[x0\], #16
+ 224: 0c878400 st2 {v0.4h-v1.4h}, \[x0\], x7
+ 228: 0c9f8800 st2 {v0.2s-v1.2s}, \[x0\], #16
+ 22c: 0c878800 st2 {v0.2s-v1.2s}, \[x0\], x7
+ 230: 4cdf8000 ld2 {v0.16b-v1.16b}, \[x0\], #32
+ 234: 4cc78000 ld2 {v0.16b-v1.16b}, \[x0\], x7
+ 238: 4cdf8400 ld2 {v0.8h-v1.8h}, \[x0\], #32
+ 23c: 4cc78400 ld2 {v0.8h-v1.8h}, \[x0\], x7
+ 240: 4cdf8800 ld2 {v0.4s-v1.4s}, \[x0\], #32
+ 244: 4cc78800 ld2 {v0.4s-v1.4s}, \[x0\], x7
+ 248: 4cdf8c00 ld2 {v0.2d-v1.2d}, \[x0\], #32
+ 24c: 4cc78c00 ld2 {v0.2d-v1.2d}, \[x0\], x7
+ 250: 4c9f8000 st2 {v0.16b-v1.16b}, \[x0\], #32
+ 254: 4c878000 st2 {v0.16b-v1.16b}, \[x0\], x7
+ 258: 4c9f8400 st2 {v0.8h-v1.8h}, \[x0\], #32
+ 25c: 4c878400 st2 {v0.8h-v1.8h}, \[x0\], x7
+ 260: 4c9f8800 st2 {v0.4s-v1.4s}, \[x0\], #32
+ 264: 4c878800 st2 {v0.4s-v1.4s}, \[x0\], x7
+ 268: 4c9f8c00 st2 {v0.2d-v1.2d}, \[x0\], #32
+ 26c: 4c878c00 st2 {v0.2d-v1.2d}, \[x0\], x7
270: 0cdf4000 ld3 {v0.8b-v2.8b}, \[x0\], #24
274: 0cdf0000 ld4 {v0.8b-v3.8b}, \[x0\], #32
278: 0cc74000 ld3 {v0.8b-v2.8b}, \[x0\], x7
@@ -218,130 +218,130 @@ Disassembly of section \.text:
348: 4c874c00 st3 {v0.2d-v2.2d}, \[x0\], x7
34c: 4c870c00 st4 {v0.2d-v3.2d}, \[x0\], x7
350: 0ddf0400 ld1 {v0.b}\[1\], \[x0\], #1
- 354: 0dff0400 ld2 {v0.b, v1.b}\[1\], \[x0\], #2
+ 354: 0dff0400 ld2 {v0.b-v1.b}\[1\], \[x0\], #2
358: 0ddf2400 ld3 {v0.b-v2.b}\[1\], \[x0\], #3
35c: 0dff2400 ld4 {v0.b-v3.b}\[1\], \[x0\], #4
360: 0ddfc000 ld1r {v0.8b}, \[x0\], #1
- 364: 0dffc000 ld2r {v0.8b, v1.8b}, \[x0\], #2
+ 364: 0dffc000 ld2r {v0.8b-v1.8b}, \[x0\], #2
368: 0ddfe000 ld3r {v0.8b-v2.8b}, \[x0\], #3
36c: 0dffe000 ld4r {v0.8b-v3.8b}, \[x0\], #4
370: 4ddfc000 ld1r {v0.16b}, \[x0\], #1
- 374: 4dffc000 ld2r {v0.16b, v1.16b}, \[x0\], #2
+ 374: 4dffc000 ld2r {v0.16b-v1.16b}, \[x0\], #2
378: 4ddfe000 ld3r {v0.16b-v2.16b}, \[x0\], #3
37c: 4dffe000 ld4r {v0.16b-v3.16b}, \[x0\], #4
380: 0d9f0400 st1 {v0.b}\[1\], \[x0\], #1
- 384: 0dbf0400 st2 {v0.b, v1.b}\[1\], \[x0\], #2
+ 384: 0dbf0400 st2 {v0.b-v1.b}\[1\], \[x0\], #2
388: 0d9f2400 st3 {v0.b-v2.b}\[1\], \[x0\], #3
38c: 0dbf2400 st4 {v0.b-v3.b}\[1\], \[x0\], #4
390: 0ddf4800 ld1 {v0.h}\[1\], \[x0\], #2
- 394: 0dff4800 ld2 {v0.h, v1.h}\[1\], \[x0\], #4
+ 394: 0dff4800 ld2 {v0.h-v1.h}\[1\], \[x0\], #4
398: 0ddf6800 ld3 {v0.h-v2.h}\[1\], \[x0\], #6
39c: 0dff6800 ld4 {v0.h-v3.h}\[1\], \[x0\], #8
3a0: 0ddfc400 ld1r {v0.4h}, \[x0\], #2
- 3a4: 0dffc400 ld2r {v0.4h, v1.4h}, \[x0\], #4
+ 3a4: 0dffc400 ld2r {v0.4h-v1.4h}, \[x0\], #4
3a8: 0ddfe400 ld3r {v0.4h-v2.4h}, \[x0\], #6
3ac: 0dffe400 ld4r {v0.4h-v3.4h}, \[x0\], #8
3b0: 4ddfc400 ld1r {v0.8h}, \[x0\], #2
- 3b4: 4dffc400 ld2r {v0.8h, v1.8h}, \[x0\], #4
+ 3b4: 4dffc400 ld2r {v0.8h-v1.8h}, \[x0\], #4
3b8: 4ddfe400 ld3r {v0.8h-v2.8h}, \[x0\], #6
3bc: 4dffe400 ld4r {v0.8h-v3.8h}, \[x0\], #8
3c0: 0d9f4800 st1 {v0.h}\[1\], \[x0\], #2
- 3c4: 0dbf4800 st2 {v0.h, v1.h}\[1\], \[x0\], #4
+ 3c4: 0dbf4800 st2 {v0.h-v1.h}\[1\], \[x0\], #4
3c8: 0d9f6800 st3 {v0.h-v2.h}\[1\], \[x0\], #6
3cc: 0dbf6800 st4 {v0.h-v3.h}\[1\], \[x0\], #8
3d0: 0ddf9000 ld1 {v0.s}\[1\], \[x0\], #4
- 3d4: 0dff9000 ld2 {v0.s, v1.s}\[1\], \[x0\], #8
+ 3d4: 0dff9000 ld2 {v0.s-v1.s}\[1\], \[x0\], #8
3d8: 0ddfb000 ld3 {v0.s-v2.s}\[1\], \[x0\], #12
3dc: 0dffb000 ld4 {v0.s-v3.s}\[1\], \[x0\], #16
3e0: 0ddfc800 ld1r {v0.2s}, \[x0\], #4
- 3e4: 0dffc800 ld2r {v0.2s, v1.2s}, \[x0\], #8
+ 3e4: 0dffc800 ld2r {v0.2s-v1.2s}, \[x0\], #8
3e8: 0ddfe800 ld3r {v0.2s-v2.2s}, \[x0\], #12
3ec: 0dffe800 ld4r {v0.2s-v3.2s}, \[x0\], #16
3f0: 4ddfc800 ld1r {v0.4s}, \[x0\], #4
- 3f4: 4dffc800 ld2r {v0.4s, v1.4s}, \[x0\], #8
+ 3f4: 4dffc800 ld2r {v0.4s-v1.4s}, \[x0\], #8
3f8: 4ddfe800 ld3r {v0.4s-v2.4s}, \[x0\], #12
3fc: 4dffe800 ld4r {v0.4s-v3.4s}, \[x0\], #16
400: 0d9f9000 st1 {v0.s}\[1\], \[x0\], #4
- 404: 0dbf9000 st2 {v0.s, v1.s}\[1\], \[x0\], #8
+ 404: 0dbf9000 st2 {v0.s-v1.s}\[1\], \[x0\], #8
408: 0d9fb000 st3 {v0.s-v2.s}\[1\], \[x0\], #12
40c: 0dbfb000 st4 {v0.s-v3.s}\[1\], \[x0\], #16
410: 4ddf8400 ld1 {v0.d}\[1\], \[x0\], #8
- 414: 4dff8400 ld2 {v0.d, v1.d}\[1\], \[x0\], #16
+ 414: 4dff8400 ld2 {v0.d-v1.d}\[1\], \[x0\], #16
418: 4ddfa400 ld3 {v0.d-v2.d}\[1\], \[x0\], #24
41c: 4dffa400 ld4 {v0.d-v3.d}\[1\], \[x0\], #32
420: 0ddfcc00 ld1r {v0.1d}, \[x0\], #8
- 424: 0dffcc00 ld2r {v0.1d, v1.1d}, \[x0\], #16
+ 424: 0dffcc00 ld2r {v0.1d-v1.1d}, \[x0\], #16
428: 0ddfec00 ld3r {v0.1d-v2.1d}, \[x0\], #24
42c: 0dffec00 ld4r {v0.1d-v3.1d}, \[x0\], #32
430: 4ddfcc00 ld1r {v0.2d}, \[x0\], #8
- 434: 4dffcc00 ld2r {v0.2d, v1.2d}, \[x0\], #16
+ 434: 4dffcc00 ld2r {v0.2d-v1.2d}, \[x0\], #16
438: 4ddfec00 ld3r {v0.2d-v2.2d}, \[x0\], #24
43c: 4dffec00 ld4r {v0.2d-v3.2d}, \[x0\], #32
440: 4d9f8400 st1 {v0.d}\[1\], \[x0\], #8
- 444: 4dbf8400 st2 {v0.d, v1.d}\[1\], \[x0\], #16
+ 444: 4dbf8400 st2 {v0.d-v1.d}\[1\], \[x0\], #16
448: 4d9fa400 st3 {v0.d-v2.d}\[1\], \[x0\], #24
44c: 4dbfa400 st4 {v0.d-v3.d}\[1\], \[x0\], #32
450: 0dc70400 ld1 {v0.b}\[1\], \[x0\], x7
- 454: 0de70400 ld2 {v0.b, v1.b}\[1\], \[x0\], x7
+ 454: 0de70400 ld2 {v0.b-v1.b}\[1\], \[x0\], x7
458: 0dc72400 ld3 {v0.b-v2.b}\[1\], \[x0\], x7
45c: 0de72400 ld4 {v0.b-v3.b}\[1\], \[x0\], x7
460: 0dc74800 ld1 {v0.h}\[1\], \[x0\], x7
- 464: 0de74800 ld2 {v0.h, v1.h}\[1\], \[x0\], x7
+ 464: 0de74800 ld2 {v0.h-v1.h}\[1\], \[x0\], x7
468: 0dc76800 ld3 {v0.h-v2.h}\[1\], \[x0\], x7
46c: 0de76800 ld4 {v0.h-v3.h}\[1\], \[x0\], x7
470: 0dc79000 ld1 {v0.s}\[1\], \[x0\], x7
- 474: 0de79000 ld2 {v0.s, v1.s}\[1\], \[x0\], x7
+ 474: 0de79000 ld2 {v0.s-v1.s}\[1\], \[x0\], x7
478: 0dc7b000 ld3 {v0.s-v2.s}\[1\], \[x0\], x7
47c: 0de7b000 ld4 {v0.s-v3.s}\[1\], \[x0\], x7
480: 4dc78400 ld1 {v0.d}\[1\], \[x0\], x7
- 484: 4de78400 ld2 {v0.d, v1.d}\[1\], \[x0\], x7
+ 484: 4de78400 ld2 {v0.d-v1.d}\[1\], \[x0\], x7
488: 4dc7a400 ld3 {v0.d-v2.d}\[1\], \[x0\], x7
48c: 4de7a400 ld4 {v0.d-v3.d}\[1\], \[x0\], x7
490: 0dc7c000 ld1r {v0.8b}, \[x0\], x7
- 494: 0de7c000 ld2r {v0.8b, v1.8b}, \[x0\], x7
+ 494: 0de7c000 ld2r {v0.8b-v1.8b}, \[x0\], x7
498: 0dc7e000 ld3r {v0.8b-v2.8b}, \[x0\], x7
49c: 0de7e000 ld4r {v0.8b-v3.8b}, \[x0\], x7
4a0: 4dc7c000 ld1r {v0.16b}, \[x0\], x7
- 4a4: 4de7c000 ld2r {v0.16b, v1.16b}, \[x0\], x7
+ 4a4: 4de7c000 ld2r {v0.16b-v1.16b}, \[x0\], x7
4a8: 4dc7e000 ld3r {v0.16b-v2.16b}, \[x0\], x7
4ac: 4de7e000 ld4r {v0.16b-v3.16b}, \[x0\], x7
4b0: 0dc7c400 ld1r {v0.4h}, \[x0\], x7
- 4b4: 0de7c400 ld2r {v0.4h, v1.4h}, \[x0\], x7
+ 4b4: 0de7c400 ld2r {v0.4h-v1.4h}, \[x0\], x7
4b8: 0dc7e400 ld3r {v0.4h-v2.4h}, \[x0\], x7
4bc: 0de7e400 ld4r {v0.4h-v3.4h}, \[x0\], x7
4c0: 4dc7c400 ld1r {v0.8h}, \[x0\], x7
- 4c4: 4de7c400 ld2r {v0.8h, v1.8h}, \[x0\], x7
+ 4c4: 4de7c400 ld2r {v0.8h-v1.8h}, \[x0\], x7
4c8: 4dc7e400 ld3r {v0.8h-v2.8h}, \[x0\], x7
4cc: 4de7e400 ld4r {v0.8h-v3.8h}, \[x0\], x7
4d0: 0dc7c800 ld1r {v0.2s}, \[x0\], x7
- 4d4: 0de7c800 ld2r {v0.2s, v1.2s}, \[x0\], x7
+ 4d4: 0de7c800 ld2r {v0.2s-v1.2s}, \[x0\], x7
4d8: 0dc7e800 ld3r {v0.2s-v2.2s}, \[x0\], x7
4dc: 0de7e800 ld4r {v0.2s-v3.2s}, \[x0\], x7
4e0: 4dc7c800 ld1r {v0.4s}, \[x0\], x7
- 4e4: 4de7c800 ld2r {v0.4s, v1.4s}, \[x0\], x7
+ 4e4: 4de7c800 ld2r {v0.4s-v1.4s}, \[x0\], x7
4e8: 4dc7e800 ld3r {v0.4s-v2.4s}, \[x0\], x7
4ec: 4de7e800 ld4r {v0.4s-v3.4s}, \[x0\], x7
4f0: 0dc7cc00 ld1r {v0.1d}, \[x0\], x7
- 4f4: 0de7cc00 ld2r {v0.1d, v1.1d}, \[x0\], x7
+ 4f4: 0de7cc00 ld2r {v0.1d-v1.1d}, \[x0\], x7
4f8: 0dc7ec00 ld3r {v0.1d-v2.1d}, \[x0\], x7
4fc: 0de7ec00 ld4r {v0.1d-v3.1d}, \[x0\], x7
500: 4dc7cc00 ld1r {v0.2d}, \[x0\], x7
- 504: 4de7cc00 ld2r {v0.2d, v1.2d}, \[x0\], x7
+ 504: 4de7cc00 ld2r {v0.2d-v1.2d}, \[x0\], x7
508: 4dc7ec00 ld3r {v0.2d-v2.2d}, \[x0\], x7
50c: 4de7ec00 ld4r {v0.2d-v3.2d}, \[x0\], x7
510: 0d870400 st1 {v0.b}\[1\], \[x0\], x7
- 514: 0da70400 st2 {v0.b, v1.b}\[1\], \[x0\], x7
+ 514: 0da70400 st2 {v0.b-v1.b}\[1\], \[x0\], x7
518: 0d872400 st3 {v0.b-v2.b}\[1\], \[x0\], x7
51c: 0da72400 st4 {v0.b-v3.b}\[1\], \[x0\], x7
520: 0d874800 st1 {v0.h}\[1\], \[x0\], x7
- 524: 0da74800 st2 {v0.h, v1.h}\[1\], \[x0\], x7
+ 524: 0da74800 st2 {v0.h-v1.h}\[1\], \[x0\], x7
528: 0d876800 st3 {v0.h-v2.h}\[1\], \[x0\], x7
52c: 0da76800 st4 {v0.h-v3.h}\[1\], \[x0\], x7
530: 0d879000 st1 {v0.s}\[1\], \[x0\], x7
- 534: 0da79000 st2 {v0.s, v1.s}\[1\], \[x0\], x7
+ 534: 0da79000 st2 {v0.s-v1.s}\[1\], \[x0\], x7
538: 0d87b000 st3 {v0.s-v2.s}\[1\], \[x0\], x7
53c: 0da7b000 st4 {v0.s-v3.s}\[1\], \[x0\], x7
540: 4d878400 st1 {v0.d}\[1\], \[x0\], x7
- 544: 4da78400 st2 {v0.d, v1.d}\[1\], \[x0\], x7
+ 544: 4da78400 st2 {v0.d-v1.d}\[1\], \[x0\], x7
548: 4d87a400 st3 {v0.d-v2.d}\[1\], \[x0\], x7
54c: 4da7a400 st4 {v0.d-v3.d}\[1\], \[x0\], x7
diff --git a/gas/testsuite/gas/aarch64/neon-vfp-reglist.d b/gas/testsuite/gas/aarch64/neon-vfp-reglist.d
index ad779685d4d..a8e7c2df7c2 100644
--- a/gas/testsuite/gas/aarch64/neon-vfp-reglist.d
+++ b/gas/testsuite/gas/aarch64/neon-vfp-reglist.d
@@ -6,188 +6,188 @@ Disassembly of section \.text:
0+ <.*>:
0: 0c407000 ld1 {v0.8b}, \[x0\]
- 4: 0c40a000 ld1 {v0.8b, v1.8b}, \[x0\]
+ 4: 0c40a000 ld1 {v0.8b-v1.8b}, \[x0\]
8: 0c406000 ld1 {v0.8b-v2.8b}, \[x0\]
c: 0c402000 ld1 {v0.8b-v3.8b}, \[x0\]
- 10: 0c408000 ld2 {v0.8b, v1.8b}, \[x0\]
+ 10: 0c408000 ld2 {v0.8b-v1.8b}, \[x0\]
14: 0c404000 ld3 {v0.8b-v2.8b}, \[x0\]
18: 0c400000 ld4 {v0.8b-v3.8b}, \[x0\]
1c: 0c007000 st1 {v0.8b}, \[x0\]
- 20: 0c00a000 st1 {v0.8b, v1.8b}, \[x0\]
+ 20: 0c00a000 st1 {v0.8b-v1.8b}, \[x0\]
24: 0c006000 st1 {v0.8b-v2.8b}, \[x0\]
28: 0c002000 st1 {v0.8b-v3.8b}, \[x0\]
- 2c: 0c008000 st2 {v0.8b, v1.8b}, \[x0\]
+ 2c: 0c008000 st2 {v0.8b-v1.8b}, \[x0\]
30: 0c004000 st3 {v0.8b-v2.8b}, \[x0\]
34: 0c000000 st4 {v0.8b-v3.8b}, \[x0\]
38: 4c407000 ld1 {v0.16b}, \[x0\]
- 3c: 4c40a000 ld1 {v0.16b, v1.16b}, \[x0\]
+ 3c: 4c40a000 ld1 {v0.16b-v1.16b}, \[x0\]
40: 4c406000 ld1 {v0.16b-v2.16b}, \[x0\]
44: 4c402000 ld1 {v0.16b-v3.16b}, \[x0\]
- 48: 4c408000 ld2 {v0.16b, v1.16b}, \[x0\]
+ 48: 4c408000 ld2 {v0.16b-v1.16b}, \[x0\]
4c: 4c404000 ld3 {v0.16b-v2.16b}, \[x0\]
50: 4c400000 ld4 {v0.16b-v3.16b}, \[x0\]
54: 4c007000 st1 {v0.16b}, \[x0\]
- 58: 4c00a000 st1 {v0.16b, v1.16b}, \[x0\]
+ 58: 4c00a000 st1 {v0.16b-v1.16b}, \[x0\]
5c: 4c006000 st1 {v0.16b-v2.16b}, \[x0\]
60: 4c002000 st1 {v0.16b-v3.16b}, \[x0\]
- 64: 4c008000 st2 {v0.16b, v1.16b}, \[x0\]
+ 64: 4c008000 st2 {v0.16b-v1.16b}, \[x0\]
68: 4c004000 st3 {v0.16b-v2.16b}, \[x0\]
6c: 4c000000 st4 {v0.16b-v3.16b}, \[x0\]
70: 0c407400 ld1 {v0.4h}, \[x0\]
- 74: 0c40a400 ld1 {v0.4h, v1.4h}, \[x0\]
+ 74: 0c40a400 ld1 {v0.4h-v1.4h}, \[x0\]
78: 0c406400 ld1 {v0.4h-v2.4h}, \[x0\]
7c: 0c402400 ld1 {v0.4h-v3.4h}, \[x0\]
- 80: 0c408400 ld2 {v0.4h, v1.4h}, \[x0\]
+ 80: 0c408400 ld2 {v0.4h-v1.4h}, \[x0\]
84: 0c404400 ld3 {v0.4h-v2.4h}, \[x0\]
88: 0c400400 ld4 {v0.4h-v3.4h}, \[x0\]
8c: 0c007400 st1 {v0.4h}, \[x0\]
- 90: 0c00a400 st1 {v0.4h, v1.4h}, \[x0\]
+ 90: 0c00a400 st1 {v0.4h-v1.4h}, \[x0\]
94: 0c006400 st1 {v0.4h-v2.4h}, \[x0\]
98: 0c002400 st1 {v0.4h-v3.4h}, \[x0\]
- 9c: 0c008400 st2 {v0.4h, v1.4h}, \[x0\]
+ 9c: 0c008400 st2 {v0.4h-v1.4h}, \[x0\]
a0: 0c004400 st3 {v0.4h-v2.4h}, \[x0\]
a4: 0c000400 st4 {v0.4h-v3.4h}, \[x0\]
a8: 4c407400 ld1 {v0.8h}, \[x0\]
- ac: 4c40a400 ld1 {v0.8h, v1.8h}, \[x0\]
+ ac: 4c40a400 ld1 {v0.8h-v1.8h}, \[x0\]
b0: 4c406400 ld1 {v0.8h-v2.8h}, \[x0\]
b4: 4c402400 ld1 {v0.8h-v3.8h}, \[x0\]
- b8: 4c408400 ld2 {v0.8h, v1.8h}, \[x0\]
+ b8: 4c408400 ld2 {v0.8h-v1.8h}, \[x0\]
bc: 4c404400 ld3 {v0.8h-v2.8h}, \[x0\]
c0: 4c400400 ld4 {v0.8h-v3.8h}, \[x0\]
c4: 4c007400 st1 {v0.8h}, \[x0\]
- c8: 4c00a400 st1 {v0.8h, v1.8h}, \[x0\]
+ c8: 4c00a400 st1 {v0.8h-v1.8h}, \[x0\]
cc: 4c006400 st1 {v0.8h-v2.8h}, \[x0\]
d0: 4c002400 st1 {v0.8h-v3.8h}, \[x0\]
- d4: 4c008400 st2 {v0.8h, v1.8h}, \[x0\]
+ d4: 4c008400 st2 {v0.8h-v1.8h}, \[x0\]
d8: 4c004400 st3 {v0.8h-v2.8h}, \[x0\]
dc: 4c000400 st4 {v0.8h-v3.8h}, \[x0\]
e0: 0c407800 ld1 {v0.2s}, \[x0\]
- e4: 0c40a800 ld1 {v0.2s, v1.2s}, \[x0\]
+ e4: 0c40a800 ld1 {v0.2s-v1.2s}, \[x0\]
e8: 0c406800 ld1 {v0.2s-v2.2s}, \[x0\]
ec: 0c402800 ld1 {v0.2s-v3.2s}, \[x0\]
- f0: 0c408800 ld2 {v0.2s, v1.2s}, \[x0\]
+ f0: 0c408800 ld2 {v0.2s-v1.2s}, \[x0\]
f4: 0c404800 ld3 {v0.2s-v2.2s}, \[x0\]
f8: 0c400800 ld4 {v0.2s-v3.2s}, \[x0\]
fc: 0c007800 st1 {v0.2s}, \[x0\]
- 100: 0c00a800 st1 {v0.2s, v1.2s}, \[x0\]
+ 100: 0c00a800 st1 {v0.2s-v1.2s}, \[x0\]
104: 0c006800 st1 {v0.2s-v2.2s}, \[x0\]
108: 0c002800 st1 {v0.2s-v3.2s}, \[x0\]
- 10c: 0c008800 st2 {v0.2s, v1.2s}, \[x0\]
+ 10c: 0c008800 st2 {v0.2s-v1.2s}, \[x0\]
110: 0c004800 st3 {v0.2s-v2.2s}, \[x0\]
114: 0c000800 st4 {v0.2s-v3.2s}, \[x0\]
118: 4c407800 ld1 {v0.4s}, \[x0\]
- 11c: 4c40a800 ld1 {v0.4s, v1.4s}, \[x0\]
+ 11c: 4c40a800 ld1 {v0.4s-v1.4s}, \[x0\]
120: 4c406800 ld1 {v0.4s-v2.4s}, \[x0\]
124: 4c402800 ld1 {v0.4s-v3.4s}, \[x0\]
- 128: 4c408800 ld2 {v0.4s, v1.4s}, \[x0\]
+ 128: 4c408800 ld2 {v0.4s-v1.4s}, \[x0\]
12c: 4c404800 ld3 {v0.4s-v2.4s}, \[x0\]
130: 4c400800 ld4 {v0.4s-v3.4s}, \[x0\]
134: 4c007800 st1 {v0.4s}, \[x0\]
- 138: 4c00a800 st1 {v0.4s, v1.4s}, \[x0\]
+ 138: 4c00a800 st1 {v0.4s-v1.4s}, \[x0\]
13c: 4c006800 st1 {v0.4s-v2.4s}, \[x0\]
140: 4c002800 st1 {v0.4s-v3.4s}, \[x0\]
- 144: 4c008800 st2 {v0.4s, v1.4s}, \[x0\]
+ 144: 4c008800 st2 {v0.4s-v1.4s}, \[x0\]
148: 4c004800 st3 {v0.4s-v2.4s}, \[x0\]
14c: 4c000800 st4 {v0.4s-v3.4s}, \[x0\]
150: 4c407c00 ld1 {v0.2d}, \[x0\]
- 154: 4c40ac00 ld1 {v0.2d, v1.2d}, \[x0\]
+ 154: 4c40ac00 ld1 {v0.2d-v1.2d}, \[x0\]
158: 4c406c00 ld1 {v0.2d-v2.2d}, \[x0\]
15c: 4c402c00 ld1 {v0.2d-v3.2d}, \[x0\]
- 160: 4c408c00 ld2 {v0.2d, v1.2d}, \[x0\]
+ 160: 4c408c00 ld2 {v0.2d-v1.2d}, \[x0\]
164: 4c404c00 ld3 {v0.2d-v2.2d}, \[x0\]
168: 4c400c00 ld4 {v0.2d-v3.2d}, \[x0\]
16c: 4c007c00 st1 {v0.2d}, \[x0\]
- 170: 4c00ac00 st1 {v0.2d, v1.2d}, \[x0\]
+ 170: 4c00ac00 st1 {v0.2d-v1.2d}, \[x0\]
174: 4c006c00 st1 {v0.2d-v2.2d}, \[x0\]
178: 4c002c00 st1 {v0.2d-v3.2d}, \[x0\]
- 17c: 4c008c00 st2 {v0.2d, v1.2d}, \[x0\]
+ 17c: 4c008c00 st2 {v0.2d-v1.2d}, \[x0\]
180: 4c004c00 st3 {v0.2d-v2.2d}, \[x0\]
184: 4c000c00 st4 {v0.2d-v3.2d}, \[x0\]
188: 0d400400 ld1 {v0.b}\[1\], \[x0\]
- 18c: 0d600400 ld2 {v0.b, v1.b}\[1\], \[x0\]
+ 18c: 0d600400 ld2 {v0.b-v1.b}\[1\], \[x0\]
190: 0d402400 ld3 {v0.b-v2.b}\[1\], \[x0\]
194: 0d602400 ld4 {v0.b-v3.b}\[1\], \[x0\]
198: 0d000400 st1 {v0.b}\[1\], \[x0\]
- 19c: 0d200400 st2 {v0.b, v1.b}\[1\], \[x0\]
+ 19c: 0d200400 st2 {v0.b-v1.b}\[1\], \[x0\]
1a0: 0d002400 st3 {v0.b-v2.b}\[1\], \[x0\]
1a4: 0d202400 st4 {v0.b-v3.b}\[1\], \[x0\]
1a8: 0d400400 ld1 {v0.b}\[1\], \[x0\]
- 1ac: 0d600400 ld2 {v0.b, v1.b}\[1\], \[x0\]
+ 1ac: 0d600400 ld2 {v0.b-v1.b}\[1\], \[x0\]
1b0: 0d402400 ld3 {v0.b-v2.b}\[1\], \[x0\]
1b4: 0d602400 ld4 {v0.b-v3.b}\[1\], \[x0\]
1b8: 0d000400 st1 {v0.b}\[1\], \[x0\]
- 1bc: 0d200400 st2 {v0.b, v1.b}\[1\], \[x0\]
+ 1bc: 0d200400 st2 {v0.b-v1.b}\[1\], \[x0\]
1c0: 0d002400 st3 {v0.b-v2.b}\[1\], \[x0\]
1c4: 0d202400 st4 {v0.b-v3.b}\[1\], \[x0\]
1c8: 0d404800 ld1 {v0.h}\[1\], \[x0\]
- 1cc: 0d604800 ld2 {v0.h, v1.h}\[1\], \[x0\]
+ 1cc: 0d604800 ld2 {v0.h-v1.h}\[1\], \[x0\]
1d0: 0d406800 ld3 {v0.h-v2.h}\[1\], \[x0\]
1d4: 0d606800 ld4 {v0.h-v3.h}\[1\], \[x0\]
1d8: 0d004800 st1 {v0.h}\[1\], \[x0\]
- 1dc: 0d204800 st2 {v0.h, v1.h}\[1\], \[x0\]
+ 1dc: 0d204800 st2 {v0.h-v1.h}\[1\], \[x0\]
1e0: 0d006800 st3 {v0.h-v2.h}\[1\], \[x0\]
1e4: 0d206800 st4 {v0.h-v3.h}\[1\], \[x0\]
1e8: 0d404800 ld1 {v0.h}\[1\], \[x0\]
- 1ec: 0d604800 ld2 {v0.h, v1.h}\[1\], \[x0\]
+ 1ec: 0d604800 ld2 {v0.h-v1.h}\[1\], \[x0\]
1f0: 0d406800 ld3 {v0.h-v2.h}\[1\], \[x0\]
1f4: 0d606800 ld4 {v0.h-v3.h}\[1\], \[x0\]
1f8: 0d004800 st1 {v0.h}\[1\], \[x0\]
- 1fc: 0d204800 st2 {v0.h, v1.h}\[1\], \[x0\]
+ 1fc: 0d204800 st2 {v0.h-v1.h}\[1\], \[x0\]
200: 0d006800 st3 {v0.h-v2.h}\[1\], \[x0\]
204: 0d206800 st4 {v0.h-v3.h}\[1\], \[x0\]
208: 0d409000 ld1 {v0.s}\[1\], \[x0\]
- 20c: 0d609000 ld2 {v0.s, v1.s}\[1\], \[x0\]
+ 20c: 0d609000 ld2 {v0.s-v1.s}\[1\], \[x0\]
210: 0d40b000 ld3 {v0.s-v2.s}\[1\], \[x0\]
214: 0d60b000 ld4 {v0.s-v3.s}\[1\], \[x0\]
218: 0d009000 st1 {v0.s}\[1\], \[x0\]
- 21c: 0d209000 st2 {v0.s, v1.s}\[1\], \[x0\]
+ 21c: 0d209000 st2 {v0.s-v1.s}\[1\], \[x0\]
220: 0d00b000 st3 {v0.s-v2.s}\[1\], \[x0\]
224: 0d20b000 st4 {v0.s-v3.s}\[1\], \[x0\]
228: 0d409000 ld1 {v0.s}\[1\], \[x0\]
- 22c: 0d609000 ld2 {v0.s, v1.s}\[1\], \[x0\]
+ 22c: 0d609000 ld2 {v0.s-v1.s}\[1\], \[x0\]
230: 0d40b000 ld3 {v0.s-v2.s}\[1\], \[x0\]
234: 0d60b000 ld4 {v0.s-v3.s}\[1\], \[x0\]
238: 0d009000 st1 {v0.s}\[1\], \[x0\]
- 23c: 0d209000 st2 {v0.s, v1.s}\[1\], \[x0\]
+ 23c: 0d209000 st2 {v0.s-v1.s}\[1\], \[x0\]
240: 0d00b000 st3 {v0.s-v2.s}\[1\], \[x0\]
244: 0d20b000 st4 {v0.s-v3.s}\[1\], \[x0\]
248: 4d408400 ld1 {v0.d}\[1\], \[x0\]
- 24c: 4d608400 ld2 {v0.d, v1.d}\[1\], \[x0\]
+ 24c: 4d608400 ld2 {v0.d-v1.d}\[1\], \[x0\]
250: 4d40a400 ld3 {v0.d-v2.d}\[1\], \[x0\]
254: 4d60a400 ld4 {v0.d-v3.d}\[1\], \[x0\]
258: 4d008400 st1 {v0.d}\[1\], \[x0\]
- 25c: 4d208400 st2 {v0.d, v1.d}\[1\], \[x0\]
+ 25c: 4d208400 st2 {v0.d-v1.d}\[1\], \[x0\]
260: 4d00a400 st3 {v0.d-v2.d}\[1\], \[x0\]
264: 4d20a400 st4 {v0.d-v3.d}\[1\], \[x0\]
268: 0d40c000 ld1r {v0.8b}, \[x0\]
- 26c: 0d60c000 ld2r {v0.8b, v1.8b}, \[x0\]
+ 26c: 0d60c000 ld2r {v0.8b-v1.8b}, \[x0\]
270: 0d40e000 ld3r {v0.8b-v2.8b}, \[x0\]
274: 0d60e000 ld4r {v0.8b-v3.8b}, \[x0\]
278: 4d40c000 ld1r {v0.16b}, \[x0\]
- 27c: 4d60c000 ld2r {v0.16b, v1.16b}, \[x0\]
+ 27c: 4d60c000 ld2r {v0.16b-v1.16b}, \[x0\]
280: 4d40e000 ld3r {v0.16b-v2.16b}, \[x0\]
284: 4d60e000 ld4r {v0.16b-v3.16b}, \[x0\]
288: 0d40c400 ld1r {v0.4h}, \[x0\]
- 28c: 0d60c400 ld2r {v0.4h, v1.4h}, \[x0\]
+ 28c: 0d60c400 ld2r {v0.4h-v1.4h}, \[x0\]
290: 0d40e400 ld3r {v0.4h-v2.4h}, \[x0\]
294: 0d60e400 ld4r {v0.4h-v3.4h}, \[x0\]
298: 4d40c400 ld1r {v0.8h}, \[x0\]
- 29c: 4d60c400 ld2r {v0.8h, v1.8h}, \[x0\]
+ 29c: 4d60c400 ld2r {v0.8h-v1.8h}, \[x0\]
2a0: 4d40e400 ld3r {v0.8h-v2.8h}, \[x0\]
2a4: 4d60e400 ld4r {v0.8h-v3.8h}, \[x0\]
2a8: 0d40c800 ld1r {v0.2s}, \[x0\]
- 2ac: 0d60c800 ld2r {v0.2s, v1.2s}, \[x0\]
+ 2ac: 0d60c800 ld2r {v0.2s-v1.2s}, \[x0\]
2b0: 0d40e800 ld3r {v0.2s-v2.2s}, \[x0\]
2b4: 0d60e800 ld4r {v0.2s-v3.2s}, \[x0\]
2b8: 4d40c800 ld1r {v0.4s}, \[x0\]
- 2bc: 4d60c800 ld2r {v0.4s, v1.4s}, \[x0\]
+ 2bc: 4d60c800 ld2r {v0.4s-v1.4s}, \[x0\]
2c0: 4d40e800 ld3r {v0.4s-v2.4s}, \[x0\]
2c4: 4d60e800 ld4r {v0.4s-v3.4s}, \[x0\]
2c8: 0d40cc00 ld1r {v0.1d}, \[x0\]
- 2cc: 0d60cc00 ld2r {v0.1d, v1.1d}, \[x0\]
+ 2cc: 0d60cc00 ld2r {v0.1d-v1.1d}, \[x0\]
2d0: 0d40ec00 ld3r {v0.1d-v2.1d}, \[x0\]
2d4: 0d60ec00 ld4r {v0.1d-v3.1d}, \[x0\]
2d8: 4d40cc00 ld1r {v0.2d}, \[x0\]
- 2dc: 4d60cc00 ld2r {v0.2d, v1.2d}, \[x0\]
+ 2dc: 4d60cc00 ld2r {v0.2d-v1.2d}, \[x0\]
2e0: 4d40ec00 ld3r {v0.2d-v2.2d}, \[x0\]
2e4: 4d60ec00 ld4r {v0.2d-v3.2d}, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/reglist-1.d b/gas/testsuite/gas/aarch64/reglist-1.d
new file mode 100644
index 00000000000..5ab8170a3cc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-1.d
@@ -0,0 +1,21 @@
+#as: -march=armv8-a+sve
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 4c40ac1f ld1 {v31\.2d-v0\.2d}, \[x0\]
+[^:]+: 4c40681f ld1 {v31\.4s-v1\.4s}, \[x0\]
+[^:]+: 4c40241f ld1 {v31\.8h-v2\.8h}, \[x0\]
+[^:]+: 4c40201e ld1 {v30\.16b-v1\.16b}, \[x0\]
+[^:]+: 0c40601e ld1 {v30\.8b-v0\.8b}, \[x0\]
+[^:]+: 0c40241d ld1 {v29\.4h-v0\.4h}, \[x0\]
+[^:]+: a420e01f ld2b {z31\.b-z0\.b}, p0/z, \[x0\]
+[^:]+: a440e01e ld3b {z30\.b-z0\.b}, p0/z, \[x0\]
+[^:]+: a440e01f ld3b {z31\.b-z1\.b}, p0/z, \[x0\]
+[^:]+: a460e01d ld4b {z29\.b-z0\.b}, p0/z, \[x0\]
+[^:]+: a460e01e ld4b {z30\.b-z1\.b}, p0/z, \[x0\]
+[^:]+: a460e01f ld4b {z31\.b-z2\.b}, p0/z, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/reglist-1.s b/gas/testsuite/gas/aarch64/reglist-1.s
new file mode 100644
index 00000000000..631688fb295
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-1.s
@@ -0,0 +1,15 @@
+ ld1 { v31.2d - v0.2d }, [x0]
+ ld1 { v31.4s - v1.4s }, [x0]
+ ld1 { v31.8h - v2.8h }, [x0]
+ ld1 { v30.16b - v1.16b }, [x0]
+ ld1 { v30.8b - v0.8b }, [x0]
+ ld1 { v29.4h - v0.4h }, [x0]
+
+ ld2b { z31.b - z0.b }, p0/z, [x0]
+
+ ld3b { z30.b - z0.b }, p0/z, [x0]
+ ld3b { z31.b - z1.b }, p0/z, [x0]
+
+ ld4b { z29.b - z0.b }, p0/z, [x0]
+ ld4b { z30.b - z1.b }, p0/z, [x0]
+ ld4b { z31.b - z2.b }, p0/z, [x0]
diff --git a/gas/testsuite/gas/aarch64/reglist-2.d b/gas/testsuite/gas/aarch64/reglist-2.d
new file mode 100644
index 00000000000..7bfc14b5d5a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-2.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: reglist-2.s
+#error_output: reglist-2.l
diff --git a/gas/testsuite/gas/aarch64/reglist-2.l b/gas/testsuite/gas/aarch64/reglist-2.l
new file mode 100644
index 00000000000..9d7dfbef13e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-2.l
@@ -0,0 +1,8 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v1\.2d-v0\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v31\.2d-v3\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v30\.2d-v2\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v29\.2d-v1\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v31\.2d-v30\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: invalid range in vector register list at operand 1 -- `ld1 {v0\.2d-v0\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: invalid range in vector register list at operand 1 -- `ld1 {v31\.2d-v31\.2d},\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/reglist-2.s b/gas/testsuite/gas/aarch64/reglist-2.s
new file mode 100644
index 00000000000..91a6cbfe069
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-2.s
@@ -0,0 +1,7 @@
+ ld1 { v1.2d - v0.2d }, [x0]
+ ld1 { v31.2d - v3.2d }, [x0]
+ ld1 { v30.2d - v2.2d }, [x0]
+ ld1 { v29.2d - v1.2d }, [x0]
+ ld1 { v31.2d - v30.2d }, [x0]
+ ld1 { v0.2d - v0.2d }, [x0]
+ ld1 { v31.2d - v31.2d }, [x0]
diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d
index ee5ba485f3c..e3a6aab392c 100644
--- a/gas/testsuite/gas/aarch64/sve.d
+++ b/gas/testsuite/gas/aarch64/sve.d
@@ -17486,359 +17486,359 @@ Disassembly of section .*:
[^:]+: c531c000 ld1w {z0.d}, p0/z, \[z0.d, #68\]
[^:]+: c53fc000 ld1w {z0.d}, p0/z, \[z0.d, #124\]
[^:]+: c53fc000 ld1w {z0.d}, p0/z, \[z0.d, #124\]
-[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c01f ld2b {z31.b, z0.b}, p0/z, \[x0, x0\]
-[^:]+: a420c01f ld2b {z31.b, z0.b}, p0/z, \[x0, x0\]
-[^:]+: a420c01f ld2b {z31.b, z0.b}, p0/z, \[x0, x0\]
-[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a427e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a427e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a427e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a428e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a428e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a428e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a429e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a429e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a429e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a42fe000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a42fe000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a42fe000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a5a0c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c001 ld2d {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c001 ld2d {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c001 ld2d {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c01f ld2d {z31.d, z0.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c01f ld2d {z31.d, z0.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c800 ld2d {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c800 ld2d {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c800 ld2d {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0dc00 ld2d {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0dc00 ld2d {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0dc00 ld2d {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c060 ld2d {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-[^:]+: a5a0c060 ld2d {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-[^:]+: a5a0c060 ld2d {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-[^:]+: a5a0c3e0 ld2d {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-[^:]+: a5a0c3e0 ld2d {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-[^:]+: a5a0c3e0 ld2d {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-[^:]+: a5a4c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-[^:]+: a5a4c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-[^:]+: a5a4c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-[^:]+: a5bec000 ld2d {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-[^:]+: a5bec000 ld2d {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-[^:]+: a5bec000 ld2d {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a7e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a5a7e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a5a7e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a5a8e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a5a8e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a5a8e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a5a9e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a5a9e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a5a9e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a5afe000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a5afe000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a5afe000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a4a0c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c001 ld2h {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c001 ld2h {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c001 ld2h {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c01f ld2h {z31.h, z0.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c01f ld2h {z31.h, z0.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c800 ld2h {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c800 ld2h {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c800 ld2h {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0dc00 ld2h {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0dc00 ld2h {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0dc00 ld2h {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c060 ld2h {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-[^:]+: a4a0c060 ld2h {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-[^:]+: a4a0c060 ld2h {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-[^:]+: a4a0c3e0 ld2h {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-[^:]+: a4a0c3e0 ld2h {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-[^:]+: a4a0c3e0 ld2h {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-[^:]+: a4a4c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-[^:]+: a4a4c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-[^:]+: a4a4c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-[^:]+: a4bec000 ld2h {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-[^:]+: a4bec000 ld2h {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-[^:]+: a4bec000 ld2h {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a7e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a4a7e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a4a7e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a4a8e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a4a8e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a4a8e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a4a9e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a4a9e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a4a9e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a4afe000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a4afe000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a4afe000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a520c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c001 ld2w {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c001 ld2w {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c001 ld2w {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c01f ld2w {z31.s, z0.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c01f ld2w {z31.s, z0.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c800 ld2w {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-[^:]+: a520c800 ld2w {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-[^:]+: a520c800 ld2w {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-[^:]+: a520dc00 ld2w {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-[^:]+: a520dc00 ld2w {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-[^:]+: a520dc00 ld2w {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-[^:]+: a520c060 ld2w {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-[^:]+: a520c060 ld2w {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-[^:]+: a520c060 ld2w {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-[^:]+: a520c3e0 ld2w {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-[^:]+: a520c3e0 ld2w {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-[^:]+: a520c3e0 ld2w {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-[^:]+: a524c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-[^:]+: a524c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-[^:]+: a524c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-[^:]+: a53ec000 ld2w {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-[^:]+: a53ec000 ld2w {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-[^:]+: a53ec000 ld2w {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a527e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a527e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a527e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a528e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a528e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a528e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a529e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a529e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a529e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a52fe000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a52fe000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a52fe000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a420c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001 ld2b {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001 ld2b {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001 ld2b {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001 ld2b {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001 ld2b {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c01f ld2b {z31.b-z0.b}, p0/z, \[x0, x0\]
+[^:]+: a420c01f ld2b {z31.b-z0.b}, p0/z, \[x0, x0\]
+[^:]+: a420c01f ld2b {z31.b-z0.b}, p0/z, \[x0, x0\]
+[^:]+: a420c800 ld2b {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800 ld2b {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800 ld2b {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800 ld2b {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800 ld2b {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420dc00 ld2b {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00 ld2b {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00 ld2b {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00 ld2b {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00 ld2b {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420c060 ld2b {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060 ld2b {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060 ld2b {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060 ld2b {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060 ld2b {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c3e0 ld2b {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0 ld2b {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0 ld2b {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0 ld2b {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0 ld2b {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a424c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000 ld2b {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a43ec000 ld2b {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000 ld2b {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000 ld2b {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000 ld2b {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000 ld2b {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000 ld2b {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001 ld2b {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e01f ld2b {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e01f ld2b {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e01f ld2b {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e01f ld2b {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800 ld2b {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00 ld2b {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060 ld2b {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0 ld2b {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a427e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a427e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a427e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a428e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a428e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a428e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a429e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a429e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a429e000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a42fe000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a42fe000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a42fe000 ld2b {z0.b-z1.b}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a5a0c000 ld2d {z0.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c000 ld2d {z0.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c000 ld2d {z0.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c001 ld2d {z1.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c001 ld2d {z1.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c001 ld2d {z1.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c01f ld2d {z31.d-z0.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c01f ld2d {z31.d-z0.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c800 ld2d {z0.d-z1.d}, p2/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c800 ld2d {z0.d-z1.d}, p2/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c800 ld2d {z0.d-z1.d}, p2/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0dc00 ld2d {z0.d-z1.d}, p7/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0dc00 ld2d {z0.d-z1.d}, p7/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0dc00 ld2d {z0.d-z1.d}, p7/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c060 ld2d {z0.d-z1.d}, p0/z, \[x3, x0, lsl #3\]
+[^:]+: a5a0c060 ld2d {z0.d-z1.d}, p0/z, \[x3, x0, lsl #3\]
+[^:]+: a5a0c060 ld2d {z0.d-z1.d}, p0/z, \[x3, x0, lsl #3\]
+[^:]+: a5a0c3e0 ld2d {z0.d-z1.d}, p0/z, \[sp, x0, lsl #3\]
+[^:]+: a5a0c3e0 ld2d {z0.d-z1.d}, p0/z, \[sp, x0, lsl #3\]
+[^:]+: a5a0c3e0 ld2d {z0.d-z1.d}, p0/z, \[sp, x0, lsl #3\]
+[^:]+: a5a4c000 ld2d {z0.d-z1.d}, p0/z, \[x0, x4, lsl #3\]
+[^:]+: a5a4c000 ld2d {z0.d-z1.d}, p0/z, \[x0, x4, lsl #3\]
+[^:]+: a5a4c000 ld2d {z0.d-z1.d}, p0/z, \[x0, x4, lsl #3\]
+[^:]+: a5bec000 ld2d {z0.d-z1.d}, p0/z, \[x0, x30, lsl #3\]
+[^:]+: a5bec000 ld2d {z0.d-z1.d}, p0/z, \[x0, x30, lsl #3\]
+[^:]+: a5bec000 ld2d {z0.d-z1.d}, p0/z, \[x0, x30, lsl #3\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000 ld2d {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001 ld2d {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f ld2d {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f ld2d {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f ld2d {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f ld2d {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800 ld2d {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00 ld2d {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060 ld2d {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0 ld2d {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a7e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a5a7e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a5a7e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a5a8e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a5a8e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a5a8e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a5a9e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a5a9e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a5a9e000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a5afe000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a5afe000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a5afe000 ld2d {z0.d-z1.d}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a4a0c000 ld2h {z0.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c000 ld2h {z0.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c000 ld2h {z0.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c001 ld2h {z1.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c001 ld2h {z1.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c001 ld2h {z1.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c01f ld2h {z31.h-z0.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c01f ld2h {z31.h-z0.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c800 ld2h {z0.h-z1.h}, p2/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c800 ld2h {z0.h-z1.h}, p2/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c800 ld2h {z0.h-z1.h}, p2/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0dc00 ld2h {z0.h-z1.h}, p7/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0dc00 ld2h {z0.h-z1.h}, p7/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0dc00 ld2h {z0.h-z1.h}, p7/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c060 ld2h {z0.h-z1.h}, p0/z, \[x3, x0, lsl #1\]
+[^:]+: a4a0c060 ld2h {z0.h-z1.h}, p0/z, \[x3, x0, lsl #1\]
+[^:]+: a4a0c060 ld2h {z0.h-z1.h}, p0/z, \[x3, x0, lsl #1\]
+[^:]+: a4a0c3e0 ld2h {z0.h-z1.h}, p0/z, \[sp, x0, lsl #1\]
+[^:]+: a4a0c3e0 ld2h {z0.h-z1.h}, p0/z, \[sp, x0, lsl #1\]
+[^:]+: a4a0c3e0 ld2h {z0.h-z1.h}, p0/z, \[sp, x0, lsl #1\]
+[^:]+: a4a4c000 ld2h {z0.h-z1.h}, p0/z, \[x0, x4, lsl #1\]
+[^:]+: a4a4c000 ld2h {z0.h-z1.h}, p0/z, \[x0, x4, lsl #1\]
+[^:]+: a4a4c000 ld2h {z0.h-z1.h}, p0/z, \[x0, x4, lsl #1\]
+[^:]+: a4bec000 ld2h {z0.h-z1.h}, p0/z, \[x0, x30, lsl #1\]
+[^:]+: a4bec000 ld2h {z0.h-z1.h}, p0/z, \[x0, x30, lsl #1\]
+[^:]+: a4bec000 ld2h {z0.h-z1.h}, p0/z, \[x0, x30, lsl #1\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000 ld2h {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001 ld2h {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f ld2h {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f ld2h {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f ld2h {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f ld2h {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800 ld2h {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00 ld2h {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060 ld2h {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0 ld2h {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a7e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a4a7e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a4a7e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a4a8e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a4a8e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a4a8e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a4a9e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a4a9e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a4a9e000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a4afe000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a4afe000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a4afe000 ld2h {z0.h-z1.h}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a520c000 ld2w {z0.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c000 ld2w {z0.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c000 ld2w {z0.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c001 ld2w {z1.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c001 ld2w {z1.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c001 ld2w {z1.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c01f ld2w {z31.s-z0.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c01f ld2w {z31.s-z0.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c800 ld2w {z0.s-z1.s}, p2/z, \[x0, x0, lsl #2\]
+[^:]+: a520c800 ld2w {z0.s-z1.s}, p2/z, \[x0, x0, lsl #2\]
+[^:]+: a520c800 ld2w {z0.s-z1.s}, p2/z, \[x0, x0, lsl #2\]
+[^:]+: a520dc00 ld2w {z0.s-z1.s}, p7/z, \[x0, x0, lsl #2\]
+[^:]+: a520dc00 ld2w {z0.s-z1.s}, p7/z, \[x0, x0, lsl #2\]
+[^:]+: a520dc00 ld2w {z0.s-z1.s}, p7/z, \[x0, x0, lsl #2\]
+[^:]+: a520c060 ld2w {z0.s-z1.s}, p0/z, \[x3, x0, lsl #2\]
+[^:]+: a520c060 ld2w {z0.s-z1.s}, p0/z, \[x3, x0, lsl #2\]
+[^:]+: a520c060 ld2w {z0.s-z1.s}, p0/z, \[x3, x0, lsl #2\]
+[^:]+: a520c3e0 ld2w {z0.s-z1.s}, p0/z, \[sp, x0, lsl #2\]
+[^:]+: a520c3e0 ld2w {z0.s-z1.s}, p0/z, \[sp, x0, lsl #2\]
+[^:]+: a520c3e0 ld2w {z0.s-z1.s}, p0/z, \[sp, x0, lsl #2\]
+[^:]+: a524c000 ld2w {z0.s-z1.s}, p0/z, \[x0, x4, lsl #2\]
+[^:]+: a524c000 ld2w {z0.s-z1.s}, p0/z, \[x0, x4, lsl #2\]
+[^:]+: a524c000 ld2w {z0.s-z1.s}, p0/z, \[x0, x4, lsl #2\]
+[^:]+: a53ec000 ld2w {z0.s-z1.s}, p0/z, \[x0, x30, lsl #2\]
+[^:]+: a53ec000 ld2w {z0.s-z1.s}, p0/z, \[x0, x30, lsl #2\]
+[^:]+: a53ec000 ld2w {z0.s-z1.s}, p0/z, \[x0, x30, lsl #2\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000 ld2w {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001 ld2w {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e01f ld2w {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e01f ld2w {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e01f ld2w {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e01f ld2w {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800 ld2w {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00 ld2w {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060 ld2w {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0 ld2w {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a527e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a527e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a527e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a528e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a528e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a528e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a529e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a529e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a529e000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a52fe000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a52fe000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a52fe000 ld2w {z0.s-z1.s}, p0/z, \[x0, #-2, mul vl\]
[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
@@ -17849,9 +17849,9 @@ Disassembly of section .*:
[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
-[^:]+: a440c01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a440c01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a440c01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
+[^:]+: a440c01f ld3b {z31.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a440c01f ld3b {z31.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a440c01f ld3b {z31.b-z1.b}, p0/z, \[x0, x0\]
[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
@@ -17896,10 +17896,10 @@ Disassembly of section .*:
[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f ld3b {z31.b-z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f ld3b {z31.b-z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f ld3b {z31.b-z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f ld3b {z31.b-z1.b}, p0/z, \[x0\]
[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
@@ -17946,8 +17946,8 @@ Disassembly of section .*:
[^:]+: a5c0c001 ld3d {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
[^:]+: a5c0c001 ld3d {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
[^:]+: a5c0c001 ld3d {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5c0c01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5c0c01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5c0c01f ld3d {z31.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5c0c01f ld3d {z31.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
[^:]+: a5c0c800 ld3d {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
[^:]+: a5c0c800 ld3d {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
[^:]+: a5c0c800 ld3d {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
@@ -17980,10 +17980,10 @@ Disassembly of section .*:
[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f ld3d {z31.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f ld3d {z31.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f ld3d {z31.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f ld3d {z31.d-z1.d}, p0/z, \[x0\]
[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
@@ -18030,8 +18030,8 @@ Disassembly of section .*:
[^:]+: a4c0c001 ld3h {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
[^:]+: a4c0c001 ld3h {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
[^:]+: a4c0c001 ld3h {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4c0c01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4c0c01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4c0c01f ld3h {z31.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4c0c01f ld3h {z31.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
[^:]+: a4c0c800 ld3h {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
[^:]+: a4c0c800 ld3h {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
[^:]+: a4c0c800 ld3h {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
@@ -18064,10 +18064,10 @@ Disassembly of section .*:
[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f ld3h {z31.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f ld3h {z31.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f ld3h {z31.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f ld3h {z31.h-z1.h}, p0/z, \[x0\]
[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
@@ -18114,8 +18114,8 @@ Disassembly of section .*:
[^:]+: a540c001 ld3w {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
[^:]+: a540c001 ld3w {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
[^:]+: a540c001 ld3w {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a540c01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a540c01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a540c01f ld3w {z31.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a540c01f ld3w {z31.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
[^:]+: a540c800 ld3w {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
[^:]+: a540c800 ld3w {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
[^:]+: a540c800 ld3w {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
@@ -18148,10 +18148,10 @@ Disassembly of section .*:
[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f ld3w {z31.s-z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f ld3w {z31.s-z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f ld3w {z31.s-z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f ld3w {z31.s-z1.s}, p0/z, \[x0\]
[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
@@ -18202,9 +18202,9 @@ Disassembly of section .*:
[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
-[^:]+: a460c01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a460c01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a460c01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
+[^:]+: a460c01f ld4b {z31.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a460c01f ld4b {z31.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a460c01f ld4b {z31.b-z2.b}, p0/z, \[x0, x0\]
[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
@@ -18249,10 +18249,10 @@ Disassembly of section .*:
[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f ld4b {z31.b-z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f ld4b {z31.b-z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f ld4b {z31.b-z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f ld4b {z31.b-z2.b}, p0/z, \[x0\]
[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
@@ -18299,8 +18299,8 @@ Disassembly of section .*:
[^:]+: a5e0c001 ld4d {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
[^:]+: a5e0c001 ld4d {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
[^:]+: a5e0c001 ld4d {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5e0c01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5e0c01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5e0c01f ld4d {z31.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5e0c01f ld4d {z31.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
[^:]+: a5e0c800 ld4d {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
[^:]+: a5e0c800 ld4d {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
[^:]+: a5e0c800 ld4d {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
@@ -18333,10 +18333,10 @@ Disassembly of section .*:
[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f ld4d {z31.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f ld4d {z31.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f ld4d {z31.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f ld4d {z31.d-z2.d}, p0/z, \[x0\]
[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
@@ -18383,8 +18383,8 @@ Disassembly of section .*:
[^:]+: a4e0c001 ld4h {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
[^:]+: a4e0c001 ld4h {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
[^:]+: a4e0c001 ld4h {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4e0c01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4e0c01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4e0c01f ld4h {z31.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4e0c01f ld4h {z31.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
[^:]+: a4e0c800 ld4h {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
[^:]+: a4e0c800 ld4h {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
[^:]+: a4e0c800 ld4h {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
@@ -18417,10 +18417,10 @@ Disassembly of section .*:
[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f ld4h {z31.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f ld4h {z31.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f ld4h {z31.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f ld4h {z31.h-z2.h}, p0/z, \[x0\]
[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
@@ -18467,8 +18467,8 @@ Disassembly of section .*:
[^:]+: a560c001 ld4w {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
[^:]+: a560c001 ld4w {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
[^:]+: a560c001 ld4w {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a560c01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a560c01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a560c01f ld4w {z31.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a560c01f ld4w {z31.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
[^:]+: a560c800 ld4w {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
[^:]+: a560c800 ld4w {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
[^:]+: a560c800 ld4w {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
@@ -18501,10 +18501,10 @@ Disassembly of section .*:
[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f ld4w {z31.s-z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f ld4w {z31.s-z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f ld4w {z31.s-z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f ld4w {z31.s-z2.s}, p0/z, \[x0\]
[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
@@ -32604,359 +32604,359 @@ Disassembly of section .*:
[^:]+: e569e000 st1w {z0.d}, p0, \[x0, #-7, mul vl\]
[^:]+: e56fe000 st1w {z0.d}, p0, \[x0, #-1, mul vl\]
[^:]+: e56fe000 st1w {z0.d}, p0, \[x0, #-1, mul vl\]
-[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e420601f st2b {z31.b, z0.b}, p0, \[x0, x0\]
-[^:]+: e420601f st2b {z31.b, z0.b}, p0, \[x0, x0\]
-[^:]+: e420601f st2b {z31.b, z0.b}, p0, \[x0, x0\]
-[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e01f st2b {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e01f st2b {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e01f st2b {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e01f st2b {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e437e000 st2b {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-[^:]+: e437e000 st2b {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-[^:]+: e437e000 st2b {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-[^:]+: e438e000 st2b {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-[^:]+: e438e000 st2b {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-[^:]+: e438e000 st2b {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-[^:]+: e439e000 st2b {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-[^:]+: e439e000 st2b {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-[^:]+: e439e000 st2b {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-[^:]+: e43fe000 st2b {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-[^:]+: e43fe000 st2b {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-[^:]+: e43fe000 st2b {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5a06000 st2d {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06000 st2d {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06000 st2d {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06001 st2d {z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06001 st2d {z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06001 st2d {z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a0601f st2d {z31.d, z0.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a0601f st2d {z31.d, z0.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06800 st2d {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-[^:]+: e5a06800 st2d {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-[^:]+: e5a06800 st2d {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-[^:]+: e5a07c00 st2d {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-[^:]+: e5a07c00 st2d {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-[^:]+: e5a07c00 st2d {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-[^:]+: e5a06060 st2d {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-[^:]+: e5a06060 st2d {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-[^:]+: e5a06060 st2d {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-[^:]+: e5a063e0 st2d {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-[^:]+: e5a063e0 st2d {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-[^:]+: e5a063e0 st2d {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-[^:]+: e5a46000 st2d {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-[^:]+: e5a46000 st2d {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-[^:]+: e5a46000 st2d {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-[^:]+: e5be6000 st2d {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-[^:]+: e5be6000 st2d {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-[^:]+: e5be6000 st2d {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e01f st2d {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e01f st2d {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e01f st2d {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e01f st2d {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b7e000 st2d {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-[^:]+: e5b7e000 st2d {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-[^:]+: e5b7e000 st2d {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-[^:]+: e5b8e000 st2d {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-[^:]+: e5b8e000 st2d {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-[^:]+: e5b8e000 st2d {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-[^:]+: e5b9e000 st2d {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-[^:]+: e5b9e000 st2d {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-[^:]+: e5b9e000 st2d {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-[^:]+: e5bfe000 st2d {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5bfe000 st2d {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5bfe000 st2d {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-[^:]+: e4a06000 st2h {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06000 st2h {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06000 st2h {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06001 st2h {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06001 st2h {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06001 st2h {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a0601f st2h {z31.h, z0.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a0601f st2h {z31.h, z0.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06800 st2h {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-[^:]+: e4a06800 st2h {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-[^:]+: e4a06800 st2h {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-[^:]+: e4a07c00 st2h {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-[^:]+: e4a07c00 st2h {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-[^:]+: e4a07c00 st2h {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-[^:]+: e4a06060 st2h {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-[^:]+: e4a06060 st2h {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-[^:]+: e4a06060 st2h {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-[^:]+: e4a063e0 st2h {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-[^:]+: e4a063e0 st2h {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-[^:]+: e4a063e0 st2h {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-[^:]+: e4a46000 st2h {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-[^:]+: e4a46000 st2h {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-[^:]+: e4a46000 st2h {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-[^:]+: e4be6000 st2h {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-[^:]+: e4be6000 st2h {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-[^:]+: e4be6000 st2h {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000 st2h {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001 st2h {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e01f st2h {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e01f st2h {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e01f st2h {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e01f st2h {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800 st2h {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060 st2h {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0 st2h {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b7e000 st2h {z0.h, z1.h}, p0, \[x0, #14, mul vl\]
-[^:]+: e4b7e000 st2h {z0.h, z1.h}, p0, \[x0, #14, mul vl\]
-[^:]+: e4b7e000 st2h {z0.h, z1.h}, p0, \[x0, #14, mul vl\]
-[^:]+: e4b8e000 st2h {z0.h, z1.h}, p0, \[x0, #-16, mul vl\]
-[^:]+: e4b8e000 st2h {z0.h, z1.h}, p0, \[x0, #-16, mul vl\]
-[^:]+: e4b8e000 st2h {z0.h, z1.h}, p0, \[x0, #-16, mul vl\]
-[^:]+: e4b9e000 st2h {z0.h, z1.h}, p0, \[x0, #-14, mul vl\]
-[^:]+: e4b9e000 st2h {z0.h, z1.h}, p0, \[x0, #-14, mul vl\]
-[^:]+: e4b9e000 st2h {z0.h, z1.h}, p0, \[x0, #-14, mul vl\]
-[^:]+: e4bfe000 st2h {z0.h, z1.h}, p0, \[x0, #-2, mul vl\]
-[^:]+: e4bfe000 st2h {z0.h, z1.h}, p0, \[x0, #-2, mul vl\]
-[^:]+: e4bfe000 st2h {z0.h, z1.h}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5206000 st2w {z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e5206000 st2w {z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e5206000 st2w {z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e5206001 st2w {z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e5206001 st2w {z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e5206001 st2w {z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e520601f st2w {z31.s, z0.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e520601f st2w {z31.s, z0.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e5206800 st2w {z0.s, z1.s}, p2, \[x0, x0, lsl #2\]
-[^:]+: e5206800 st2w {z0.s, z1.s}, p2, \[x0, x0, lsl #2\]
-[^:]+: e5206800 st2w {z0.s, z1.s}, p2, \[x0, x0, lsl #2\]
-[^:]+: e5207c00 st2w {z0.s, z1.s}, p7, \[x0, x0, lsl #2\]
-[^:]+: e5207c00 st2w {z0.s, z1.s}, p7, \[x0, x0, lsl #2\]
-[^:]+: e5207c00 st2w {z0.s, z1.s}, p7, \[x0, x0, lsl #2\]
-[^:]+: e5206060 st2w {z0.s, z1.s}, p0, \[x3, x0, lsl #2\]
-[^:]+: e5206060 st2w {z0.s, z1.s}, p0, \[x3, x0, lsl #2\]
-[^:]+: e5206060 st2w {z0.s, z1.s}, p0, \[x3, x0, lsl #2\]
-[^:]+: e52063e0 st2w {z0.s, z1.s}, p0, \[sp, x0, lsl #2\]
-[^:]+: e52063e0 st2w {z0.s, z1.s}, p0, \[sp, x0, lsl #2\]
-[^:]+: e52063e0 st2w {z0.s, z1.s}, p0, \[sp, x0, lsl #2\]
-[^:]+: e5246000 st2w {z0.s, z1.s}, p0, \[x0, x4, lsl #2\]
-[^:]+: e5246000 st2w {z0.s, z1.s}, p0, \[x0, x4, lsl #2\]
-[^:]+: e5246000 st2w {z0.s, z1.s}, p0, \[x0, x4, lsl #2\]
-[^:]+: e53e6000 st2w {z0.s, z1.s}, p0, \[x0, x30, lsl #2\]
-[^:]+: e53e6000 st2w {z0.s, z1.s}, p0, \[x0, x30, lsl #2\]
-[^:]+: e53e6000 st2w {z0.s, z1.s}, p0, \[x0, x30, lsl #2\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e000 st2w {z0.s, z1.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
-[^:]+: e530e001 st2w {z1.s, z2.s}, p0, \[x0\]
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-[^:]+: e530e01f st2w {z31.s, z0.s}, p0, \[x0\]
-[^:]+: e530e01f st2w {z31.s, z0.s}, p0, \[x0\]
-[^:]+: e530e01f st2w {z31.s, z0.s}, p0, \[x0\]
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-[^:]+: e530e800 st2w {z0.s, z1.s}, p2, \[x0\]
-[^:]+: e530e800 st2w {z0.s, z1.s}, p2, \[x0\]
-[^:]+: e530e800 st2w {z0.s, z1.s}, p2, \[x0\]
-[^:]+: e530e800 st2w {z0.s, z1.s}, p2, \[x0\]
-[^:]+: e530e800 st2w {z0.s, z1.s}, p2, \[x0\]
-[^:]+: e530e800 st2w {z0.s, z1.s}, p2, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530fc00 st2w {z0.s, z1.s}, p7, \[x0\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e060 st2w {z0.s, z1.s}, p0, \[x3\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e530e3e0 st2w {z0.s, z1.s}, p0, \[sp\]
-[^:]+: e537e000 st2w {z0.s, z1.s}, p0, \[x0, #14, mul vl\]
-[^:]+: e537e000 st2w {z0.s, z1.s}, p0, \[x0, #14, mul vl\]
-[^:]+: e537e000 st2w {z0.s, z1.s}, p0, \[x0, #14, mul vl\]
-[^:]+: e538e000 st2w {z0.s, z1.s}, p0, \[x0, #-16, mul vl\]
-[^:]+: e538e000 st2w {z0.s, z1.s}, p0, \[x0, #-16, mul vl\]
-[^:]+: e538e000 st2w {z0.s, z1.s}, p0, \[x0, #-16, mul vl\]
-[^:]+: e539e000 st2w {z0.s, z1.s}, p0, \[x0, #-14, mul vl\]
-[^:]+: e539e000 st2w {z0.s, z1.s}, p0, \[x0, #-14, mul vl\]
-[^:]+: e539e000 st2w {z0.s, z1.s}, p0, \[x0, #-14, mul vl\]
-[^:]+: e53fe000 st2w {z0.s, z1.s}, p0, \[x0, #-2, mul vl\]
-[^:]+: e53fe000 st2w {z0.s, z1.s}, p0, \[x0, #-2, mul vl\]
-[^:]+: e53fe000 st2w {z0.s, z1.s}, p0, \[x0, #-2, mul vl\]
+[^:]+: e4206000 st2b {z0.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e4206000 st2b {z0.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e4206000 st2b {z0.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e4206000 st2b {z0.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e4206000 st2b {z0.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e4206001 st2b {z1.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e4206001 st2b {z1.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e4206001 st2b {z1.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e4206001 st2b {z1.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e4206001 st2b {z1.b-z2.b}, p0, \[x0, x0\]
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+[^:]+: e420601f st2b {z31.b-z0.b}, p0, \[x0, x0\]
+[^:]+: e420601f st2b {z31.b-z0.b}, p0, \[x0, x0\]
+[^:]+: e4206800 st2b {z0.b-z1.b}, p2, \[x0, x0\]
+[^:]+: e4206800 st2b {z0.b-z1.b}, p2, \[x0, x0\]
+[^:]+: e4206800 st2b {z0.b-z1.b}, p2, \[x0, x0\]
+[^:]+: e4206800 st2b {z0.b-z1.b}, p2, \[x0, x0\]
+[^:]+: e4206800 st2b {z0.b-z1.b}, p2, \[x0, x0\]
+[^:]+: e4207c00 st2b {z0.b-z1.b}, p7, \[x0, x0\]
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+[^:]+: e4207c00 st2b {z0.b-z1.b}, p7, \[x0, x0\]
+[^:]+: e4206060 st2b {z0.b-z1.b}, p0, \[x3, x0\]
+[^:]+: e4206060 st2b {z0.b-z1.b}, p0, \[x3, x0\]
+[^:]+: e4206060 st2b {z0.b-z1.b}, p0, \[x3, x0\]
+[^:]+: e4206060 st2b {z0.b-z1.b}, p0, \[x3, x0\]
+[^:]+: e4206060 st2b {z0.b-z1.b}, p0, \[x3, x0\]
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+[^:]+: e42063e0 st2b {z0.b-z1.b}, p0, \[sp, x0\]
+[^:]+: e42063e0 st2b {z0.b-z1.b}, p0, \[sp, x0\]
+[^:]+: e42063e0 st2b {z0.b-z1.b}, p0, \[sp, x0\]
+[^:]+: e42063e0 st2b {z0.b-z1.b}, p0, \[sp, x0\]
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+[^:]+: e4246000 st2b {z0.b-z1.b}, p0, \[x0, x4\]
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+[^:]+: e530e060 st2w {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060 st2w {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060 st2w {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060 st2w {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0 st2w {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e537e000 st2w {z0.s-z1.s}, p0, \[x0, #14, mul vl\]
+[^:]+: e537e000 st2w {z0.s-z1.s}, p0, \[x0, #14, mul vl\]
+[^:]+: e537e000 st2w {z0.s-z1.s}, p0, \[x0, #14, mul vl\]
+[^:]+: e538e000 st2w {z0.s-z1.s}, p0, \[x0, #-16, mul vl\]
+[^:]+: e538e000 st2w {z0.s-z1.s}, p0, \[x0, #-16, mul vl\]
+[^:]+: e538e000 st2w {z0.s-z1.s}, p0, \[x0, #-16, mul vl\]
+[^:]+: e539e000 st2w {z0.s-z1.s}, p0, \[x0, #-14, mul vl\]
+[^:]+: e539e000 st2w {z0.s-z1.s}, p0, \[x0, #-14, mul vl\]
+[^:]+: e539e000 st2w {z0.s-z1.s}, p0, \[x0, #-14, mul vl\]
+[^:]+: e53fe000 st2w {z0.s-z1.s}, p0, \[x0, #-2, mul vl\]
+[^:]+: e53fe000 st2w {z0.s-z1.s}, p0, \[x0, #-2, mul vl\]
+[^:]+: e53fe000 st2w {z0.s-z1.s}, p0, \[x0, #-2, mul vl\]
[^:]+: e4406000 st3b {z0.b-z2.b}, p0, \[x0, x0\]
[^:]+: e4406000 st3b {z0.b-z2.b}, p0, \[x0, x0\]
[^:]+: e4406000 st3b {z0.b-z2.b}, p0, \[x0, x0\]
@@ -32967,9 +32967,9 @@ Disassembly of section .*:
[^:]+: e4406001 st3b {z1.b-z3.b}, p0, \[x0, x0\]
[^:]+: e4406001 st3b {z1.b-z3.b}, p0, \[x0, x0\]
[^:]+: e4406001 st3b {z1.b-z3.b}, p0, \[x0, x0\]
-[^:]+: e440601f st3b {z31.b, z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e440601f st3b {z31.b, z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e440601f st3b {z31.b, z0.b, z1.b}, p0, \[x0, x0\]
+[^:]+: e440601f st3b {z31.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e440601f st3b {z31.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e440601f st3b {z31.b-z1.b}, p0, \[x0, x0\]
[^:]+: e4406800 st3b {z0.b-z2.b}, p2, \[x0, x0\]
[^:]+: e4406800 st3b {z0.b-z2.b}, p2, \[x0, x0\]
[^:]+: e4406800 st3b {z0.b-z2.b}, p2, \[x0, x0\]
@@ -33014,10 +33014,10 @@ Disassembly of section .*:
[^:]+: e450e001 st3b {z1.b-z3.b}, p0, \[x0\]
[^:]+: e450e001 st3b {z1.b-z3.b}, p0, \[x0\]
[^:]+: e450e001 st3b {z1.b-z3.b}, p0, \[x0\]
-[^:]+: e450e01f st3b {z31.b, z0.b, z1.b}, p0, \[x0\]
-[^:]+: e450e01f st3b {z31.b, z0.b, z1.b}, p0, \[x0\]
-[^:]+: e450e01f st3b {z31.b, z0.b, z1.b}, p0, \[x0\]
-[^:]+: e450e01f st3b {z31.b, z0.b, z1.b}, p0, \[x0\]
+[^:]+: e450e01f st3b {z31.b-z1.b}, p0, \[x0\]
+[^:]+: e450e01f st3b {z31.b-z1.b}, p0, \[x0\]
+[^:]+: e450e01f st3b {z31.b-z1.b}, p0, \[x0\]
+[^:]+: e450e01f st3b {z31.b-z1.b}, p0, \[x0\]
[^:]+: e450e800 st3b {z0.b-z2.b}, p2, \[x0\]
[^:]+: e450e800 st3b {z0.b-z2.b}, p2, \[x0\]
[^:]+: e450e800 st3b {z0.b-z2.b}, p2, \[x0\]
@@ -33064,8 +33064,8 @@ Disassembly of section .*:
[^:]+: e5c06001 st3d {z1.d-z3.d}, p0, \[x0, x0, lsl #3\]
[^:]+: e5c06001 st3d {z1.d-z3.d}, p0, \[x0, x0, lsl #3\]
[^:]+: e5c06001 st3d {z1.d-z3.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5c0601f st3d {z31.d, z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5c0601f st3d {z31.d, z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5c0601f st3d {z31.d-z1.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5c0601f st3d {z31.d-z1.d}, p0, \[x0, x0, lsl #3\]
[^:]+: e5c06800 st3d {z0.d-z2.d}, p2, \[x0, x0, lsl #3\]
[^:]+: e5c06800 st3d {z0.d-z2.d}, p2, \[x0, x0, lsl #3\]
[^:]+: e5c06800 st3d {z0.d-z2.d}, p2, \[x0, x0, lsl #3\]
@@ -33098,10 +33098,10 @@ Disassembly of section .*:
[^:]+: e5d0e001 st3d {z1.d-z3.d}, p0, \[x0\]
[^:]+: e5d0e001 st3d {z1.d-z3.d}, p0, \[x0\]
[^:]+: e5d0e001 st3d {z1.d-z3.d}, p0, \[x0\]
-[^:]+: e5d0e01f st3d {z31.d, z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5d0e01f st3d {z31.d, z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5d0e01f st3d {z31.d, z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5d0e01f st3d {z31.d, z0.d, z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f st3d {z31.d-z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f st3d {z31.d-z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f st3d {z31.d-z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f st3d {z31.d-z1.d}, p0, \[x0\]
[^:]+: e5d0e800 st3d {z0.d-z2.d}, p2, \[x0\]
[^:]+: e5d0e800 st3d {z0.d-z2.d}, p2, \[x0\]
[^:]+: e5d0e800 st3d {z0.d-z2.d}, p2, \[x0\]
@@ -33148,8 +33148,8 @@ Disassembly of section .*:
[^:]+: e4c06001 st3h {z1.h-z3.h}, p0, \[x0, x0, lsl #1\]
[^:]+: e4c06001 st3h {z1.h-z3.h}, p0, \[x0, x0, lsl #1\]
[^:]+: e4c06001 st3h {z1.h-z3.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4c0601f st3h {z31.h, z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4c0601f st3h {z31.h, z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4c0601f st3h {z31.h-z1.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4c0601f st3h {z31.h-z1.h}, p0, \[x0, x0, lsl #1\]
[^:]+: e4c06800 st3h {z0.h-z2.h}, p2, \[x0, x0, lsl #1\]
[^:]+: e4c06800 st3h {z0.h-z2.h}, p2, \[x0, x0, lsl #1\]
[^:]+: e4c06800 st3h {z0.h-z2.h}, p2, \[x0, x0, lsl #1\]
@@ -33182,10 +33182,10 @@ Disassembly of section .*:
[^:]+: e4d0e001 st3h {z1.h-z3.h}, p0, \[x0\]
[^:]+: e4d0e001 st3h {z1.h-z3.h}, p0, \[x0\]
[^:]+: e4d0e001 st3h {z1.h-z3.h}, p0, \[x0\]
-[^:]+: e4d0e01f st3h {z31.h, z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4d0e01f st3h {z31.h, z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4d0e01f st3h {z31.h, z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4d0e01f st3h {z31.h, z0.h, z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f st3h {z31.h-z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f st3h {z31.h-z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f st3h {z31.h-z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f st3h {z31.h-z1.h}, p0, \[x0\]
[^:]+: e4d0e800 st3h {z0.h-z2.h}, p2, \[x0\]
[^:]+: e4d0e800 st3h {z0.h-z2.h}, p2, \[x0\]
[^:]+: e4d0e800 st3h {z0.h-z2.h}, p2, \[x0\]
@@ -33232,8 +33232,8 @@ Disassembly of section .*:
[^:]+: e5406001 st3w {z1.s-z3.s}, p0, \[x0, x0, lsl #2\]
[^:]+: e5406001 st3w {z1.s-z3.s}, p0, \[x0, x0, lsl #2\]
[^:]+: e5406001 st3w {z1.s-z3.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e540601f st3w {z31.s, z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e540601f st3w {z31.s, z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e540601f st3w {z31.s-z1.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e540601f st3w {z31.s-z1.s}, p0, \[x0, x0, lsl #2\]
[^:]+: e5406800 st3w {z0.s-z2.s}, p2, \[x0, x0, lsl #2\]
[^:]+: e5406800 st3w {z0.s-z2.s}, p2, \[x0, x0, lsl #2\]
[^:]+: e5406800 st3w {z0.s-z2.s}, p2, \[x0, x0, lsl #2\]
@@ -33266,10 +33266,10 @@ Disassembly of section .*:
[^:]+: e550e001 st3w {z1.s-z3.s}, p0, \[x0\]
[^:]+: e550e001 st3w {z1.s-z3.s}, p0, \[x0\]
[^:]+: e550e001 st3w {z1.s-z3.s}, p0, \[x0\]
-[^:]+: e550e01f st3w {z31.s, z0.s, z1.s}, p0, \[x0\]
-[^:]+: e550e01f st3w {z31.s, z0.s, z1.s}, p0, \[x0\]
-[^:]+: e550e01f st3w {z31.s, z0.s, z1.s}, p0, \[x0\]
-[^:]+: e550e01f st3w {z31.s, z0.s, z1.s}, p0, \[x0\]
+[^:]+: e550e01f st3w {z31.s-z1.s}, p0, \[x0\]
+[^:]+: e550e01f st3w {z31.s-z1.s}, p0, \[x0\]
+[^:]+: e550e01f st3w {z31.s-z1.s}, p0, \[x0\]
+[^:]+: e550e01f st3w {z31.s-z1.s}, p0, \[x0\]
[^:]+: e550e800 st3w {z0.s-z2.s}, p2, \[x0\]
[^:]+: e550e800 st3w {z0.s-z2.s}, p2, \[x0\]
[^:]+: e550e800 st3w {z0.s-z2.s}, p2, \[x0\]
@@ -33320,9 +33320,9 @@ Disassembly of section .*:
[^:]+: e4606001 st4b {z1.b-z4.b}, p0, \[x0, x0\]
[^:]+: e4606001 st4b {z1.b-z4.b}, p0, \[x0, x0\]
[^:]+: e4606001 st4b {z1.b-z4.b}, p0, \[x0, x0\]
-[^:]+: e460601f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e460601f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e460601f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0, x0\]
+[^:]+: e460601f st4b {z31.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e460601f st4b {z31.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e460601f st4b {z31.b-z2.b}, p0, \[x0, x0\]
[^:]+: e4606800 st4b {z0.b-z3.b}, p2, \[x0, x0\]
[^:]+: e4606800 st4b {z0.b-z3.b}, p2, \[x0, x0\]
[^:]+: e4606800 st4b {z0.b-z3.b}, p2, \[x0, x0\]
@@ -33367,10 +33367,10 @@ Disassembly of section .*:
[^:]+: e470e001 st4b {z1.b-z4.b}, p0, \[x0\]
[^:]+: e470e001 st4b {z1.b-z4.b}, p0, \[x0\]
[^:]+: e470e001 st4b {z1.b-z4.b}, p0, \[x0\]
-[^:]+: e470e01f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
-[^:]+: e470e01f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
-[^:]+: e470e01f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
-[^:]+: e470e01f st4b {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
+[^:]+: e470e01f st4b {z31.b-z2.b}, p0, \[x0\]
+[^:]+: e470e01f st4b {z31.b-z2.b}, p0, \[x0\]
+[^:]+: e470e01f st4b {z31.b-z2.b}, p0, \[x0\]
+[^:]+: e470e01f st4b {z31.b-z2.b}, p0, \[x0\]
[^:]+: e470e800 st4b {z0.b-z3.b}, p2, \[x0\]
[^:]+: e470e800 st4b {z0.b-z3.b}, p2, \[x0\]
[^:]+: e470e800 st4b {z0.b-z3.b}, p2, \[x0\]
@@ -33417,8 +33417,8 @@ Disassembly of section .*:
[^:]+: e5e06001 st4d {z1.d-z4.d}, p0, \[x0, x0, lsl #3\]
[^:]+: e5e06001 st4d {z1.d-z4.d}, p0, \[x0, x0, lsl #3\]
[^:]+: e5e06001 st4d {z1.d-z4.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5e0601f st4d {z31.d, z0.d, z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5e0601f st4d {z31.d, z0.d, z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5e0601f st4d {z31.d-z2.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5e0601f st4d {z31.d-z2.d}, p0, \[x0, x0, lsl #3\]
[^:]+: e5e06800 st4d {z0.d-z3.d}, p2, \[x0, x0, lsl #3\]
[^:]+: e5e06800 st4d {z0.d-z3.d}, p2, \[x0, x0, lsl #3\]
[^:]+: e5e06800 st4d {z0.d-z3.d}, p2, \[x0, x0, lsl #3\]
@@ -33451,10 +33451,10 @@ Disassembly of section .*:
[^:]+: e5f0e001 st4d {z1.d-z4.d}, p0, \[x0\]
[^:]+: e5f0e001 st4d {z1.d-z4.d}, p0, \[x0\]
[^:]+: e5f0e001 st4d {z1.d-z4.d}, p0, \[x0\]
-[^:]+: e5f0e01f st4d {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5f0e01f st4d {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5f0e01f st4d {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5f0e01f st4d {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f st4d {z31.d-z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f st4d {z31.d-z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f st4d {z31.d-z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f st4d {z31.d-z2.d}, p0, \[x0\]
[^:]+: e5f0e800 st4d {z0.d-z3.d}, p2, \[x0\]
[^:]+: e5f0e800 st4d {z0.d-z3.d}, p2, \[x0\]
[^:]+: e5f0e800 st4d {z0.d-z3.d}, p2, \[x0\]
@@ -33501,8 +33501,8 @@ Disassembly of section .*:
[^:]+: e4e06001 st4h {z1.h-z4.h}, p0, \[x0, x0, lsl #1\]
[^:]+: e4e06001 st4h {z1.h-z4.h}, p0, \[x0, x0, lsl #1\]
[^:]+: e4e06001 st4h {z1.h-z4.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4e0601f st4h {z31.h, z0.h, z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4e0601f st4h {z31.h, z0.h, z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4e0601f st4h {z31.h-z2.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4e0601f st4h {z31.h-z2.h}, p0, \[x0, x0, lsl #1\]
[^:]+: e4e06800 st4h {z0.h-z3.h}, p2, \[x0, x0, lsl #1\]
[^:]+: e4e06800 st4h {z0.h-z3.h}, p2, \[x0, x0, lsl #1\]
[^:]+: e4e06800 st4h {z0.h-z3.h}, p2, \[x0, x0, lsl #1\]
@@ -33535,10 +33535,10 @@ Disassembly of section .*:
[^:]+: e4f0e001 st4h {z1.h-z4.h}, p0, \[x0\]
[^:]+: e4f0e001 st4h {z1.h-z4.h}, p0, \[x0\]
[^:]+: e4f0e001 st4h {z1.h-z4.h}, p0, \[x0\]
-[^:]+: e4f0e01f st4h {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4f0e01f st4h {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4f0e01f st4h {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4f0e01f st4h {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f st4h {z31.h-z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f st4h {z31.h-z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f st4h {z31.h-z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f st4h {z31.h-z2.h}, p0, \[x0\]
[^:]+: e4f0e800 st4h {z0.h-z3.h}, p2, \[x0\]
[^:]+: e4f0e800 st4h {z0.h-z3.h}, p2, \[x0\]
[^:]+: e4f0e800 st4h {z0.h-z3.h}, p2, \[x0\]
@@ -33585,8 +33585,8 @@ Disassembly of section .*:
[^:]+: e5606001 st4w {z1.s-z4.s}, p0, \[x0, x0, lsl #2\]
[^:]+: e5606001 st4w {z1.s-z4.s}, p0, \[x0, x0, lsl #2\]
[^:]+: e5606001 st4w {z1.s-z4.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e560601f st4w {z31.s, z0.s, z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e560601f st4w {z31.s, z0.s, z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e560601f st4w {z31.s-z2.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e560601f st4w {z31.s-z2.s}, p0, \[x0, x0, lsl #2\]
[^:]+: e5606800 st4w {z0.s-z3.s}, p2, \[x0, x0, lsl #2\]
[^:]+: e5606800 st4w {z0.s-z3.s}, p2, \[x0, x0, lsl #2\]
[^:]+: e5606800 st4w {z0.s-z3.s}, p2, \[x0, x0, lsl #2\]
@@ -33619,10 +33619,10 @@ Disassembly of section .*:
[^:]+: e570e001 st4w {z1.s-z4.s}, p0, \[x0\]
[^:]+: e570e001 st4w {z1.s-z4.s}, p0, \[x0\]
[^:]+: e570e001 st4w {z1.s-z4.s}, p0, \[x0\]
-[^:]+: e570e01f st4w {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
-[^:]+: e570e01f st4w {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
-[^:]+: e570e01f st4w {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
-[^:]+: e570e01f st4w {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
+[^:]+: e570e01f st4w {z31.s-z2.s}, p0, \[x0\]
+[^:]+: e570e01f st4w {z31.s-z2.s}, p0, \[x0\]
+[^:]+: e570e01f st4w {z31.s-z2.s}, p0, \[x0\]
+[^:]+: e570e01f st4w {z31.s-z2.s}, p0, \[x0\]
[^:]+: e570e800 st4w {z0.s-z3.s}, p2, \[x0\]
[^:]+: e570e800 st4w {z0.s-z3.s}, p2, \[x0\]
[^:]+: e570e800 st4w {z0.s-z3.s}, p2, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/sve2.d b/gas/testsuite/gas/aarch64/sve2.d
index beb76b5ffef..6c0d94203cb 100644
--- a/gas/testsuite/gas/aarch64/sve2.d
+++ b/gas/testsuite/gas/aarch64/sve2.d
@@ -113,9 +113,9 @@ Disassembly of section \.text:
*[0-9a-f]+: 45409400 eortb z0\.h, z0\.h, z0\.h
*[0-9a-f]+: 45809400 eortb z0\.s, z0\.s, z0\.s
*[0-9a-f]+: 45c09400 eortb z0\.d, z0\.d, z0\.d
- *[0-9a-f]+: 057b16b1 ext z17\.b, {z21\.b, z22\.b}, #221
- *[0-9a-f]+: 05600000 ext z0\.b, {z0\.b, z1\.b}, #0
- *[0-9a-f]+: 056003e0 ext z0\.b, {z31\.b, z0\.b}, #0
+ *[0-9a-f]+: 057b16b1 ext z17\.b, {z21\.b-z22\.b}, #221
+ *[0-9a-f]+: 05600000 ext z0\.b, {z0\.b-z1\.b}, #0
+ *[0-9a-f]+: 056003e0 ext z0\.b, {z31\.b-z0\.b}, #0
*[0-9a-f]+: 645096b1 faddp z17\.h, p5/m, z17\.h, z21\.h
*[0-9a-f]+: 64508000 faddp z0\.h, p0/m, z0\.h, z0\.h
*[0-9a-f]+: 64908000 faddp z0\.s, p0/m, z0\.s, z0\.s
@@ -480,12 +480,12 @@ Disassembly of section \.text:
*[0-9a-f]+: 45407400 smullt z0\.h, z0\.b, z0\.b
*[0-9a-f]+: 45807400 smullt z0\.s, z0\.h, z0\.h
*[0-9a-f]+: 45c07400 smullt z0\.d, z0\.s, z0\.s
- *[0-9a-f]+: 052d96b1 splice z17\.b, p5, {z21\.b, z22\.b}
- *[0-9a-f]+: 052d8000 splice z0\.b, p0, {z0\.b, z1\.b}
- *[0-9a-f]+: 056d8000 splice z0\.h, p0, {z0\.h, z1\.h}
- *[0-9a-f]+: 05ad8000 splice z0\.s, p0, {z0\.s, z1\.s}
- *[0-9a-f]+: 05ed8000 splice z0\.d, p0, {z0\.d, z1\.d}
- *[0-9a-f]+: 052d83e0 splice z0\.b, p0, {z31\.b, z0\.b}
+ *[0-9a-f]+: 052d96b1 splice z17\.b, p5, {z21\.b-z22\.b}
+ *[0-9a-f]+: 052d8000 splice z0\.b, p0, {z0\.b-z1\.b}
+ *[0-9a-f]+: 056d8000 splice z0\.h, p0, {z0\.h-z1\.h}
+ *[0-9a-f]+: 05ad8000 splice z0\.s, p0, {z0\.s-z1\.s}
+ *[0-9a-f]+: 05ed8000 splice z0\.d, p0, {z0\.d-z1\.d}
+ *[0-9a-f]+: 052d83e0 splice z0\.b, p0, {z31\.b-z0\.b}
*[0-9a-f]+: 4408b6b1 sqabs z17\.b, p5/m, z21\.b
*[0-9a-f]+: 4408a000 sqabs z0\.b, p0/m, z0\.b
*[0-9a-f]+: 4448a000 sqabs z0\.h, p0/m, z0\.h
@@ -915,12 +915,12 @@ Disassembly of section \.text:
*[0-9a-f]+: 445c8000 suqadd z0\.h, p0/m, z0\.h, z0\.h
*[0-9a-f]+: 449c8000 suqadd z0\.s, p0/m, z0\.s, z0\.s
*[0-9a-f]+: 44dc8000 suqadd z0\.d, p0/m, z0\.d, z0\.d
- *[0-9a-f]+: 053b2ab1 tbl z17\.b, {z21\.b, z22\.b}, z27\.b
- *[0-9a-f]+: 05202800 tbl z0\.b, {z0\.b, z1\.b}, z0\.b
- *[0-9a-f]+: 05602800 tbl z0\.h, {z0\.h, z1\.h}, z0\.h
- *[0-9a-f]+: 05a02800 tbl z0\.s, {z0\.s, z1\.s}, z0\.s
- *[0-9a-f]+: 05e02800 tbl z0\.d, {z0\.d, z1\.d}, z0\.d
- *[0-9a-f]+: 05202be0 tbl z0\.b, {z31\.b, z0\.b}, z0\.b
+ *[0-9a-f]+: 053b2ab1 tbl z17\.b, {z21\.b-z22\.b}, z27\.b
+ *[0-9a-f]+: 05202800 tbl z0\.b, {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: 05602800 tbl z0\.h, {z0\.h-z1\.h}, z0\.h
+ *[0-9a-f]+: 05a02800 tbl z0\.s, {z0\.s-z1\.s}, z0\.s
+ *[0-9a-f]+: 05e02800 tbl z0\.d, {z0\.d-z1\.d}, z0\.d
+ *[0-9a-f]+: 05202be0 tbl z0\.b, {z31\.b-z0\.b}, z0\.b
*[0-9a-f]+: 053b2eb1 tbx z17\.b, z21\.b, z27\.b
*[0-9a-f]+: 05202c00 tbx z0\.b, z0\.b, z0\.b
*[0-9a-f]+: 05602c00 tbx z0\.h, z0\.h, z0\.h
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4e950cf70f8..1a1e1bd22f3 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3246,7 +3246,7 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
/* The hyphenated form is preferred for disassembly if there are
more than two registers in the list, and the register numbers
are monotonically increasing in increments of one. */
- if (stride == 1 && num_regs > 2 && last_reg > first_reg)
+ if (stride == 1 && num_regs > 1)
snprintf (buf, size, "{%s-%s}%s",
style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
--
2.25.1
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 42/43] aarch64: Add support for strided register lists
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
@ 2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
0 siblings, 1 reply; 46+ messages in thread
From: Simon Marchi @ 2023-03-30 15:50 UTC (permalink / raw)
To: Richard Sandiford, binutils
On 3/30/23 06:23, Richard Sandiford wrote:
> SME2 has instructions that accept strided register lists,
> such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this
> patch is to extend binutils to support such lists.
>
> The parsing code already had (unused) support for strides of 2.
> The idea here is instead to accept all strides during parsing
> and reject invalid strides during constraint checking.
>
> The SME2 instructions that accept strided operands also have
> non-strided forms. The errors about invalid strides therefore
> take a bitmask of acceptable strides, which allows multiple
> possibilities to be summed up in a single message.
>
> I've tried to update all code that handles register lists.
Hi Richard,
In a binutils-gdb build with --enable-targets=all, I get:
make[4]: Entering directory '/home/smarchi/build/binutils-gdb-all-targets/binutils'
CCLD objdump
mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-dis-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist
mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-dis-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist
mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist
mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist
mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist
mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist
collect2: error: ld returned 1 exit status
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 61afe561a12..ef59d531d17 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -1122,6 +1122,19 @@ struct aarch64_indexed_za
> unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
> };
>
> +/* Information about a list of registers. */
> +struct aarch64_reglist
> +{
> + unsigned first_regno : 8;
> + unsigned num_regs : 8;
> + /* The difference between the nth and the n+1th register. */
> + unsigned stride : 8;
> + /* 1 if it is a list of reg element. */
> + unsigned has_index : 1;
> + /* Lane index; valid only when has_index is 1. */
> + int64_t index;
> +} reglist;
Probably because this last "reglist" shouldn't be there.
Simon
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 42/43] aarch64: Add support for strided register lists
2023-03-30 15:50 ` Simon Marchi
@ 2023-03-30 16:06 ` Richard Sandiford
0 siblings, 0 replies; 46+ messages in thread
From: Richard Sandiford @ 2023-03-30 16:06 UTC (permalink / raw)
To: Simon Marchi; +Cc: binutils
Simon Marchi <simon.marchi@polymtl.ca> writes:
> On 3/30/23 06:23, Richard Sandiford wrote:
>> SME2 has instructions that accept strided register lists,
>> such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this
>> patch is to extend binutils to support such lists.
>>
>> The parsing code already had (unused) support for strides of 2.
>> The idea here is instead to accept all strides during parsing
>> and reject invalid strides during constraint checking.
>>
>> The SME2 instructions that accept strided operands also have
>> non-strided forms. The errors about invalid strides therefore
>> take a bitmask of acceptable strides, which allows multiple
>> possibilities to be summed up in a single message.
>>
>> I've tried to update all code that handles register lists.
>
> Hi Richard,
>
> In a binutils-gdb build with --enable-targets=all, I get:
>
>
> make[4]: Entering directory '/home/smarchi/build/binutils-gdb-all-targets/binutils'
> CCLD objdump
> mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-dis-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist
> mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-dis-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist
> mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist
> mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): reglist
> mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc-2.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist
> mold: error: duplicate symbol: ../opcodes/.libs/libopcodes.a(aarch64-opc.o): ../opcodes/.libs/libopcodes.a(aarch64-dis.o): __odr_asan.reglist
> collect2: error: ld returned 1 exit status
Yeah, I've just pushed a patch for this. Sorry for the breakage.
Richard
>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>> index 61afe561a12..ef59d531d17 100644
>> --- a/include/opcode/aarch64.h
>> +++ b/include/opcode/aarch64.h
>> @@ -1122,6 +1122,19 @@ struct aarch64_indexed_za
>> unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
>> };
>>
>> +/* Information about a list of registers. */
>> +struct aarch64_reglist
>> +{
>> + unsigned first_regno : 8;
>> + unsigned num_regs : 8;
>> + /* The difference between the nth and the n+1th register. */
>> + unsigned stride : 8;
>> + /* 1 if it is a list of reg element. */
>> + unsigned has_index : 1;
>> + /* Lane index; valid only when has_index is 1. */
>> + int64_t index;
>> +} reglist;
>
> Probably because this last "reglist" shouldn't be there.
>
> Simon
^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2023-03-30 16:06 UTC | newest]
Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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